FPGA

¨ Array of programmable logic-blocks with programmable

interconnects
¨ Actel Programmable Gate Array
¤ Multiplexer-based logic blocks
¤ Anti-fuse technology for interconnects
¨ Xilinx Logic Cell Array
¤ SRAM-based logic blocks and interconnects

28 Digital Logic Design

 Actel programmable gate arrays
I/O Buffers, Programming and Test Logic
Rows of programmable
logic building blocks

I/O Buffers, Programming and Test Logic

I/O Buffers, Programming and Test Logic

+ ... ...
rows of interconnect

... ...
Anti-fuse Technology:
Program Once

... ...

Use Anti-fuses to build

up long wiring runs from
short segments I/O Buffers, Programming and Test Logic
Logic Module Wiring Tracks

8 input, single output combinational logic blocks

FFs constructed from discrete cross coupled gates
29 Digital Logic Design
Actel logic module
8 inputs

A S0 S1
Basic Module is a
Modified 4:1 Multiplexer
D0
2:1 MUX Example:
D1 Implementation of S-R Latch
2:1 MUX Y
R "0"
D2 1
2:1 MUX 0
D3
2:1 MUX
"0"
B
2:1 MUX Q
Y = (S0+S1)’(A’D0+AD1)+(S0+S1)(B’D2+BD3) 1
"1" 0
2:1 MUX
Q = (R’+0)’(0+0)+(R’+0)(S×1+S’Qold)
= R’(S+S’Qold) 0 1
= R’(S+SQold+S’Qold) = R’(S+Qold) S
Digital Logic Design
 Xilinx logic cell arrays

¨ CMOS static RAM technology: programmable on the fly!

¨ All personality elements connected into serial shift register
¨ Shift in string of 1's and 0's IOB IOB IOB IOB
on power up

IOB
¨ General chip architecture:
¤ IO Blocks (IOBs) CLB CLB

IOB
¤ Logic Blocks (CLBs)
¤ Wiring Channels Wiring Channels
IOB

CLB CLB
IOB

Note 4
31 Digital Logic Design
 Xilinx IO block (IOB)
Program Controlled Options
Vcc
OUT TS OUTPUT SLEW PASSIVE
INV INV SOURCE RATE PULLUP
¨ Inputs:
¤ Tri-state enable Enable
Output
¤ bit to output
¤ input, output clocks
MUX PAD
¨ Outputs: Out D Q Output
Buffer
¤ input bit
R bi-directional
Direct In
¨ Internal FFs for input
and output paths Registered In Q D
TTL or CMOS
Input Buffer
¨ Fast/Slow outputs R

¤ 5 ns vs. 30 ns rise Clocks Global Reset

¨ Pull-up used with unused IOBs

32 Digital Logic Design
 Xilinx Configurable Logic Block (CLB)

¨ 2 four-bit address SRAMs and 2 FFs

¨ Any function of 5 variables
¨ Global reset, clock, clock enable, independent DIN
Reset
DIN Mux D RD
Q
CE
Q1 Mux X
F
A
B Combinational
C Function
D Generator
E G
Q2 Mux Y
Mux D RD
Q
Clock Mux CE
Clock
Enable
33 Digital Logic Design
 Combinational Function Generator
Q1
A
B Mux
Function
C Mux of 4 F
Q1 Variables
D Mux
A E
B Mux F Q2
Function
C Mux of 5 Q1
Variables
D G A
E B Mux
Function
Q2 of 4 G
C Mux
Variables
Any function of 5 variables D Mux
E
Q2
Two independent functions
of 4 variables each
34 Digital Logic Design
 Implementation examples with CLBs

¨ Ex1: n-input majority circuit

¤ Assert 1 whenever n/2 or
greater inputs are 1 7-input Majority Circuit

CLB
5-input
Majority Circuit CLB CLB

CLB

¨ Ex2: n-input parity functions

¤ 5 input = 1 CLB, 2 Levels of CLBs 9 Input Parity Logic
yield up to 25 inputs! CLB

CLB

35 Digital Logic Design

 Implementation examples with CLBs

¨ Ex3: 4-bit binary adder A3 B3 A2 B2 A1 B1 A0 B0 Cin

¤Full adder
è 4 CLB delays to carry out
CLB CLB CLB CLB

Cout S3 C2 S2 C1 S1 C0 S0

¤2 ´ two-bit adders (3 CLBs each) A3 B3A2B2 A1 B1A0B0Cin

è yields 2 CLBs to final carry out

CLB S2 CLB S0
S3 S1
Cout C1

36 Digital Logic Design

 Xilinx wiring channels for interconnect
Direct
Connections
¨ Direct connections
DI CE A DI CE A
¨ Global long line B
C CLB0
X B
C CLB1
X
K Y K Y
¨ Horizontal/Vertical E D R E D R
Horizontal
long lines Long Line

¨ Switching matrix Switching

Matrix
connections Horizontal
Long Line
DI CE A DI CE A
B X B X
C CLB2 C CLB3
K Y K Y
E D R E D R

Vertical Global
Long Lines Long Line

37 Digital Logic Design

Xilinx application: BCD to excess 3 FSM

¨ Logic equations

Q2+ = Q2’ Q0 + Q2 Q0’

Q1+ = X’ Q2’ Q1’ Q0 + X’ Q2’ Q0’ + X Q2’ Q0 + Q1’ Q0
Q0+ = Q0’
Z = X Q1 + X’ Q1’

¨ Synchronous Mealy machine

¨ No function has more than 4 variables + 4 FFs implies 2 CLBs
¨ Global Reset to be used
¨ Place Q2+, Q0+ in one CLB and Q1, Z in the second CLB
à maximize use of direct & general purpose interconnections

38 Digital Logic Design

 Implementing the BCD to excess 3 FSM
Clk Clk
Q2+ = Q2’ Q0
X + Q2 Q0’
Q1+ = X’ Q2’ Q1’ Q0
+ X’ Q2’ Q0’
CE + X Q2’ Q0
CE A CE A
+ Q1’ Q0
DI X DI X X Q0+ = Q0’
Q2 Q2 Q2 Q1
FG FG Z = X Q1 + X’ Q1’
B Q0 Q1
B Q0
C C
Y X Y
Q0 Q0 Q1 Z
K FG K FG
E E
D RES D RES
CLB1 CLB2

39 Digital Logic Design

 Case study: traffic light controller

¨ A busy highway is intersected by a little used farmroad

¨ Detectors C sense the presence of cars waiting on the farmroad
¤ with no car on farmroad, light remain green in highway direction
¤ if vehicle on farmroad, highway lights go from Green to Yellow to Red,
allowing the farmroad lights to become green
¤ these stay green only as long as a farmroad car is detected but never
longer than a set interval
¤ when these are met, farm lights transition farm road
from Green to Yellow to Red, allowing car sensors
highway to return to green
¤ even if farmroad vehicles are waiting,
highway gets at least a set interval
highway
as green

40 Digital Logic Design

 Case study: traffic light controller

¨ Assume you have an interval timer that generates:

¤ a short time pulse (TS) and
¤ a long time pulse (TL),
¤ in response to a set (ST) signal.
¤ TS is to be used for timing yellow lights
and TL for green lights
¨ Decomposition into primitive subsystems
¤ Controller FSM: next state/output functions, state register
¤ Short time/long time interval counter
¤ Car Sensor
¤ Output Decoders and Traffic Lights

41 Digital Logic Design

 Block diagram of the traffic light system
Inputs
TL,TS,C
Outputs
ST,H1H0,F1F0

TS TL ST discussed in Note 7

H1H0

C F1F0

42 Digital Logic Design

 Implementing 3 sub-blocks

43 Digital Logic Design

 Tabulation of I/Os and states

¨ Tabulation of inputs and outputs

inputs description outputs description
reset place FSM in initial state HG, HY, HR assert green/yellow/red highway lights
C detect vehicle on the farm road FG, FY, FR assert green/yellow/red highway lights
TS short time interval expired ST start timing a short or long interval
TL long time interval expired

¨ Tabulation of unique states – some light configurations

imply others
state description
HG highway green (farm road red)
HY highway yellow (farm road red)
FG farm road green (highway red)
FY farm road yellow (highway red)

44 Digital Logic Design

 Implementing Next state/Output logic
¨ State assignment: HG=00, HY=10, FG=01, FY=11
P1 = CTLQ1’ + TS’Q1Q0’ + C’Q1’Q0 + TS’Q1Q0
P0 = TSQ1Q0’ + Q1’Q0 + TS’Q1Q0
ST = CTLQ1’ + C’Q1’Q0 + TSQ1Q0’ + TSQ1Q0
H1 = TSQ1Q0 + Q1’Q0 + TS’Q1Q0
H0 = TS’Q1Q0’ + TSQ1Q0’
F1 = Q0’
F0 = TS’Q1Q0 + TSQ1Q0

¨ PAL/PLA implementation
¤ 5 inputs, 7 outputs, 8 product terms
¤ PAL 22V10 – 12 inputs, 10 prog. IOs, 8 to 16 prod terms per OR
¨ ROM implementation
¤ 32 word by 8-bit ROM (256 bits)
¤ Reset may double ROM size
45 Digital Logic Design
 Another way to build Next state logic

¨ Counter-based Implementation
¨ HG=00, HY=01, FG=10, FY=11

state transitions
state transitions

46 Digital Logic Design

 Another way to build Output logic

¨ Output logic directly connected to Light decoder

¨ Dispense with direct output functions for the traffic lights

HG=00, HY=01, FG=10, FY=11

47 Digital Logic Design

 Sequential logic implementation

¨ Models for representing sequential circuits

¤ Finite state machines and their state diagrams Notes 5 & 6
¤ Mealy, Moore, and synchronous Mealy machines
¨ Finite state machine design procedure
¤ deriving state diagram & state transition table
¤ assigning codes to states Note 7
¤ determining next state and output functions
¤ implementing combinational logic
¨ Implementation technologies
¤ Random logic with flip-flops
Note 8
¤ PLA/PAL/ROM with flip-flops
¤ FPGA
48 Digital Logic Design