B.Tech. TSS anate MINATION VLSI DESIGN Time : 2 Hours Note. Attempt all questions.Each question carries equal marks. Q.1. Attempt any two parts of the following: (S*4=20) (© What are the advantages of polysilicon gate technology over metal gate? How is it fabricated? ‘Ans, Advantages of Potysiticon Gate: (0 It is used to provide conducting lines between devices and gates in fabrication of IC. (ii It has electrical isolation properties, hence can be used as inerlevel dielectric, (i) This has stability at polysilicon — SiO, interface at high temperature: Fabrication: The oxidation of the Si- substrate is done by creating a thick SiO, layer fon the surface. Then the field oxide is selectively etched to expose the Si-surface on which the MOS transistor will be created. Following ths step, the surface is covered with them, high quality oxide layer which will ‘eventually form the gate oxide layer ofthe MOS transistor. On top of the their oxide layer, a layer ‘of polysilicon is deposited. It is used both as ‘gate electrode material for MOS transistor and also as an interconnect medium in Si ICs. After deposition, itis patterned and etched to form the interconnects and MOS gate. SiO(b) Sketch the cross section of a p- channel enhancement MOSFET. Explain the operation and draw the characteristics of the device. ‘Ans. P-Channel Enhancement MOSFET: CIS Characteristics: Ip (ma) ~2-1 Vr Vos ‘Transfor Charact, ty (may Vos=-6V -5V -av -3v Yos Drain Characteristics: Source Gate Drain (At Veg" 0, and Vpg is applied, 1g = 0. (i At Vos (~ ve) potential, drain and gate are at (~ ve) potential w.tt source. The (- ve) ‘poential at gate will pressure the e's in the n- substrate along the edge of the SiO, layer to leave the area and enter deeper regions of n- ‘substrate. The result is depletion region near the SiO, insulating layer void of e's. The holes in the n-substrate will be attracted to (— ve) gate ‘and sccumulate in the region near the surface of SiO, layer. Due to insulating properties of Si0,, prevents the (+) ve carriers to be absorbed at the gate terminal’ Mss alt (iti As Vigg= more (~ ve), the concentration of holes near SiO, surface increases until the induced fiole type region can support a measurable flow between D&S. The level of Veg that results in significant increase in Ip is called threshold voltage (V;). (AC ve) Veg above V; induces a channel and hence 1, by creating a the layer of (+) ve changes. The conducting of channel is enhanced by Vog and thus pulling more holes into the channel. (© Explain the processing steps of n- well process of CMOS fabrication with suitable diagram. Is n-well CMOS circuit superior to p-well MOS circuits? Justify your answer, ‘Ans. n-well process (CMOS): n-well process are superior to p-well because of the lower substrate bias effects on transistor threshold voltage and inherently lower parasitic capacitances associated with source and drain regions.CIS View: Ye Yoo Vou Ves ta ow Prsubstrato Processing Steps: Fomaton of vl rons Define wQ0S POS active aren Field & ate oxidation Ferm per poy p+ diffusion + 1+ diffusion Contact cuts + Deposit & pattern metallization + ‘Over glass with cuts for bonding pads Q2. Attempt any two parts of the following: (6x2=10) (@) Describe the operation of a basic nMOS inverter. Aiso draw and explain the transfer ‘characteristics of nMOS inverter. What are differences between the real inverter and the ideal inverter? Ans.n OS Inverter: For very low input voltages, the Vay is equal to the high value of Vyp the driven MOS transistor isin cut off and hence does not conduct. The voltage drop across the load device is very small in magnitude and the outut level is high.‘As Vey increases, the driver transistor starts conducting a certain drain curret and the output voltage eventually starts to decrease. This drop in the voltage level does not occur abruptly, such 4 in ideal inverter VTC, but rather gradually and with finite slope. ‘As the inpat voltage further increased, the Vy At continues to drop and reaches a valve OF Voy, when the input voltage is Voy In ideal inverter, the fall of the voltages is abrupt if input voltage DS Vig < Vy is iterpreted as logic ‘0° whereas Vy Vq SV is logic ‘1°, The output voltages for above are logic “1° and logic ‘0” resp. tn actual inverter any input voltage level between the lowest available voltage (usually the syound potential) and V,, is interpreted as logic “0', while any input voltage between highest available voltage (usually power supply voltage) ‘and Vy is considered as log ‘1’. The output for ‘above levels are any output voltage level between the highest available voltage in the system and Voy is interpreted as logic 1° whereas any output voltage between the lowest available voltage and Vo is considered as logic ‘0°. Yoo s— ves (pul down) (©) Draw the circuit diagram for NAND gale. Discuss its working. Also show the stick diagram and tayout for two input NAND gate in aMOS design style. ‘Aus. NAND Gate: urs VA VB Vout tow low high low high high high low high high high low Ifthe input voltage V,and V, are logic high, both transistors are ON ‘and the output voltage is low. Else, if ether one or both of the drive ‘transistor are off the output voltage will be Palle to logic high by load transistor. (©) What do you mean by scaling? What are the differnet scaling models? Explain thems. List the limitations of sealing. ‘Ans. Scaling: ‘The reduction of the size i the dimensions of MOSFETs is commonly refered to as scaling. It is concerned with systematic reduction of overall dimension ofthe device as allowed by the available technology, Of internal electric fields in the MOSFET while the dimensions are scaled down by a factor of S. (i) Constant Voltage Scaling: All dimensions of the MOSFET are reduced by &factor of ‘S* whereas the power supply voltage and the terminal voltages, on the other hand remain ‘unchanged. Before Sealing ‘After Sealing "Fall Sealing Constant Volinge @ Channel length us us (i) Channel width ws ws Gili) Gate Oxide thickness foxs fox. Gv)_umetion depth, xfs fs (0) Power supply voltage Yous Yoo (vi) Threshold voltage Vygis Yo (vil) Doping density SNe SNp Limitations: (0 Substrate doping effect is neglected. (@) Limits of miaturization. (Gi) Limits of interconnect and contact resistance. (@) Limits due two substhreshold currents. (©) Limits on logic levels and supply voltage duc to noise. . (Limits due to current density. Q.3. Attempt aay two parts of the following: (Sx2=10) (@) Describe the Lambda based design rales. Explain why is it required? ‘Ans. Lambda Based Design Rules: ‘These are required to achieve for any circuit to be manufactured with a particular process, a hhigh overall yield and reliability while using the smallest possible Si area. ‘These design rules specify the layout constraints in terms of a single parameter (X) and allow linear, proportional scaling of all geometrical constraints. It was devised to simplify the industry std micron besed design rules and to allow scaling capability for various processes. ‘Active Area rales Contact Ries Min active area width =~ 32 Poly contact size -2 Min active area spacing ~ 32. Min poly contact spacing — 24 Poly Rietes ‘Active Contact size “2 Min poly width “2 Min active contact spacing ~ 24 Min poly spacing “2 Min gate extension of polyover active - 22 Min poly active edge spacing “a Metal Rules Min metal width = — 32 ‘Min metal Spacing — 32. (©) What is pass transistors? Discuss the property of a pass transistor. Draw the switch logic arrangements to implement the functioas: @F=A-B-C(G=A+B4C asing pass transistors. ‘Ans. Pass Transistor: It uses a purely nMOS pass transistor network forthe logic operations instead of CMOS TG network. All inputs are applied in complementary form i.e. every input signal and its inverse must be provided. ‘The CPL circuit eisentially consists of complementary inputs, an nMOS pass transistor logic to ‘generate complementary outputs and CMOS output inverters to restore the output signals. Properties: (@ thas reduced parasitic capacitances, associated with each node in the circuit. (ii) High speed compared to full CMOS. (ii) Increased process complex (i) The V; of nMOS transistor in pass gate network must be reduced to about OF in order to celminate the ¥; drop. (») Reduced overall noise immunity. (*0 Highly modular design. (vit) Wide range of functions can be realized using same basic pass transistor structures. F=A 3 (aBcy (asc)G=(A+B+OQ casey (asBecy ABC (© Name the various design techniques. Describe the “cell based design”. List the various standard Wbrary cell ‘Ans, Varlous Design Techniques: (i Field programmable gate array (if) Gate Array Design (iii) Standard cell based design (is) ull custom design Oono0000 Std Rell Row: Fouling channel Oo a Qa a a Routing channel G a Oo Rlouting channel oo00000(Cell Based Design: The std cells also called polycell. In this style, all ofthe commonly used logic cels are developed, characterized and stored in a std cel library. Each gate can be implemented in several versions to provide adequate driving capability for different fan-outs. ‘To enable automated placement of the cells and routing of inter cell connectios, each cell layout is designed witha fixed height, soi that a number of cells can be abutied sie by side to form rows. “The power and ground rails run parallel to the upper and lower boundaries of the cell. The input and output pins are located on the upper and lower boundaries of the cel ‘The chip area contains rows or columns of standard cells. Between cell rows and channels for dedicated intercell routing. The logic cells are placed into rows, their heights are matched and eighboirng cells can be abuted side by side. Std cell based design may consist of macro blocks, cach coresponding to a specific unit ofthe system architecture. Libraries: (2 verter, (i) NAND gates, i) NOR gates, (v) Complex AOI gates, (v) DAL gates (vf) D- Iatches, (i) ip flops. Q-4. Attempt any two parts of the following: (Sx2=10) (@) What are the different types of memory cells? Explain the operation of any one of ‘them. ‘Ans. Memory Cells: =o mene i orn ay on (RAM) 1 a NN — Mask ROM Dynamic RAM ‘Static RAM — Programmable ROM (PROM) ae oan Poem toe res ee eo car elon tee It consists of ross coupled MOS inverters. I is addressed by seting Ay = Ay= 1. When Ay = 1 the cells conneced tothe data and Gat line. When 4, T&T are ON. ‘To ite into cll set w= 1, Ty becomes ON. If data input is“ the voltage at ‘D* wll corespond to level-1 making T; ON and level at D will be 6’, Ifthe data input is at logic ‘0°, then T, will be offand D would be at “1.Data input ‘To read the state of the flip-flop, set R= 1. This connects the data output to 5. Thus the complement of the data level written into the cell is read at data output. (®) What do you understand by full custom design? How is it differ from semi custom design? Explain. ‘Ans, Full Custom Design: In this design, the entire mask design is done a new without use of any library. The development cost of such design style is high. The concept of design reuse is ‘becoming popular in order to reduce design cycle time and development cost. The rigorous full ‘custom is design of memory cells. In this design the geometry, orientation and placement of every transistor is done individually bby the designer, design productivity is usually very low - typically a few tens of transistors/day, per desiner. In semicustom design, all ofthe logic cells are predesigned and some (possiblyall) of the mask layers are customized. In full custom all the logic cells are customized and all mask layers are customized, Full custom is most expensive to manufacture and to design as compared to semicustom. (© What are PLDs? Discuss the advantages and disadvantages of PLDs. Explain, ‘Ans. PLS: These are standard ICs that are available in standard configurations from a catalog of parts and are sold in very high volume to many different customers.Oj oO q QO oO a Oo Macro cal OOOODOOOO pouudouoooO Gl PLDs may be configured or programmed to create a part customized to a specific application. Advantages: (0 No customized mask layers on logic cells. (Go Fast design tumaround and more flexible. (it) A single logic block of programmable interconnect. (0) A matrix of oie macrocells that usualy consists of PAL followed by a flip-flop oF latch By using these programmable devices in a large array of AND gates and an array of OR gates, a new flexible and programmablic logic devices called logic arrays are created. Disndvanage: (0 They are programmed to create a part customized to a specific application Q5. Attempt any two parts of the following: (2-10) (a) Discuss briefly testing of VLSI circuits. ‘Ans, Testing of VLSI Circuits: Chip testing in the conventional sense, is a multi-purpose and attempts to detect faults in fabrication design and failures due to the stressful operating conditions, ‘namely the reliability problems. Input test vectors are devised and applied to the DUT or circuit ‘under test (CUT) as its stimuli. Then the measured outputs are compared with the expected correct responses to determine whether DUT (device under test) is good or lead. The main difficulty in testing is that only input and output pins of DUT are accessible, although atthe test bench in the development lab, the internal nodes of unpackaged chips ean be probed atthe topmost metal level before passivation is done. As the operating clock check frequencyof the chip increases the speed test has also become difficult problem. Different testing techniques: (0 AGHOC Testable Design technique. (i) Scan Based Techniques(Gi) Built in set test (Gv) Current Monitoring Ippo test. (b) What do you mean by stuck-at UO fault? Explain testing ofa logie gate with suitable example. ‘Ans. Stuck at Input Faults: These are logical faults. These are stuck at 0 or stuck at I faults. ‘When the resistance is low or a pull up delay fault when the resistance is high. A S20 whan resistance is low or a pull - 2. > up dolay fault when the resis- 8 tance is high. ‘When some part of the input line is shorted to the power ral, then S-#-1 can happen. ‘-A-0 or S-A-1 faults most frequently occur due to their oxide shorts or metal to metal short. A A 8. 8 <= ong ‘out —e > Sat SAO ‘Testing Logic Gate: Taking a example of NOR gate (8) A metallic blob (physical defect) between the common drain terminal in the n-diffusion region and the ground bus can be modeled as a resistive short between the output node Z and the ground and also by a stuck-at-O (S-8-0) faults of output Z when the resistance is low or pull up delay fault when the resistance is high. (©) What do you understand by FPGAs? Discuss the various advantages and applications of FPGAs. ‘Ans. FPGAs: Fully fabricated FPGA chips contain tens to hundreds to thousands or even more of logic gates with programmable interconnencts, are available to users for their custom hardware programming to realize desired functionality, cus oo 00),00,, 09, re 8 ff [lo [Oo 8 Block Bio fo fo 8 Bio 8 Bio 8 tooteatt eat oo! i Horizontal Routing ChannelIt consists of VO buffers, an array of configurable logic blocks (CLBs) and programmable nterconnect structures. The programming of the interconnects is accomplished by programming of LAM cells whose output terminals are connected to the gates of MOS pass transistors. The signal coting between the CLBs and the input block is accomplished by setting the configurable switch natrices accordingly. ‘Advantages: () Short tur around time .¢ the time required from the start of the design process ‘mil a functional chip is available. - (i No physical manufacturing step is necessary only a functional sample can be obtained 2s ‘oon as the design is mapped into a speciic technology. (iii) Fast prototyping. (Gv) Cost effective chip design for low volume applications. (») Much large. Disadvantage: ( More complex. (i) Typical price of FPGa chips is usually higher.