VHDL and Simulation

History of VHDL

• <1985: various tools for circuit design; many were in-house tools

• The problem of DoD

‒ Long hardware life cycle vs. short-term product support

• 1981: Very High Speed Integrated Circuits (VHSIC) program

• 1983-85: Development of baseline language by Intermetrics,

IBM and TI

• 1987: VHDL (VHSIC Hardware Description Language), IEEE

Standard 1076-1987

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VHDL: A Hardware Description Language

Synthesis of a multiplexer
A 0
Specification: If Sel = 0, Q
Q=A; B 1
Else
Q=B; Sel

EDA
Tools PROCESS (A, B, Sel)
Nand_a BEGIN
S1
A
Inv
 Nand_c
IF Sel=‘0’ THEN
Sel  Q <= A;
Seln  Q ELSE
Q <= B;
B

S2 END IF;
Nand_b END PROCESS;

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VHDL Simulation with Delays

PROCESS (A, B, Sel)

BEGIN
• Delays cannot be fixed when
IF Sel=‘0’ THEN
writing VHDL code.
Q <= A after 5ns;
ELSE • Synthesis tools ignore all delays.
Q <= B after 2ns;
END IF;
END PROCESS;

A 1
0
B 1
0
Sel 1
0
Q 1
0

0 10 12 20 30 40 t(ns)

4
VHDL Simulation without Delays

PROCESS (A, B, Sel)

Nand_a
BEGIN A 
S1
IF Sel=‘0’ THEN Sel 
Inv Nand_c
Q <= A; Seln  Q

ELSE 
B S2
Q <= B;
Nand_b
END IF;
END PROCESS;

A 1
0
B 1
0
Sel 1
0
Q 1
0

0 10 20 30 40 t(ns)

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Naïve Execution Order of Multiple Processes

A C=AB=AA

B=A
P1: PROCESS (A) P2: PROCESS (A, B)
BEGIN BEGIN
B <= not A; C<=A and B;
END PROCESS; END PROCESS;

A 1 A 1
0 P1 0 2 P1 1 P2

B 1 B 1
0 0 3 P2

C 1 C 1
0 0
0
no change
0 10 20 t(ns) 0 10 20 t(ns)

P1P2 P2P1P2

• Process execution order does not affect simulation results.

• VHDL standards do not specify the execution order of processes.
6
VHDL Description of Flip-flop

A B
PROCESS (clk)
D Q BEGIN
IF clk’event and clk=‘1’ THEN
clk B <= A;
END IF;
END PROCESS;

A 1
0
clk 1
0
no change change at clock edge
B 1
0

0 10 20 30 40 t(ns)

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VHDL Description of Multiple Flip-flops

P1: PROCESS (clk) P2: PROCESS (clk)

BEGIN BEGIN
IF clk’event and clk=‘1’ THEN IF clk’event and clk=‘1’ THEN
B <= A; C <= B;
END IF; END IF;
END PROCESS; END PROCESS;

A B C
D Q D Q

clk

The clock signal (clk) reaches all flip-flops at the same time.

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 Naïve Simulation of Multiple Flip-Flops

P1: PROCESS (clk) P2: PROCESS (clk)

BEGIN BEGIN
IF clk’event and clk=‘1’ THEN IF clk’event and clk=‘1’ THEN
B <= A; C <= B;
END IF; END IF;
END PROCESS; END PROCESS;

A 1 A 1
0 0
clk 1 clk 1
0 1 P1
0 4 P1, no change
P1
B 1 B 1
2
0 0 3 P2
1 2 P2 1
C C 1 P2, no change
0 0
0 10 20 30 40 t(ns) 0 10 20 30 40 t(ns)

P1P2 P2P1

Processes are activated by the rising edge of the clk signal.

Process execution order does affect simulation results.
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 Implicit Delay

A 1 A 1
0 0
clk 1 clk 1
0 1 P1
0 4 P1, no change
P1
B 1 B 1
2
0 0 3 P2
1 2 P2 1
C C 1 P2, no change
0 0
0 10 20 30 40 t(ns) 0 10 20 30 40 t(ns)

P1P2  P2P1 
Implicit delay: a change at B cannot reach B′ instantly.

A B B′ C
D Q D Q

clk

The clock signal (clk) reaches all flip-flops at the same time.

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 Implicit Delta Delay
Implicitly added by the simulator

P1: PROCESS (clk) P2: PROCESS (clk)

BEGIN BEGIN
IF clk’event and clk=‘1’ THEN IF clk’event and clk=‘1’ THEN
B <= A after ; C <= B after ;
END IF; END IF;
END PROCESS; END PROCESS;

A 1 A 1
0 0
clk 1 clk 1
0 1 P1
0 4 P1, no change
P1
B 1 B 1
2
0 B changes at 10+ 0 10+ 3 P2
1 2 P2 1 1 P2, no change
C C
0 0
0 10 20 30 40 t(ns) 0 10 20 30 40 t(ns)
no change C changes at 30 + C changes at 30+
P1P2 P2P1
•  is an imaginary delay equal to 0.
• Signals (with the assignment “<=“) without explicit delay
are updated after one  delay.
• The  delay helps maintain consistent simulation results.
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 Mismatch between Simulation and Circuit due to  Delay

P1: PROCESS (clk_1) P2: PROCESS (clk_2)

BEGIN BEGIN
IF clk_1’event and clk_1=‘1’ THEN IF clk_2’event and clk_2=‘1’ THEN
B <= A; C <= B;
END IF; END IF;
END PROCESS; END PROCESS;
A B C
P3: clk_2 <= clk_1; --Clock assignment D Q D Q

A 1 clk_1=clk_2
0
Clk_1 1 A 1
0 clk_2 changes at 10+
1 0
Clk_2 0 Clk_1 1
Clk_2 0
B 1 B 1
0 B changes at 10+ 0
1 1
C C
0 C changes at 10+2 0
0 10 20 30 t(ns) 0 10 20 30 t(ns)

This mismatch can only be avoided by using the clock signal carefully.
12
 Adding Delays to Avoid Mismatch?

P1: PROCESS (clk_1) P2: PROCESS (clk_2)

BEGIN BEGIN
IF clk_1’event and clk_1=‘1’ THEN IF clk_2’event and clk_2=‘1’ THEN
B <= A after 5ns; C <= B after 5ns;
END IF; END IF;
END PROCESS; END PROCESS;
A B C
D Q D Q
clk_2 <= clk_1; --Clock assignment

clk_1=clk_2
A 1 A1
0 0
Clk_1 1 Clk_1 1
0 clk_2 changes at 10+ 0
1 1
Clk_2 0 Clk_2 0
B 1 B changes at 15 B1 B changes at 9
0 0
1 no change at 10 1
C C
0 0
0 10 20 30 t(ns) 0 2 4 6 8 10 12 14 16 t(ns)
C changes at 35 C changes at 17

Clock period = 20 Clock period = 4

13
Mismatch due to Incomplete Sensitivity List

PROCESS (A) A
C
BEGIN B
C <= A xor B;
END PROCESS; Circuit to describe

A 1 A 1
0 0
1 1
B B
0 0
1 1
C 0 C 0
0 10 20 30 t(ns) 0 10 20 30 t(ns)

Synthesis tools still generate the correct circuit  Mismatch.

14
Event-driven Simulation
Execution of all transactions at time step tn in Δ-cycles. Advancing the simulation time tn → tn+1 ,
when all transactions at time tn have been executed.

Δ-cycle:

• Signal-Update-Phase:

- Execution of all transactions for the current time step.

- If a transaction changes a signal value, this is an event.

• Process-Evaluation-Phase:

- Processes, for which an event is present, will be executed.

- Value assignments to signals will be scheduled.

Signal- Signal-
Update Update
+Δ +Δ
Process- Process-
Evaluation Evaluation

tn tn+1 time
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Transport Delay
Modeling of an ideal component with unlimited bandwidth.

ENTITY inverter IS
PORT (
inp : IN std_logic;
outp : OUT std_logic);
END inverter;

ARCHITECTURE delayMechanism OF inverter IS

BEGIN
outp <= TRANSPORT NOT inp AFTER 10 ns;
END ARCHITECTURE;

inp

inp outp
outp

ns
5 10 15 20 25 30 35

16
Inertial Delay
Modeling of real components with finite bandwidth.
(Pulses, which are shorter than the component’s delay, will be suppressed.)
ENTITY inverter IS
PORT (
inp : IN std_logic;
outp : OUT std_logic);
END inverter;

ARCHITECTURE delayMechanism OF inverter IS

BEGIN
outp <= INERTIAL NOT inp AFTER 10 ns;
END ARCHITECTURE;

inp

inp outp
outp

ns
5 10 15 20 25 30 35

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Delays in VHDL

• Simulator generates signal waveforms according to hardware description

and delays.
• But delays are ignored by EDA tools in synthesizing circuits:
o delay units are very difficult to implement accurately in silicon;
o delays are random variables with bounds due to process variations;
o sizing and library flexibility.
• In practice, designers describe circuit structure and function using HDL
without delays.
• Static timing tools report whether a design can work at a given clock
frequency.

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Thanks!

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