The 5th International Conference on Electrical Engineering – Boumerdes (ICEE-B)

October 29-31, 2017, Boumerdes, Algeria.

Design and Implementation of Three-Level Inverter

for Grid-tied PV Systems
Ayachi Amor Yacine, Ayachi Amor Noureddine, Kheldoun Aissa, Metidji Brahim
Signals and Systems Laboratory
Institute of Electrical and Electronic Engineering, University M’hamed Bougara of Boumerdes
Boumerdes, Algeria
[email protected], [email protected],[email protected], [email protected]

Abstract—High quality voltage and current are required when using either DSP card [5] or Dspace platform [6, 7] which
PV generator is connected to grid utility. To this, multilevel increase the cost of the PV system. The paper investigates the
inverters are very desirable to be used as connection interface. To
keep the cost of the whole system as low as possible, a cost- use of a cost-effective card, STM32F4 board, to implement
effective control device using STM32F4 discovery board is the control system without affecting much the cost of the
employed to control three-level inverter that can be used in grid- grid-tied PV system.
tied PV system. The paper develops and implements the control
strategy of simplified space vector pulse width modulation The paper is organized as follows: section II illustrates
(SVPWM) algorithm using Matlab/Simulink software. Obtained the modeling of the PV generator, section III is devoted the
experimental results depict the powerfulness of used card as well
as the high quality of the delivered power. structure of three-phase three-level NPC inverter while
section IV and V explain in details the principle of SVM
Keywords-PV system; Three-level inverter; Simplified SVM; technique with simplified algorithm. Finally, section VI
STM32F4; Implementation.
demonstrates the implementation part of the proposed system.
Conclusion is given in section V.
I. INTRODUCTION
II. PV GNERATOR
The energy demand increases with the same rate as the
The electrical equivalent circuit of PV module is
population increase as well as the technology development.
composed of a current source, a diode, a parallel connected
Besides exhausting of fossil fuels and negative effects of resistor, and a serial resistor which results in the circuit as seen
nuclear fuels, tendency of generation energy nearby location, in Fig. 1 [8, 9].
where it is consumed, to decrease the transmission losses and
improve the energy reliability has increased interest on
renewable energy sources (RESs) [1].

Solar energy is one of the most important RESs with its

superior advantages such as being inexhaustible energy
Figure 1. Electrical equivalent circuit of PV cell.
source, accessible nearly all around the world, pollution free
operation and little maintenance requirement. Solar energy is The mathematical model that predicts the current
converted to DC electrical energy via photovoltaic (PV) production of the PV cell becomes an algebraically simply
modules. This PV system can operate either in standalone model, being the current-voltage relationship defined in Eq.
mode, grid interactive mode or hybrid mode. Since most of the (1).
loads and public grid are AC, an inverter is required that
§ V  I . Rs · V  I .R (1)
convert the DC power generated from the PV array to the AC I I pv  I s ¨ e Vt  1¸  s
¨ ¸ R
load and/or grid interactive [2, 3]. © ¹ sh

Where:
There are two categories into which inverters can be Ipv : PV cell output current, A
classified are two level inverters and multilevel inverters. In Vpv : PV cell output voltage, V
this paper, owing to its advantages in terms of power quality Iph : the photocurrent due to incident sunlight, A
and simplicity with respect to two-level, NPC three-level Is: The reverse saturation or leakage current of the diode, in A
inverter is retained [4]. Similar systems are implemented Vt: thermal voltage ( Vt N s KT /(aq) )

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Rs, Rp,a, Ns: series resistance, shunt resistance, ideality factor difficulties, a simplified algorithm of SVM technique is
and number of series PV cells. employed to alleviate the algorithm complexity and ensure the
III. THREE-LEVEL NPC INVERTER neutral point balancing between upper and lower DC-link
capacitors [11].
The three-level NPC inverter structure is shown in
Fig 2. Each leg contains four active switches S1 to S4 with
antiparallel diodes D1 to D4. IV. SVM PRINCIPLE
The capacitors at the DC side are used to split the
Space vector modulation (SVM) is one of the preferred real-
DC input into two and provide the neutral point 0. The
time modulation techniques and is widely used for voltage
clamping diodes can be defined as the diodes connected to the
source inverters control.
neutral point, D1, D2. When switches S2 and S3 are connected,
From table 1 the three switching states [P], [O] and
the output terminal A can be taken to the neutral through one of [N] can represent the operation of the SVM technique.
the clamping diodes. The voltage applied to each of the DC Considering the operation of three lags, the inverter has 27
capacitors C1 and C2 are equals half of the total DC voltage. possible switching states. There are 24 active vectors
including 12 short vectors, 6 medium vectors and 6 long
vectors, and the remaining three are zero vectors (PPP, OOO,
NNN), which lie at the center of the hexagon as illustrated in
table 2. The area of the hexagon can be divided into six sectors
(A to F), for each has four regions (1 to 4), with 24 regions of
operation in total as shown in Fig. 3 [10].
TABLE 2. SUMMARIZE THE 27 SWITCHING STATES WITH THEIR VECTOR
MAGNITUDE.

Space Switching State Vector Vector

Vector Classification Magnitude
[PPP], [OOO], Zero Vector 0
[NNN]
[ONN], [POO]

Figure 2. The structure of three-phase NPC inverter [OON], [PPO]

Small Vector
Table 1 shows the Switching states of the NPC inverter where [NON], [OPO]
P, O and N, representing the A, B and C phase state of the [NOO], [OPP]
voltages. P means positive, O is 0 and N is negative.
[NNO], [OOP]
A terminal voltage +E/2 is performed by turning on
the switches S1 and S2 and for an output voltage equal to 0 the [ONO], [POP]
switches S2 and S3 are turned on, while the switches S3 and [PON]
S4 are used to generate an output voltage equal to – E/2, [OPN]
Medium Vector
taking into account the dc bus voltage is equal E [10, 11].
[NPO]

[NOP]
TABLE 1. SWITCHING STATES FOR A THREE-PHASE THREE-LEVEL NPC
INVERTER. [ONP]

Switching states Terminal [PNO]

S1x S2x S3x S4x voltage [PNN]
P ON ON OFF OFF E/2
O OFF ON ON OFF 0 [PPN]
Large Vector
N OFF OFF ON ON -E/2 [NPN]

[NPP]
The three-level Inverter has five levels line-to-line voltage, [NNP]
therefor lower du/dt and harmonics compared with two-level
[PNP]
inverter that has three level line-to-line voltage. This will
reduce switching stresses across power switches. However, the
complexity of the control algorithm increases and voltage
across the capacitors must be balanced. To overcome these

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 From Fig 4 m1 and m2 can be calculated as below:

(6)

(7)
(8)
And then,
If m1, m2 and (m1 + m2) < 0.5, then Vref is in region 1.
If m1 > 0.5, then Vref is in region 4.
Figure 3. Space-vector diagram of the three-level converter
If m2 > 0.5, then Vref is in region 3.
Assuming the instantaneous voltage value of three-phase sine If m1 and m2 < 0.5 and (m1 + m2) > 0.5, then Vref is in region
wave is respectively: 2 [12].

By using sector A as an example, the calculation of the on time

(2) can be demonstrated below.
Suppose Vref laying in the region 2, so it can be composed by
the three nearest vectors V1, V2 and V8 as illustrated in Fig 5.
The magnitude and angle of the rotating vector can be found During a sampling period Ts the equations for on time of the
using Clark’s Transformation Eq (3) where: voltage vectors can be given as:

(3) (9)

(4) Therefore;

Where
(10)

(5)

Where:
Where θ is computed to locate the sector to which Vref
belongs, therefore:
If θ is between 0° ≤ θ < 60°, then Vref will be in Sector A.
If θ is between 60° ≤ θ < 120°, then Vref will be in Sector B.
If θ is between 120° ≤ θ < 180°, then Vref will be in Sector C.
If θ is between 180° ≤ θ < 240°, then Vref will be Sector D.
If θ is between 240° ≤ θ < 300°, then Vref will be Sector E.
If θ is between 300° ≤ θ < 360°, then Vref will be Sector F.

Figure 5. Vector combination in sector A

Figure 4: Space vector diagram for m1 and m2 in Sector A.

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Using the same procedure, the dwelling time in other regions in V. SIMPLIFIED SVM ALGORITHM
sector A can be obtained as shown in Table 3.
The main idea of the simplified algorithm is how to achieve the
Calculation Flow based only on one sector instead of six as
TABLE 3. ON TIMES IN SECTOR A.
demonstrated in Fig. 6, just by knowing the relationships in
Dwell Time calculations and arrangement for switches between
the first sector and the others as explained below [10].

After calculating the on time, the switching sequence has to be

determined. As the converter has some redundant switching
states, the switching sequence are arranged in order to achieve
Figure 6. Calculation flow for the three-level SVPWM Simplified calculation.
low THD and balancing the DC-link capacitors.
The switching sequences in the regions of sector (A) are
arranged as follows: Suppose reference vector A stays in region 2 of sector A, while
reference vector B is obtained by rotating vector A
Region 1: PPO-POO-OOO-OON-ONN and return. counterclockwise by 60° as shown in Fig 7.
Region 2: PPO-POO-PON-OON-ONN and return.
Region 3: PPO-PPN-PON-OON and return.
Region 4: POO-PON-PNN-ONN and return.

According to switching sequences arranged in symmetrical

pattern, the PWM firing time setting for each switch in sector A
can be achieved as given in Table 4.

TABLE 4. PWM FIRING TIME SETTING FOR EACH SWITCH OF UPPER ARMS IN
SECTOR (A).
Figure 7. Two vectors with 60o shifting in the sector A and B.
So the reference vector can be expressed in the following
form.

(11)

And when the reference vector is in the other sectors, it will be

rotated to sector A by where (n=1, 2, 3, 4, 5).
The corresponding reference vector in other sectors can be
constructed as given in Table 5.

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 TABLE 5. RELATIONSHIPS OF VOLTAGES CONSTRUCTING THE REFERENCE
VECTORS IN SIX SECTORS.

Sectors Phase voltage A Phase voltage B Phase voltage

C
A Ua Ub Uc
B -Ub -Uc -Ua
C Uc Ua Ub
D -Ua -Ub -Uc
E Ub Uc Ua
F -Uc -Ua -Ub (a) (b)
Figure 12. 5 kHz gate signal generated by a TMS320F2812 DSP using the
proposed SVM technique, a) filtred and unfiltred PWM signal, (b) dead time
VI. IMPLEMENTATION AND RESULTS between two switches of the same leg.
In order to avoid the simultaneous conduction of the four
The three-level inverter is composed of three legs and each switches a dead-time, or delay of 4.7μs is implemented using
leg contain four power switches. As the signal obtained the NAND gates through the buffers in series with R=470Ω and
STM32F4 board is weak in amplitude and in order to isolate parallel with C=10nF, the introduced time delay is given by:
the control circuit from the power circuit, each power device is
equipped by gate or drive switching circuitry. Fig. 10 depicts (12)
the architecture of the system. The PWM signal generated by
the STM32F4 card control the state of inverter switches. To The complete experimental setup showing the different
ovoid short circuit within the same leg, the gate switching components of the system is shown in fig. 13.
circuit with an RC circuit to introduce the required delay.

(a) (b) (c)

Figure 10. (a) STM32F4 Discovery board, (b) Gates driving circuit, (c) (NPC)
inverter Power circuit.
Figure 13. Hardware set up for Three Phase Inverter (NPC) using STM32F4.
The source code of simplified algorithm has been written in
MATLAB Function blocks (Fig 11), compiled and uploaded on
the card. It generates three 50 Hz sinusoidal references, selects
the inverter sector and computes all switching duty cycles
based on the proposed algorithm; then it configures six PWM
generators to work at 5 kHz. The main results can be seen in
Fig 12. (a).

(a) (b)

Figure 14. (a) Line to neutral inverter voltage (Van), (b) Fundamental
component of (Van).

Figure 11. Embedded simulated model for Three Phase SVM Technique in
STM32F4 Discovery Kit in Waijung Software.

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 easy as it is compatible with Matlab/Simulink. As further work,
this experimental setup will be extended to integrate the PV
generator, MPPT algorithm and a filter in order to obtain the
grid-tied PV system.

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