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VHDL Code For A Single Traffic Light Con

This document provides a VHDL code for a single traffic light controller with a 60 Hz clock signal and asynchronous reset. The code defines the states as Red (R), Yellow (Y), and Green (G) with waiting times of 45 seconds, 5 seconds, and 45 seconds respectively. When reset, the light is set to Red. It contains an architecture with a process to handle the clock and reset signals to change the present state and a second process to set the light outputs and next states based on the present state.

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aksharaavk30
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41 views

VHDL Code For A Single Traffic Light Con

This document provides a VHDL code for a single traffic light controller with a 60 Hz clock signal and asynchronous reset. The code defines the states as Red (R), Yellow (Y), and Green (G) with waiting times of 45 seconds, 5 seconds, and 45 seconds respectively. When reset, the light is set to Red. It contains an architecture with a process to handle the clock and reset signals to change the present state and a second process to set the light outputs and next states based on the present state.

Uploaded by

aksharaavk30
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Sanzhar Askaruly Nazarbayev University, School of Engineering

Task

Write a VHDL code for a single traffic light controller. Assume you have 60 Hz clock signal. Your
design should allow asynchronous reset. When the circuit is reset, the traffic light should be Red. The
waiting times are as follows: Red (45 sec), Yellow (5 sec), and Green (45 sec).

Method

library ieee;
use ieee.std_logic_1164.all;
entity tlc is
port (
clk, reset : in bit;
r, y, g : out bit);
end tlc;

architecture behavior of tlc is


TYPE state IS (R, Y, G);
CONSTANT timeMAX : INTEGER := 2700;
CONSTANT timeR : INTEGER := 2700;
CONSTANT timeY : INTEGER := 300;
CONSTANT timeG : INTEGER := 2700;
SIGNAL pr_state, next_state : state;
SIGNAL time: INTEGER RANGE 0 TO timeMAX;
BEGIN
PROCESS(clk, reset)
VARIABLE count : INTEGER RANGE 0 TO timeMAX;
BEGIN
IF (reset = '1') THEN pr_state <= R;
ELSIF (clk'event) AND (clk = '1') THEN count := count +1;
IF (count = time) THEN pr_state <= next_state;
count := 0;
END IF;
END IF;
END PROCESS;
PROCESS(pr_state)
BEGIN
CASE pr_state IS
WHEN R => r <=’1’; y <=‘0’; g <=‘0’;
time <= timeR;
next_state <= Y;
WHEN Y => r <=‘0’; y <=‘1’; g <=‘0’;
time <= timeY;
next_state <= G;
WHEN G => r <=‘0’; y <=‘0’; g <=‘1’;
time <= timeG;
next_state <= Y;
WHEN Y => r <=‘0’; y <=‘1’; g <=‘0’;
time <= timeY;
next_state <= R;
END CASE;
END PROCESS;
END behavior;

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