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8bit UpCounter With Different Data Types

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19 views

8bit UpCounter With Different Data Types

Uploaded by

2110046346
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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8-bit Up-Counter with Different Data Types

1. Std_logic data type

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cnt8_std is
port( data: in std_logic_vector(7 downto 0);
greset,load,enable,clk: in std_logic;
cnt: out std_logic_vector(7 downto 0));
end cnt8_std;

architecture Behavioral of cnt8_std is

begin
process(greset,clk)
variable count: std_logic_vector(7 downto 0);
begin
if greset='1' then
count:="00000000";
elsif clk'event and clk='1' then
if load='1' then
count:=data;
elsif enable='1' then
count:=count+1;
end if;
end if;
cnt<=count;
end process;
end Behavioral;

2. Unsigned data type

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cnt8_unsigned is
port( data: in unsigned(7 downto 0);
greset,load,enable,clk: in std_logic;
cnt: out std_logic_vector(7 downto 0));
end cnt8_unsigned;

architecture Behavioral of cnt8_unsigned is

begin
process(greset,clk)
variable count:unsigned(7 downto 0);
begin
if greset='1' then
count:="00000000";
elsif clk'event and clk='1' then
if load='1' then
count:=data;
elsif enable='1' then
count:=count+1;
end if;
end if;
cnt<=conv_std_logic_vector(count,8);
end process;
end Behavioral;

3. Signed data type

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cnt8_signed is
port( data:in signed(7 downto 0);
greset,load,enable,clk:in std_logic;
cnt:out std_logic_vector(7 downto 0));
end cnt8_signed;

architecture Behavioral of cnt8_signed is

begin
process(greset,clk)
variable count:signed(7 downto 0);
begin
if greset='1' then
count:="00000000";
elsif clk'event and clk='1' then
if load='1' then
count:=data;
elsif enable='1' then
count:=count+1;
end if;
end if;
cnt<=conv_std_logic_vector(count,8);
end process;
end Behavioral;

4. Integer data type

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cnt8_integer is
port( data:in std_logic_vector(7 downto 0);
greset,load,enable,clk:in std_logic;
cnt:out std_logic_vector(7 downto 0));
end cnt8_integer;

architecture Behavioral of cnt8_integer is


begin
process(greset,clk)
variable count:integer range 255 downto 0;
begin
if greset='1' then
count:=0;
elsif clk'event and clk='1' then
if load='1' then
count:=conv_integer(data);
elsif enable='1' then
count:=count+1;
end if;
end if;
cnt<=conv_std_logic_vector(count,8);
end process;
end Behavioral;

oes: process (oe, cnt) -- three-state buffers


begin
if oe = ‘0’ then
cnt_out <= (others => ‘Z’);
else
cnt_out <= cnt;
end if;
end process oes;
end archcnt8;

where oes process can be replaced with the following code:

cnt_out <= (others => ‘Z’) when oe = ‘0’ else cnt;

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