An Interleaved Multi-mode ∆Σ RF-DAC with Fully

Integrated, AC Coupled Digital Input

Dissertation

Presented in Partial Fulfillment of the Requirements for the Degree

Doctor of Philosophy in the Graduate School of The Ohio State
University

By

Jamin J. McCue, B.S.E.E., M.S.

Graduate Program in Electrical and Computer Engineering

The Ohio State University

2015

Dissertation Committee:
Dr. Waleed Khalil, Advisor
Dr. Patrick Roblin
Dr. Steven Bibyk
© Copyright by

Jamin J. McCue

2015
 Abstract

With the continued growth of mobile communications, large portions of the RF

spectrum are being utilized for a variety of wireless applications. For next-generation

systems to adapt to this crowded and fluctuating wireless environment, future radio

hardware must be capable of flexible and reconfigurable operation. Key to this en-

deavor is the development of high-performance digital-to-analog converters which can

directly synthesize RF signals, bypassing the need for analog up-conversion and other

RF processing by pushing functionality into the digital domain.

In this work, a multi-mode delta-sigma (∆Σ) RF digital-to-analog converter (RF-

DAC) is developed for direct digital-to-RF synthesis. The proposed architecture uses

only a single clock frequency (fS ) for RF generation and includes a reconfigurable

∆Σ modulator (DSM) that operates in band-pass (BP) and high-pass (HP) modes

to synthesize signals around fS /4, fS /2, or 3fs /4. Analog interleaving via two 3-

bit DACs is used to reject the first DAC image, simultaneously doubling the usable

bandwidth of the HP DSM, increasing the SNR, and easing filtering requirements.

After a theoretical discussion, the proposed architecture is demonstrated by an initial

prototype implemented in a 130 nm SiGe BiCMOS process and operating at fS =

2 GHz. The design realizes a signal-to-image rejection ratio (SIRR) of 72 dB, an SNR

of 54.5 dB over a 50 M Hz bandwidth, and an in-band SFDR of 58.5 dB.

ii
 In a second revision, an on-chip 14-bit DSM is included, implemented as an array of

pipelined 1-bit pipelined subtracters to generate 3-bit, fS -rate input data. The second

prototype also utilizes on-chip amplitude and timing calibration along with a CML

data path to improve DAC speed, linearity, and SNR. Measurements at fS = 2 GHz

yield a 76.2 dB SIRR, 76.2 dB SFDR over a 100 M Hz bandwidth, −80 dBc IM3,

−67.2 dB WCDMA ACLR and −66.4 dBc LTE ACLR.

To enable the high-speed data input required by the RF-DAC, a fully integrated,

AC coupled pulse receiver is designed in support of this work. The low power and area

efficient receiver is implemented as a fully integrated pulse receiver, eliminating the

need for large, board-mounted capacitors. Additionally, the pulse receiver topology

minimizes baseline wander with return-to-zero (RZ) signaling and removes the need

for data encoding by internally latching long strings of continuous data. A common

mode feedback circuit employs replica biasing to ensure operation over PVT variations

and across various modes of operation. In a low and high power mode, the proposed

receiver is tested up to 7.5 Gb/s and 10 Gb/s, respectively, achieving a peak operation

efficiency of 0.54 mW/Gb/s and a BER < 10−13 .

Altogether, this work describes and validates a novel method of direct digital-to-

RF synthesis. The design is traced from conceptual analysis through implementation

and testing. Other circuits, such as the LVDS pulse receiver, are designed in support

of this work and serve as an indicator of both the design challenges and opportunities

found at the interface between the digital and RF domains.

iii
 To my wife Andrea: my truest critic and my closest friend.

“. . . for a crowd is not company, and faces are but a gallery of pictures,
and talk but a tinkling cymbal, where there is no love. [Life] is a mere
and miserable solitude to want true friends, without which the world is
but a wilderness.” - F. Bacon

Soli Deo Gloria

iv
 Acknowledgments

I would like to thank my family, especially my parents, for their unwavering sup-

port throughout my education, and indeed my life. I am sure that I am a direct

product of their hard-work and intentional upbringing, apart from which I would not

be who I am.

To my friends in Columbus, all of you have been more than just a needed distrac-

tion from school; you have shaped me personally more than you know.

I am indebted to the members of my lab for their technical assistance and prof-

itable discussion, without which this work would not be what it is. Additional thanks

to Samantha McDonnell for the design and use of several circuits in this work. Fur-

ther, I must thank Lucas Duncan for his contributions to this work specifically and

for his friendship in general. Because of him I never lacked an honest opinion or

needed distraction.

I would like to thank the members of the RYDI team at the AFRL (Brad, Greg,

Paul, Tony, Len, Aji, Vipul, and Cari) for their assistance financial, technical, and

otherwise. Surely I have gained much more from their input than I have given in

return, and I am forever grateful for the opportunities they have afforded me.

I would like to thank Dr. Brian Dupaix for his trail-blazing work in the CLASS

lab. Without his guidance and hard work over many years, the infrastructure needed

v
for this project would not have been available. In addition, his many directives and

urgings served to mold me into a better engineer, for which I am in his debt.

Thanks to Dr. James Wilson and Vipul Patel for their assistance with the receiver

portion of this work.

Many thanks to my committee members, Dr. Steven Bibyk and Dr. Patrick

Roblin, for their insight and for the many valuable classes I took with them.

Finally, I would like to thank my advisor, Dr. Waleed Khalil, for believing in my

potential when I knew next to nothing. This work is a direct result of his teaching,

oversight, and guidance. Over last several years at OSU, the example of his tireless

work and technical depth have and will continue to influence me.

To those I have forgotten, for I am sure there are a few, your contributions to this

work, whether direct or indirect, deserve more than a mention on this page...

-Thank you.

vi
 Vita

2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.S.E.E., Cedarville University

2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Student Research Associate,

Center for Directed Energy,
Air Force Institute of Technology

2010-2011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AFRL Sensors Fellowship

2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M.S., The Ohio State University

2009-present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graduate Research Associate,

The Ohio State University

Publications

Research Publications

Tahir Hussain, James Li, Ken Elliott, Donald Hitko, Paul Watson, Jamin McCue,
Kristian Madsen, Heterogeneous Integration: Microsystems on a Chip Through an
Optimal Combination of Diverse Electronic Micro-Components (Invited), Interna-
tional Symposium on Compound Semiconductors (ISCS), June 2015

Jamin J. McCue, Brian Dupaix, Lucas Duncan, Vipul J. Patel, Tony Quach, and
Waleed Khalil, A Time-Interleaved Multi-Mode RF-DAC for Direct Digital-to-RF
Synthesis Radio Frequency Integrated Circuits Symposium (RFIC), May 2015

Jamin J. McCue, Matthew Casto, James C. Li, Paul Watson, Waleed Khalil, An
Active Double-Balanced Down-Conversion Mixer in InP/Si BiCMOS Operating from
70-110 GHz, Compound Semiconductor Integrated Circuit Symposium (CSICS), Oct.
2014 (Nominated for Best Student Paper)

vii
Khalil, W.; McCue, J.; Dupaix, B.; Gaber, W.; Smaili, S.; Massoud, Y., ”On
the Design of RF-DACs for Random Acquisition Based Reconfigurable Receivers,”
International Symposium on Circuits and Systems (ISCAS), June 2014

Qiyang Wu; Elabd, S.; Quach, T.K.; Mattamana, A.; Dooley, S.R.; McCue, J.;
Orlando, P.L.; Creech, G.L.; Khalil, W., ”A 189 dBc/Hz FOMT wide tuning range
Ka-band VCO using tunable negative capacitance and inductance redistribution,”
Radio Frequency Integrated Circuits Symposium (RFIC), June 2013

Qiyang Wu; Elabd, S.; McCue, J.J.; Khalil, W., ”Analytical and Experimental
Study of Tuning Range Limitation in mm-Wave CMOS LC-VCOs,” International
Symposium on Circuits and Systems (ISCAS), May 2013

Qiyang Wu; Quach, T.K.; Mattamana, A.; Elabd, S.; Orlando, P.L.; Dooley, S.R.;
McCue, J.J.; Creech, G.L.; Khalil, W., ”Frequency Tuning Range Extension in
LC-VCOs Using Negative-Capacitance Circuits,” IEEE Transactions on Circuits and
Systems II, April 2013

Qiyang Wu, Salma Elabd, Jamin J. McCue and Waleed Khalil, A 10mW 37.8GHz
Current Redistribution BiCMOS VCO with an Average FOMT of -193.5dBc/Hz,
International Solid-State Circuits Conference (ISSCC), 2013.

Wu, Qiyang; Quach, Tony; Mattamana, Aji; Elabd, Salma; Dooley, Steven R.; Mc-
Cue, Jamin J.; Orlando, Pompei L.; Creech, Gregory L.; Khalil, Waleed; , ”Design
of Wide Tuning-Range mm-Wave VCOs Using Negative Capacitance,” Compound
Semiconductor Integrated Circuit Symposium (CSICS), Oct. 2012

J. McCue, S. Bou-Sleiman, L. Orlando, A. Mattamana, T. Quach, G. Creech, W.

Khalil, Physical Modeling of a Parasitic Net Area Check (NAC) Tie-Down Diode for
De-embedding Applied Computational Electromagnetics Society Conference (ACES),
2012

Balasubramanian, S.; Creech, G.; Wilson, J.; Yoder, S.M.; McCue, J.J.; Verhelst,
M.; Khalil, W., ”Systematic Analysis of Interleaved Digital-to-Analog Converters,”
IEEE Transactions on Circuits and Systems II, Dec. 2011

Jamin J. McCue, Len Orlando, Kari Groves, Aji Mattamana, Tony Quach, and
Gregory Creech, Waleed Khalil, LNA Linearization at the Ka Band Using a .13m
SiGe Technology, GOMACH Tech Conference, 2010

viii
Richard Bartell, Jamin McCue, Matthew Krizo, Steven Fiorino, Matthew Whiteley,
Amy Ngwele, Performance Model of Laser Weapon Systems Comprised of Multiple
Tiled Subapertures, Directed Energy Professional Society, Annual Symposium 2009

Fields of Study

Major Field: Electrical and Computer Engineering

Specialization: Analog and RF Electronics

ix
 Table of Contents

Page

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii

Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

Vita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Analog Transmitter Architectures . . . . . . . . . . . . . . . . . . . 1

1.2 A Digital Alternative: The RF-DAC . . . . . . . . . . . . . . . . . 2
1.2.1 Nyquist Rate RF-DACs . . . . . . . . . . . . . . . . . . . . 3
1.2.2 ∆Σ RF-DACs . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.3 Direct Synthesis RF-DACs . . . . . . . . . . . . . . . . . . 8
1.2.4 The Proposed Multi-mode, Interleaved ∆Σ DAC . . . . . . 9
1.3 High Speed Data I/O . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.1 AC-Coupled Serial I/O . . . . . . . . . . . . . . . . . . . . 10
1.3.2 The Proposed AC-Coupled Receiver . . . . . . . . . . . . . 14
1.4 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2. AC Coupled Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1 Pulse Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.1.1 Latching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2 The Bias Latched Pulse Receiver . . . . . . . . . . . . . . . . . . . 22
2.2.1 Input Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 23

x
 2.2.2 Level Shifting and CMFB . . . . . . . . . . . . . . . . . . . 25
2.2.3 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3 LVDS Receiver Testing . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3.1 Measurement Results . . . . . . . . . . . . . . . . . . . . . 30
2.3.2 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3. The Interleaved, Multi-mode ∆Σ DAC . . . . . . . . . . . . . . . . . . . 34

3.1 Reconfigurable ∆Σ Modulation . . . . . . . . . . . . . . . . . . . . 34

3.1.1 Digital Quantizer . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1.2 Feedback Filter . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.1.3 Input Summation . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2 Multi-Nyquist Operation . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2.1 Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2.2 Inter-DAC Amplitude and Timing Errors . . . . . . . . . . 50
3.2.3 Intra-DAC Errors . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3 Comparison to Nyquist-Rate Architecture . . . . . . . . . . . . . . 55
3.3.1 In-band SNR and ENOB . . . . . . . . . . . . . . . . . . . 55
3.3.2 Noise Floor . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3.3 ∆Σ Output Efficiency . . . . . . . . . . . . . . . . . . . . . 61

4. ∆Σ DAC - First Revision . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.1 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.1.1 DAC and Data Retiming . . . . . . . . . . . . . . . . . . . 65
4.1.2 Data I/O and Loopback Testing . . . . . . . . . . . . . . . 68
4.2 Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.2.1 Test Infrastructure . . . . . . . . . . . . . . . . . . . . . . . 69
4.2.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2.3 Take Aways . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5. ∆Σ DAC - Second Revision . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.1 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.1.1 Serial Data Input . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.2 ∆Σ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.1.3 Data Path and DAC . . . . . . . . . . . . . . . . . . . . . . 83
5.2 Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.2.1 Test Infrastruction . . . . . . . . . . . . . . . . . . . . . . . 89
5.2.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.2.3 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

xi
6. Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.1 Work Summary and Conclusion . . . . . . . . . . . . . . . . . . . . 100

6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.2.1 Scaling Improvements . . . . . . . . . . . . . . . . . . . . . 102
6.2.2 System Integration . . . . . . . . . . . . . . . . . . . . . . . 103
6.3 Final Thoughts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Appendices 107

A. ∆Σ DAC Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

B. ∆Σ DAC Random Jitter Model . . . . . . . . . . . . . . . . . . . . . . . 115

C. Testing Methodology - Rev. 2 . . . . . . . . . . . . . . . . . . . . . . . . 127

C.1 Test Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

C.2 Performance and Verification Tests . . . . . . . . . . . . . . . . . . 128

D. SPI Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

D.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

D.2 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

xii
 List of Tables

Table Page

2.1 Receiver Circuit Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.2 Receiver Power Settings and Performance . . . . . . . . . . . . . . . . 31

2.3 Comparison of Gb/s Pulse Receivers . . . . . . . . . . . . . . . . . . 33

5.1 Power Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5.2 ∆Σ RF-DAC Measurement Comparison . . . . . . . . . . . . . . . . 98

C.1 Board Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . 129

D.1 Register Map for DAC Serial Interface . . . . . . . . . . . . . . . . . 133

D.2 DAC CTL0 Register Description . . . . . . . . . . . . . . . . . . . . 134

D.3 DAC CTL1 Register Description . . . . . . . . . . . . . . . . . . . . 135

D.4 DAC STATUS Register Description . . . . . . . . . . . . . . . . . . . 136

D.5 LOOPBACKx Register Description . . . . . . . . . . . . . . . . . . . 136

D.6 DATA RX ADJx Register Description . . . . . . . . . . . . . . . . . 137

D.7 CAL CUT L Register Description . . . . . . . . . . . . . . . . . . . . 137

D.8 CAL CUT S Register Description . . . . . . . . . . . . . . . . . . . . 138

D.9 CAL LO ADJ Register Description . . . . . . . . . . . . . . . . . . . 139

xiii
D.10 CAL LO DATA L Register Description . . . . . . . . . . . . . . . . . 139

D.11 CAL LO DATA S Register Description . . . . . . . . . . . . . . . . . 140

D.12 CAL MEAS DELAY Register Description . . . . . . . . . . . . . . . 140

D.13 CAL OS L Register Description . . . . . . . . . . . . . . . . . . . . . 141

D.14 CAL OS S Register Description . . . . . . . . . . . . . . . . . . . . . 141

D.15 CAL GE L Register Description . . . . . . . . . . . . . . . . . . . . . 142

D.16 CAL GE S Register Description . . . . . . . . . . . . . . . . . . . . . 142

D.17 CAL TARGET A Register Description . . . . . . . . . . . . . . . . . 143

D.18 CAL TARGET T Register Description . . . . . . . . . . . . . . . . . 143

D.19 CAL I RESx Register Description . . . . . . . . . . . . . . . . . . . . 144

D.20 CAL T RESx Register Description . . . . . . . . . . . . . . . . . . . 144

D.21 CAL DATA SEL0 Register Description . . . . . . . . . . . . . . . . . 145

D.22 CAL DAC DATA SEL0 Register Description . . . . . . . . . . . . . . 146

D.23 CAL TADJ DATA SEL0 Register Description . . . . . . . . . . . . . 147

D.24 CAL DATAx L Register Description . . . . . . . . . . . . . . . . . . 147

D.25 CAL DATAx S Register Description . . . . . . . . . . . . . . . . . . 148

D.26 CAL DAC DATAx L Register Description . . . . . . . . . . . . . . . 148

D.27 CAL DAC DATAx S Register Description . . . . . . . . . . . . . . . 149

D.28 CAL TADJ DATAx L Register Description . . . . . . . . . . . . . . . 150

D.29 CAL TADJ DATAx S Register Description . . . . . . . . . . . . . . . 150

D.30 DS CTL Register Description . . . . . . . . . . . . . . . . . . . . . . 151

xiv
D.31 CLK CTLx Register Description . . . . . . . . . . . . . . . . . . . . . 151

D.32 DS OFFSETx Register Description . . . . . . . . . . . . . . . . . . . 152

D.33 CLK ALIGN Register Description . . . . . . . . . . . . . . . . . . . . 153

D.34 DATA ARR Register Description . . . . . . . . . . . . . . . . . . . . 153

xv
 List of Figures

Figure Page

1.1 The Progression of Software Defined Transmitters . . . . . . . . . . . 3

1.2 Mixing DAC Topologies . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 AC Coupled Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.4 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1 Unencoded AC Coupled Input . . . . . . . . . . . . . . . . . . . . . . 17

2.2 AC Coupled Pulse Transient . . . . . . . . . . . . . . . . . . . . . . . 18

2.3 Capacitor Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4 Bias Latched AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . 22

2.5 LVDS Pulse Receiver Block Diagram . . . . . . . . . . . . . . . . . . 23

2.6 Receiver Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.7 Coupled Input Simulation . . . . . . . . . . . . . . . . . . . . . . . . 25

2.8 Receiver Level Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.9 Output Eye Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.10 Receiver Test Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.11 LVDS Pulse Receiver Test Board . . . . . . . . . . . . . . . . . . . . 29

xvi
2.12 Receiver Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.13 LVDS Low Power Eye Diagrams . . . . . . . . . . . . . . . . . . . . . 32

2.14 LVDS High Power Eye Diagrams . . . . . . . . . . . . . . . . . . . . 32

2.15 Receiver Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.1 Error Feedback ∆Σ Modulator . . . . . . . . . . . . . . . . . . . . . . 35

3.2 Digital Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.3 First and Second Order ∆Σ Modulators . . . . . . . . . . . . . . . . 39

3.4 Shaped Quantization Noise Spectrum . . . . . . . . . . . . . . . . . . 40

3.5 Shaping Spectrum of a Reconfigurable DSM . . . . . . . . . . . . . . 41

3.6 First and Second Order Reconfigurable DSMs . . . . . . . . . . . . . 42

3.7 Required Backoff for Various DSM Configurations . . . . . . . . . . . 44

3.8 DSM Filter Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . 46

3.9 ∆Σ Interleaving Concept Diagram . . . . . . . . . . . . . . . . . . . 47

3.10 Ideal DSM Interleaving Simulation . . . . . . . . . . . . . . . . . . . 49

3.11 Simulated Output Spectrum with Inter-DAC Mismatch . . . . . . . . 52

3.12 Comparison of Analytical and Simulated SIRR . . . . . . . . . . . . . 53

3.13 Simulated Output Spectrum with Intra-DAC Mismatch . . . . . . . . 54

3.14 Baseband Nyquist DAC and Proposed ∆Σ RF-DAC . . . . . . . . . . 56

3.15 Theoretical DSM SNR Performance . . . . . . . . . . . . . . . . . . . 58

3.16 Theoretical DSM Noise Floor . . . . . . . . . . . . . . . . . . . . . . 60

3.17 Theoretical Average In-band Noise Power . . . . . . . . . . . . . . . . 61

xvii
3.18 DAC Efficiency Model . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.19 DAC Efficiency Plot and Comparison . . . . . . . . . . . . . . . . . . 63

4.1 Block Diagram of the First DAC Revision . . . . . . . . . . . . . . . 67

4.2 ∆Σ DAC First Revision Test Setup . . . . . . . . . . . . . . . . . . . 69

4.3 ∆Σ DAC Chip: First Revision . . . . . . . . . . . . . . . . . . . . . . 70

4.4 Test Board 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.5 Measured HP and BP Spectrums . . . . . . . . . . . . . . . . . . . . 73

4.6 DAC Current Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.1 Functional Diagram: Second Revision . . . . . . . . . . . . . . . . . . 77

5.2 Serial Input Using the LVDS . . . . . . . . . . . . . . . . . . . . . . . 78

5.3 The MASH-11 pipelined Architecture . . . . . . . . . . . . . . . . . . 81

5.4 The MASH-11 pipelined Architecture . . . . . . . . . . . . . . . . . . 81

5.5 The Arrayed ∆Σ Bit Cell . . . . . . . . . . . . . . . . . . . . . . . . 82

5.6 The DAC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.7 SFDR and SNR Performance Across Jitter and Mismatch . . . . . . . 86

5.8 The DAC Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 88

5.9 ∆Σ Chip: Second Revision . . . . . . . . . . . . . . . . . . . . . . . . 89

5.10 Second DAC Revision Functional Diagram . . . . . . . . . . . . . . . 90

5.11 Test Board 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.12 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

xviii
5.13 On-chip DSM Measured Spectrum . . . . . . . . . . . . . . . . . . . . 92

5.14 Measured HP and BP Spectrums . . . . . . . . . . . . . . . . . . . . 93

5.15 Measured 800 MHz Spectrum . . . . . . . . . . . . . . . . . . . . . . 94

5.16 Measurement Results Across Sample Rate . . . . . . . . . . . . . . . 95

5.17 WCDMA Measurement Results . . . . . . . . . . . . . . . . . . . . . 96

5.18 LTE Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 97

6.1 Advantages of Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6.2 Future System Integration . . . . . . . . . . . . . . . . . . . . . . . . 105

A.1 Simulink DAC Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

C.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

C.2 Test Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

C.3 Clock and Loopback Testing . . . . . . . . . . . . . . . . . . . . . . . 130

C.4 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

C.5 Full Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

D.1 DAC CTL0 Register Fields . . . . . . . . . . . . . . . . . . . . . . . . 134

D.2 DAC CTL1 Register Fields . . . . . . . . . . . . . . . . . . . . . . . . 135

D.3 DAC STATUS Register Fields . . . . . . . . . . . . . . . . . . . . . . 135

D.4 LOOPBACKx Register Fields . . . . . . . . . . . . . . . . . . . . . . 136

D.5 DATA RX ADJx Register Fields . . . . . . . . . . . . . . . . . . . . 137

D.6 CAL CUT L Register Fields . . . . . . . . . . . . . . . . . . . . . . . 137

D.7 CAL CUT S Register Fields . . . . . . . . . . . . . . . . . . . . . . . 138

xix
D.8 CAL LO ADJ Register Fields . . . . . . . . . . . . . . . . . . . . . . 138

D.9 CAL LO DATA L Register Fields . . . . . . . . . . . . . . . . . . . . 139

D.10 CAL LO DATA S Register Fields . . . . . . . . . . . . . . . . . . . . 139

D.11 CAL MEAS DELAY Register Fields . . . . . . . . . . . . . . . . . . 140

D.12 CAL OS L Register Fields . . . . . . . . . . . . . . . . . . . . . . . . 141

D.13 CAL OS S Register Fields . . . . . . . . . . . . . . . . . . . . . . . . 141

D.14 CAL GE L Register Fields . . . . . . . . . . . . . . . . . . . . . . . . 142

D.15 CAL GE S Register Fields . . . . . . . . . . . . . . . . . . . . . . . . 142

D.16 CAL TARGET A Register Fields . . . . . . . . . . . . . . . . . . . . 143

D.17 CAL TARGET T Register Fields . . . . . . . . . . . . . . . . . . . . 143

D.18 CAL I RESx Register Fields . . . . . . . . . . . . . . . . . . . . . . . 144

D.19 CAL T RESx Register Fields . . . . . . . . . . . . . . . . . . . . . . 144

D.20 CAL DATA SEL0 Register Fields . . . . . . . . . . . . . . . . . . . . 145

D.21 CAL DAC DATA SEL0 Register Fields . . . . . . . . . . . . . . . . . 146

D.22 CAL TADJ DATA SEL0 Register Fields . . . . . . . . . . . . . . . . 146

D.23 CAL DATAx L Register Fields . . . . . . . . . . . . . . . . . . . . . 147

D.24 CAL DATAx S Register Fields . . . . . . . . . . . . . . . . . . . . . . 148

D.25 CAL DAC DATAx L Register Fields . . . . . . . . . . . . . . . . . . 148

D.26 CAL DAC DATAx S Register Fields . . . . . . . . . . . . . . . . . . 149

D.27 CAL TADJ DATAx L Register Fields . . . . . . . . . . . . . . . . . . 149

xx
D.28 CAL TADJ DATAx S Register Fields . . . . . . . . . . . . . . . . . . 150

D.29 DS CTL Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . 150

D.30 CLK CTLx Register Fields . . . . . . . . . . . . . . . . . . . . . . . . 151

D.31 DS OFFSETx Register Fields . . . . . . . . . . . . . . . . . . . . . . 152

D.32 CLK ALIGN Register Fields . . . . . . . . . . . . . . . . . . . . . . . 152

D.33 DATA ARR Register Fields . . . . . . . . . . . . . . . . . . . . . . . 153

xxi
 Chapter 1: Introduction

The last decade has seen unparalleled growth in the bandwidths available over

mobile wireless connections. Broad use of the RF spectrum has pushed transceivers

to operate in more crowded wireless environments while also requiring substantial

increases in data rates with each generation of transceiver. This crowded and rapidly

changing application space demands radios which are flexible with respect to car-

rier frequency and adaptable with respect to modulation scheme and bandwidth.

The term Software Defined Radio (SDR) has come to encapsulate the end goal of

this evolution — complete flexibility and adaptability through the programming of

a highly configurable radio [1, 2]. Implicit in this definition is the use of multiple,

simultaneous frequency bands and modulations schemes within a single radio, a truly

universal transceiver with the benefits of scalability across technology and resistance

to variations in process and environment.

1.1 Analog Transmitter Architectures

Single-band Homodyne and Heterodyne transmitters have long served as the de-

fault architecture for many wireless applications due to their reliability and intuitive

design [3–5]. In these architectures, a digital baseband signal is passed through a

low-frequency digital-to-analog converter (DAC) before being up-converted to an RF

1
band in one (Homodyne) or multiple (Heterodyne) steps. After analog processing, the

signal is amplified and transmitted via a power amplifier and antenna. These conven-

tional designs, however, do not lend themselves to the spectrum agility required by

modern mobile communications. Due to their rigid and analog-centric design, there

is an inherent trade-off made between frequency tuning and performance [6, 7]. This

is illustrated in Fig. 1.1(a) where the two architectures are depicted as low-flexibility

designs, highlighting some of the difficulties of reconfigurable implementation such

as increased LO phase noise and poor filter Q-factor. To meet the requirements of

future SDRs, highly digital transmitters have been proposed which take advantage

of adaptive hardware and process scaling to improve flexibility and performance. As

illustrated in Fig. 1.1(b), high-speed DACs play a central role in the implementation

of these digital topologies by extending the digital domain far into the transmit chain.

However, placing DACs in the RF signal path requires large increases in sample rate

while maintaining linear performance. This new paradigm has spurred significant

research into high-frequency DACs capable of high-fidelity RF output: the RF-DAC.

1.2 A Digital Alternative: The RF-DAC

Over the last decade, advances in digital and RF integration have led to the devel-

opment of RF-DACs (or mixing-DACs) capable of low noise and high linearity direct

digital-to-RF synthesis [8]. Unlike traditional D/A conversion where the output sig-

nal is restricted to less than half of the DAC sample rate, mixing-DACs (Fig. 1.2(a))

decouple the sample-rate and output frequency by combining the up-conversion mixer

and DAC into a single, typically current-mode design capable of low-distortion RF

signal generation via weighted current sources mixed by a local oscillator (LO) [7, 9].

2
 Multi-Band High Power DAC Multi-Band
Frequency Agile Digital RF Frequency Agile
Homodyne Transmitter Radio I Radio

Frequency Agility & Functionality

Frequency Agility & Functionality

BASEBAND
DIGITAL
Digital RF
DAC
DAC  Serves only a single band
I

BASEBAND
 Configurable operation difficult: Q

DIGITAL
ω1 tunable LO
PA
LO1 90°  LO tuning increases phase noise High Bandwidth DAC-PA
Q  Increased IQ Mismatch  Direct digital to high-power RF
Digital RF
DAC
 Design does not scale  III-V implementation
I

BASEBAND
 Reduced noise and linearity

DIGITAL
Digital RF  Process scalable DAC PA
Heterodyne Transmitter
I
DAC  Facilitates calibration

BASEBAND
 Limited co-design Q

DIGITAL
LO1 BPF BPF
ω1
PA
90°
ω2  Largely process scalable
Q Aggregated Single
DAC  Reliant on digital backend
Band Transmitters:
LO2  Configurable mod. and freq.
 Power inefficient  Limited co-design
 Configurable operation difficult: tunable LO and filter  Improved efficiency
Single Band  LO tuning increases phase noise Single Band Single Band Homodyne and  Reduced mismatch
Radio  Wide filter tuning degrades performance Radio Heterodyne Transmitters  Facilitates calibration

Hardware Implementation Software Hardware Implementation Software

(Analog) (Digital) (Analog) (Digital)

(a) (b)

Figure 1.1: (a) Homodyne and Heterodyne transmitters as examples of low agility,
analog centric radios.(b) High frequency DACs enabling agile, software defined trans-
mitters.

Due to the high output frequencies of these designs, the D/A conversion can be located

further down the transmit chain, removing the need for a static analog up-conversion

stage and paving the way for increasingly digital transmitter topologies.

1.2.1 Nyquist Rate RF-DACs

Despite these advances, the low resolutions of early mixing-DAC designs did not

meet the noise floor specifications of current communications standards [10]. More re-

cently, architectures have sought to satisfy these stringent noise requirements through

both higher resolution (increased NN ) and increased sample rate (fSN ). In [11], an

oversampling 14-bit polar mixing-DAC is designed for low far-out noise, critical for

2G/3G communications, while [12] increases resolution further, implementing a highly

linear 16-bit mixing-DAC, sampled in the GS/s range and tunable across multiple

GHz.

3
 However, to realize these high resolution topologies, dozens of DAC cells are re-

quired, dramatically increasing the analog and digital footprint of the design. Due to

this expanded footprint, the amplitude and timing mismatch among the DAC cells is

increased, degrading the DAC linearity and introducing data dependent distortion.

Moreover, DAC current mismatch is exacerbated by reducing the size of the cell cur-

rent source, limiting attempts to shrink the large DAC core. To minimize the impact

of these mismatches, calibration and dynamic element matching (DEM) techniques

have been proposed, correcting [13, 14], sorting-and-combining [15], or randomizing

[16] the error between DAC cells. However, even with these techniques, a large num-

ber of cells are still needed to achieve the desired noise floor, increasing the area and

complexity of the design as well as adding long calibration time during in-situ op-

eration. In addition to the costs of calibration, the large number of DAC cells limit

the high frequency performance of a design by loading the DAC output node and

modulating the DAC output impedance [17].

4
 Digital RF fS Digital RF
NN
I DAC I ΔΣ DAC
M N
fSN
Q DAC Q ΔΣ DAC
NN M N
90º 90º
fSN
LO fS LO
Up-converted Up-converted
1st Nyquist-band 1st Nyquist-band

Up-converted Up-converted Up-converted Up-converted

Signal Images Signal Images
Output

Output
Hold Hold
Shaping Shaping

First Nyquist- fLO fLO+fSN Static ΔΣ fLO fLO+fS

band Noise (a) Noise Shaping (b)

LO 90º fS Digital RF
M N
I ΔΣ DAC

Q ΔΣ DAC
M N
Proposed
LO Reconfigurable fS Architecture
ΔΣ Modulator
Selected
Hold Nyquist band
Shaping
Power

Canceled Signal Canceled

Image Images

Reconfigurable BP fS/2 HP fS LP 3fS/2

ΔΣ Shaping (c)

Figure 1.2: An IQ mixing-DAC showing both (a) Nyquist-rate and (b) oversampled
varieties, where the LO requires wide tuning for multi-band operation. (c) The inter-
leaved, reconfigurable ∆Σ modulator and DAC showing multi-Nyquist RF synthesis.

5
1.2.2 ∆Σ RF-DACs

As an alternative to high-resolution, low-noise mixing-DACs, ∆Σ mixing archi-

tectures (Fig. 1.2(b)) significantly reduce the size of the DAC with a preceding ∆Σ

modulator (DSM). The DSM shapes excess quantization noise away from an RF

passband, allowing low-noise signal synthesis within a narrow bandwidth. The mix-

ing DAC is then implemented with minimal resolution (1-3 bits), thereby leveraging

scalable digital processing to reduce analog complexity [18]. Furthermore, the low

resolution DAC core reduces output loading and internal mismatch while minimiz-

ing the overhead of calibration circuitry and limiting the time needed to run a given

calibration technique.

These advantages are first described in [19] where the performance of a conven-

tional ∆Σ DAC is compared to that of a ∆Σ mixing architecture. Pre-computed ∆Σ

data is fed into an eight-cell DAC, enabling this initial development of the mixing-

DAC architecture and showcasing the potential of low-resolution design for RF syn-

thesis.

The subsequent work in [20] digitally up-converts a lowpass (LP) DSM output to

an intermediate frequency (IF), implementing a homodyne architecture spread across

the digital and RF domains. This upconversion method offsets the signal bandwidth

from the DAC LO, clearing the output band of unwanted LO leakage and mixing

images which result from I/Q mismatch. The ∆Σ mixing DAC uses an off-chip

analog LO to drive 3-bit I and Q DACs. A self-tuned LC filter is constructed at the

DAC output to eliminate out of band noise for signals around 5 GHz. However, wide

reconfigurability is restricted by the need for wide LO and filter tuning in the design.

6
 Another digital IF architecture, reported in [21], implements a band-pass (BP)

DSM at IF, creating a low noise passband which is subsequently up-converted to

RF via an inherently-linear, 1-bit mixing-DAC. Additionally, the implemented DAC

is cascaded to realize a semi-digital reconstruction filter within the design. This

novel use of the domain interface ideally leverages the timing of the digital, the

simple summation of the RF, and the small size of the DAC to realize a digitally

reconfigurable integrated filter. The 1-bit architecture improves IM3, but the low

baseband sampling frequency limits its noise and bandwidth performance.

In [22], a ∆Σ topology enables digital I/Q mixing beyond IF by directly up-

converting high-speed DSM data with an all-digital mixer, the output of which is fed

into weighted I and Q current cells for dynamic power control. This design bridges

the ∆Σ and Nyquist domains by implementing a moderate resolution (> 6 bit) DAC

which utilizes noise shaping in the pursuit of low noise RF performance.

Despite the advantages of ∆Σ modulation, the mixing-DAC architecture has sev-

eral inherent limitations which impair their reconfigurable operation. First, the ab-

sence of a reconstruction filter before up-conversion gives rise to close-to-carrier images

in the DAC output. Even with the attenuation of hold shaping [23], mixing-DACs

have shown a maximum image suppression of 54 dB [24]. Instead, designs sample the

baseband signal at frequencies which approach or exceed the LO frequency [20, 22],

pushing DAC images further out of band. However, these high frequency sampling

clocks must be accurately aligned to the LO signal to mask the jitter of incoming

data and maintain in-band noise performance [21]. Additionally, since I/Q mixing

and combining is performed in the analog domain, both amplitude and timing mis-

matches can corrupt the output error vector magnitude and induce mixing images.

7
This is further exacerbated by the challenge of multi-band operation where the LO

must provide both wide frequency tuning and low phase noise.

1.2.3 Direct Synthesis RF-DACs

This is in contrast to fully digital mixing which does not introduce IQ mismatch

nor does it require the alignment of a widely tuned analog LO [25]. Instead, up-

sampled data is multiplied by a clock signal to digitally synthesize RF waveforms.

While the output frequency is limited by the digital sample rate of the system (encour-

aging architectures which utilize easy-to-realize multiplication), the speed and perfor-

mance of digital mixing will continue to improve with technology scaling. Therefore,

a viable alternative to the mixing-DAC architecture becomes that of fully-digital I/Q

mixing coupled with a high-speed ∆Σ DAC.

Such a system is described in [26] where a single, high-speed clock is used for

both a LP DSM and to directly synthesize the results of all-digital mixing and I/Q

combining. The baseband signal is first up-sampled to the rate of the clock (created

from an on-chip delay locked loop) and then passed through the DSM. The shaped

passband is up-converted to RF by a high-speed mux, toggling between inverted and

non-inverted I/Q data. At the output of the design, [26] employs an inherently-linear

1-bit inverter to directly synthesize a GHz-range RF output by leveraging the first

image of the sampled waveform. However, due to its supply noise sensitivity, the

single-bit inverter topology contributes high jitter and, as a result, increases in-band

noise. Additionally, when utilizing outputs in the second Nyquist zone, a high power

image is present in the first, requiring high stopband attenuation in a subsequent

reconstruction filter. In this design, the the viability of a fully digital architecture is

8
demonstrated, but the RF performance must be improved before integration into a

wireless system.

1.2.4 The Proposed Multi-mode, Interleaved ∆Σ DAC

In this work, a multi-order, multi-band ∆Σ DAC is proposed to leverage the ad-

vantages of all-digital I/Q up-conversion while also improving jitter performance and

canceling unwanted, high-power image replicas. This is accomplished by arraying two

time-interleaved channels containing both the DSM and DAC while utilizing readily

available 180◦ clocks. When summed, the channel outputs cancel the unwanted im-

ages and reject their associated non-linearity spurs, leveraging multiple Nyquist zones

to achieve high-frequency RF signal synthesis [27]. By canceling the first DAC im-

age, the proposed design uniquely enables high-pass (HP) ∆Σ modulation which,

as can be seen in Fig. 1.2(c), has twice the bandwidth (red) of BP ∆Σ modulation

(grey) due to its near Nyquist operation [28]. Additionally, any residual DAC image

is located in-band, acting as a self-interfering signal, as opposed to an out-of-band

spurious emission, limiting potential interference with adjacent communications. It

is worth noting that including the DAC as part of the interleaved data channel min-

imizes the speed and timing constraints compared with other interleaving schemes

which focus exclusively on the DSM and require a high-speed multiplexer and DAC

[29, 30]. Taking advantage of the all-digital DSM, a reconfigurable modulator is cre-

ated by switching between various MASH stages and filter functions, synthesizing RF

passbands at 1/4, 1/2, or 3/4 of the system clock rate.

9
 Altogether, the proposed architecture is able to leverage parallel, high-speed DACs

to directly output RF signals, and ∆Σ modulation is used to minimize the degradation

of the DAC performance at high frequency.

1.3 High Speed Data I/O

A significant issue in the implementation and testing of the proposed DAC, es-

pecially given its high input resolution and interleaved topology, is high-speed data

input. While baseband DACs need only receive a data stream capable of synthesiz-

ing the signal bandwidth (a few hundred MHz at most), the proposed DAC directly

synthesizes modulated RF signals which require high-rate data containing both the

desired signal and an RF carrier. Methods of data I/O such as multiplexing lower bit-

rate data and on-chip memory have been previously employed to meet data through-

put requirements in DACs [31–33], sidestepping the complexities of high-speed, chip-

to-chip serial communications by sacrificing chip area, power, time, or additional I/O

pins. Instead, a more direct approach is taken in this work, that of real-time data in-

put [34, 35]. To this end, current trends in high-performance serial I/O are discussed

and a novel, fully integrated receiver is presented as a means of enabling the real-time

operation of the interleaved DAC architecture.

1.3.1 AC-Coupled Serial I/O

With the on-going progress of integrated circuit scaling, on-chip communications

see continued improvement due to reductions in loading and circuit spacing. Chip-

to-chip data links, however, do not experience these same benefits, relying instead

on new and increasingly complex transceiver topologies to overcome package and

board-level limitations. In pursuit of higher data rates and increased power and area

10
efficiency, high-performance chip-to-chip communications have evolved from highly-

parallel topologies through DC-coupled serial designs [36] with recent architectures

now utilizing AC-coupled serial channels for efficient multi-Gb/s performance. By

placing coupling capacitors between the serial transmitter and receiver, AC-coupled

designs remove the stringent common-mode specifications typical of DC-coupled chan-

nels [37, 38], improving system efficiency and interoperability while isolating the re-

ceiver for optimal biasing [39]. In addition, capacitive serial links are also leveraged in

close-proximity chip-to-chip [40] and chip-to-board [41] communications by utilizing

the capacitance between narrowly spaced pads to realize high density I/O.

In such systems, a constant design challenge is the area-efficient integration of

coupling capacitors. As depicted in Fig. 1.3(a), traditional AC-coupled data links

rely on large, board mounted capacitors (CC ≥ 1 nF ) and DC balanced encoding to

set the channel cut-off frequency below that of the data stream [42]. In this way, the

exponential decay of the coupled data is negligible, avoiding the problematic effects of

baseline wander. However, this design methodology consumes large amounts of board

area, introduces reflections into high-speed channels [43], and is impractical for high

density or 3-D integrated designs. Instead, recent topologies have sought to integrate

the coupling capacitor within the receiver by significantly reducing its size. To avoid

baseline wander in fully integrated designs, two distinct approaches have been taken:

those centered around 1) DC compensation and large RC time-constants or 2) pulse

reception with a much smaller RC product.

Described in [44], the large time-constant approach offsets the reduced coupling

capacitance with an increased resistance (τ = RCC ), maintaining the channel cut-off

frequency well below that of the encoded data stream. Supplementing this approach,

11
 τ = RCC
Baseline NRZ Data
Wander
Encoded
Data Input

Decoder
Data Ouput
CC Sense

2R
Amp

CC
Integrated Receiver
(a)

Integrated Receiver
50Ω
CC RZ Pulse

Decoder
FF DC Sense CC Sense

2R
2R

Restore Amp Amp

NRZ Data

CC Latch
CC
50Ω LP FB
Integrated Receiver

(b) (c)

Figure 1.3: (a) AC coupled receiver with off-chip coupling and data encoding, showing
baseline wander on the input node due to a small RC product. (b) Integrated AC
coupling with a high RC time constant and feed-forward or feed-back DC restore. (c)
Fully integrated pulse receiver with high-gain sense amplifier and latching.

feed-back or feed-forward DC compensation (Fig. 1.3(b)) further reduces baseline

variations [45]. This is demonstrated in [46] where a 5-tap low-pass feedback network

actively restores the attenuated DC content by applying an analog correction voltage

to the coupled input. While effective, the associated processing lowers power efficiency

and requires adjustment with changing signal amplitude. Instead, [39] presents a pas-

sive feed-forward network to restore the signal DC without significant power overhead

or adjustment. However, both of these feed-forward and feed-back approaches require

complex adaptive circuitry at the receiver input. Additionally, the large time-constant

12
approach still utilizes data encoding which further increases receiver complexity and

lowers the effective data rate of the overall system.

As an alternative, pulse receivers minimize the time-constant of the coupled in-

put such that each bit fully decays within one unit interval (UI). In this way, the

integration of the channel coupling is enabled by capacitances in the pF to fF range.

Additionally, the resulting return-to-zero (RZ) waveform removes the effects of base-

line wander. To ensure accurate data reception, a latch or 1-tap decision feed-back

equalizer (DFE) is used to translate the three-level coupled pulse into a binary (NRZ)

output, as depicted in Fig. 1.3(c). In contrast to DC compensation, pulse receiver

topologies are simple, low power, and, because of their internal latching, do not re-

quire data encoding [47].

These advantages are highlighted in [48] and [49] where respective 1.3 Gb/s and

1.4 Gb/s face-to-face data links use inverter feedback as low-overhead DFE circuits.

The pulse receiver in [50] also utilizes an inverter gain stage along with a cross-coupled

PMOS load, forming an asynchronous latch that operates at 3 Gb/s. Though effective,

these inverter topologies have high parasitic capacitance at the receiver input, limiting

receiver bandwidth and sensitivity. The work in [51] overcomes this limitation by

implementing a sense amplifier and latch after the inverter stages, unloading the

receiver input and achieving 10 Gb/s operation. However, the sensitivity and duty-

cycle of this digital architecture are dependent on process, voltage, and temperature

(PVT) variation while the single ended input is susceptible to common-mode (power

and ground) fluctuations.

The pulse receiver in [52] utilizes a fully differential topology with a cross-coupled

NMOS latch, rejecting common-mode noise and achieving rates up to 6 Gb/s. In [53,

13
54], two differential amplifiers are implemented in parallel, latching incoming pulses

with programmable hysteresis. The parallel amplifiers utilize a high-gain, “split-

load” design to further reduce loading and increase bandwidth, realizing full and half-

rate speeds of 10 Gb/s and 16.67 Gb/s, respectively. Despite data rates > 10 Gb/s,

the power consumption of the multi-stage parallel architecture limits efficiency to

2 − 3 mW/Gb/s.

1.3.2 The Proposed AC-Coupled Receiver

In the proposed work, a fully-integrated, differential pulse receiver is implemented,

employing a single-stage, high-gain sense amplifier to maximize power efficiency. To

reduce input loading, low capacitance bias switches are implemented, creating a DFE

within the amplifier and removing the need for a separate output latch. Unlike

previous work, the proposed design also utilizes replica biased common-mode feedback

(CMFB) to ensure performance across PVT variation. With this operational stability,

a low and high power mode are implemented by scaling the supply voltage, allowing

the design to run at high speed or high efficiency (< 1 mW/Gb/s). The receiver

circuit is designed in a 0.13 µm SiGe process and utilizes the available HBTs for their

high switching speeds and low parasitic capacitance. Integrated AC coupling uses

high-density MIM capacitors sized to ensure pulse decay, thus minimizing baseline

wander and data dependent jitter. The design is mounted on a PCB test-bed and

is demonstrated at data rates from 1 − 10 Gb/s and achieves a BER < 10−13 and a

peak efficiency of 0.54 mW/Gb/s.

14
1.4 Outline

The scope of this research includes the conceptual design, circuit implementation,

and testing of the proposed pulse receiver, interleaved ∆Σ modulation, and 3-bit

RF-DAC, as illustrated by the overview in Fig. 1.4. Chapter 2 focuses on the early

design and validation of the pulse receiver while Chapters 3 discusses the theoretical

underpinnings of the interleaved DSM and DAC. Chapters 4 and 5 detail the circuit

design and testing of the first and second DAC prototypes, respectively, comparing

their performance with other state-of-the-art designs. Finally, Chapter 6 gives a

summary of the work along with future research goals for the proposed multi-mode,

interleaved ∆Σ DAC.

Proposed RF-DAC

ΔΣ
ΔΣ DAC
DAC
MOD 3-bit
3-bit
Rx MOD Output
Waveform
Data Spectrum

Figure 1.4: The scope of work: the interleaved multi-mode ∆Σ RF-DAC and the
associated high-speed I/O.

15
 Chapter 2: AC Coupled Data Input

The AC coupling of high speed I/O channels facilitates receiver design by removing

common-mode range requirements and allowing the receiver bias to be optimized for

high-speed or low-power operation. However, the addition of coupling capacitors

creates a high-pass channel response which can cause baseline wander when fed with

unbalanced NRZ data or with long strings of consecutively identical digits (CIDs).

Typically, schemes such as 8b/10b encoding are used to ensure DC balance and to

limit the low frequency content of the data stream. Large capacitors can then be used

to couple in the data, minimizing voltage droop.

The need for this design methodology is highlighted in Fig. 2.1 where (a) an AC

coupled receiver is fed with (b) a string of CIDs of amplitude Vi causing (c) the coupled

common-mode to deviate from the desired input bias VB . Using the RC input model

given in Fig. 2.1(a), the highpass transfer function of an AC coupled channel can be

approximated by (2.1). In this equation, the coupling capacitance is represented by

CC , the termination resistance by RT , and the parasitic input capacitance by CP .

VIN C sRT CC
= (2.1)
VIN sRT (CC + CP ) + 1
By modeling an incoming bit as a step function, the exponential decay of the coupled

input is expressed in (2.2), having the time constant τ given in (2.3). The typically

16
 1011111111101110

IN+
VCM
1/RCC
1
Time
Vi tB
Frequency

IN-
VCM
CIDs
Frequency
Time
Response (b)
RC Input Model Exponential
Z
VB Decay
IN
VB

VINC+
CC RT
OUT Baseline
Wander
IN+ INC+ Vi
CP
RX Time
IN- INC- CP
Baseline Vi
CC RT OUT VINC- Wander

VB VB
(a)
Time
(c)

Figure 2.1: (a) The RC input model of an AC coupled receiver. (b) Receiver in-
put containing a string of CIDs of amplitude Vi and (c) the coupled input showing
exponential decay and baseline wander.

large CC dominates the input response, allowing the coupled signal to be designed

such that the voltage droop is below some maximum tolerance [55].

Vi  −t

VIN C (t) = 1−eτ (2.2)
2

τ = RT (CC + CP ) (2.3)

17
2.1 Pulse Receiver

Unlike traditional AC coupling, however, the goal of a pulse receiver is not mini-

mum voltage droop (via a large coupling capacitance), but instead a DC balanced RZ

waveform, eliminating the common-mode variations caused by CIDs. To create this

RZ pulse, a small CC is used to ensure incoming bits are coupled into the receiver

but fully decay within one bit period (tB ). Such a design is ideal for fully-integrated

chip-to-chip I/O, as it reduces capacitor size, but a thorough modeling of the input

is needed to ensure sufficient coupling with minimal jitter. To this end, a rise time tR

is added to the model of the incoming bit, creating a more accurate representation

of high-speed data. As shown in Fig. 2.2(a), this waveform is applied to the RC

input model, the slope (m) of the transition set by the input amplitude and rise time

(m = Vi /tR ). The coupled signal, given by (2.4), is illustrated in Fig. 2.2(b) and is

comprised of two parts: the transition response (t < tR ) and the subsequent decay

(tR < t < tB ).

RT VC
VINC
VIN

m Vi
CC VE
CP
tR tB tR tB
(a) (b)

Figure 2.2: (a) The input waveform representing high-speed data with a finite rise
time and (b) the partially coupled input.

18
  
−(t−tR )
 −t

VIN C (t) = mRT CC 1 − e τ − u(t − tR ) · mRT CC 1 − e τ (2.4)

During the transition response, an incoming bit is only partially coupled into the

receiver due to the small size of CC . The peak coupled amplitude VC can be found

by evaluating (2.4) at time t−

R , resulting in the expression given in (2.5). This peak

amplitude, along with the gain of the receiver, directly sets the sensitivity of the

design with increasing values of CC contributing to a more sensitive receiver.

Vi RT CC  −tR

VC = 1−e τ (2.5)
tR

After the transition response, the coupled signal decays toward its bias point

where, at the end of the bit period, some residual error voltage VE remains. This

error represents a departure from the intended RZ signaling and causes energy from

one bit to leak into the next, resulting in ISI jitter. The magnitude of VE can be

determined by solving (2.4) at t−

B , shown in (2.6).

Vi RT CC  tR −tB −tB

VE = e τ −e τ (2.6)
tR

As with VC , a higher coupling capacitance increases VE , leading to a direct trade-

off between receiver sensitivity and ISI jitter in the sizing of the input capacitor. This

is demonstrated in Fig. 2.3(a-b) where the coupled amplitude and the error voltage

are plotted for different values of CC across bit rate. For these figures, CP is set at

10% of CC and tR is kept at 20% of tB . As CC is increased, sensitivity is improved

at the expense of jitter. This design trade-off is further complicated by increases in

data rate where a shrinking tB reduces settling time, increasing VE further.

19
 CC = 3.5 pF CC = 3.5 pF
High Sensitivity CC = 2.5 pF CC = 2.5 pF High Jitter
CC = 1.5 pF CC = 1.5 pF
CC = 0.5 pF CC = 0.5 pF
CC = 0.1 pF

Low Sensitivity Low Jitter

Bit Rate [Gb/s] Bit Rate [Gb/s]

(a) (b)

CC = 3.5 pF
Ideal CC = 2.5 pF
CC = 1.5 pF
VE Offset
CC = 0.5 pF

Δt VC

VE
tR
Bit Rate [Gb/s]
(c) (d)

Figure 2.3: (a) Coupled amplitude, (b) error voltage, and (c) jitter as a function of
coupling capacitance and bit rate.

To find the deterministic jitter added by a given VE , the difference in crossing

time (∆t) between an ideal transition and one with VE is calculated. Depicted in

Fig. 2.3(c), this timing variation can be described in (2.7) by equating these two

transition cases. Solving for ∆t (i.e. the peak-to-peak jitter) results in the expression

given in (2.8). Figure 2.3(d) plots this jitter, indicating that a 1.5 pF coupling capac-

itor will experience only 20% peak-to-peak jitter at 10 Gb/s with minimal impact to

the coupled amplitude.

20
 VIN C (t) = VIN C (t + ∆t) − VE (2.7)

 
−VE tR −t
∆t = −τ ln +eτ −t (2.8)
Vi RT CC

2.1.1 Latching

As detailed in Chapter 1.3, many pulse receivers utilize latches after the receiver

amplifier to hold the incoming pulses for an NRZ output. These single-ended, pre-

dominantly digital architectures suffer from PVT variates and common mode dis-

turbances. To overcome this, [53, 54] implement multistage, parallel amplifiers to

latch data within the gain stage. However, the multistage topology only achieves an

efficiency of 2-3 mW/Gb/s. The proposed architecture implements a bias latch fully

integrated into the single stage receiver amplifier, depicted in Fig. 2.4, realizing a

robust, low power design. Two separate bias voltages (VB1 and VB2 ) are selectively

applied to the differential inputs of the receiver to latch previous bit values. In this

way, the positive and negative input of the receiver do not decay completely to the

same potential with the difference between the two biases ∆VB setting the receiver

hysteresis. To selecet which bias is applied to each input, the receiver output is fed

back to the bias switches. The effect of this toggled bias is a latching receiver which

accurately handles strings of CIDs without encoding.

21
 1011111111101110
VB2 VB1

IN+
VCM

OUT OUT
Time
TB
CC RT

IN-
OUT VCM
IN+ INC+
CP Time

IN- INC-
RX
CP VB2

INC+
Undefined ΔVB
OUT VB1
CC RT VC

Time
OUT OUT
VC
INC- VB2
VB1 VB2 Undefined ΔVS
VB1

Time

Figure 2.4: Bias switching used to latch CIDs and limit baseline wander

2.2 The Bias Latched Pulse Receiver

A functional diagram of the proposed pulse receiver is shown in Fig. 2.5. Following

the on-chip AC coupling, a high-gain differential amplifier recovers the incoming low-

voltage pulses. A level-shifting buffer then translates the signal to CMOS levels where

cascaded inverters create the full-scale digital output. Received data is fed back from

these inverters to switches within the amplifier, toggling its bias point to latch the

data. Common mode feedback (CMFB) is employed to lock the buffer common mode

to the switching threshold of the inverters. This guarantees constant duty-cycle across

process, voltage, and temperature (PVT) variation and allows the receiver to operate

as the supply voltages are adjusted between low power and high power operation.

22
 Bias Switch Cascaded
Feedback Inverters
CC

Zo Level
Diff
2R Shifting AVG
Amp
Buffer
Zo Digital
CC
Bias Switch Output
Feedback +
Amp V Bias
REF
Common Mode
Circuit
Feedback

Figure 2.5: The pulse receiver functional diagram.

Table 2.1: Receiver Circuit Sizing

Devices Size Components Value

Q1 , Q2 L : 3 µm W : 120 nm R1 , R2 800 Ω
Q3 , Q4 L : 5 µm W : 120 nm R3 , R4 145 Ω
M1 , M3 W : 2 µm L: 240 nm R5 , R6 60 Ω
M2 , M4 W : 6 µm L: 240 nm R7 , R8 1 kΩ
M5 W : 18 µm L: 150 nm R9 , R10 25 kΩ
M6 , M8 , M10 W : 5 µm L: 120 nm R11 2.3 kΩ
M7 , M9 , M11 W : 1.7 µm L: 120 nm CC 1.4 pF

The full receiver schematic is shown in Fig. 2.6 and Table 2.1 gives the device sizes

and component values used.

2.2.1 Input Amplifier

The core of the design is the input amplifier which is created from a single differ-

ential pair. The amplifier utilizes SiGe HBTs (Q1 − Q2 ) for their superior switching

speed and low parasitic capacitances, extending the amplifier bandwidth beyond that

of the available CMOS and increasing the maximum data rate of the design.

23
 Differential Amplifier with Bias Switches
Legend
VDD

R1 R2 VCC
M1 M2 M3 M4
First Inverter First Inverter
Stage Stage

Q3
OUT R3 OUT R4 OUT
Q4
M6 M8
INC+ IN+ IN- INC-
Q1 Q2
OUT CC R5 R6 CC OUT

M7 R9 R10 M9

R7 R8
M10 VREF M5

Level Shifting R11 Level Shifting

M11 CM Feedback and
Buffer Buffer
Replica Reference

Figure 2.6: The receiver schematic.

To bias the amplifier, the proposed topology creates an offset (∆VB ) between the

positive and negative amplifier bias points, forcing opposite polarity inputs to decay

to different steady-state voltages. Figure 2.7 shows a simulation of the coupled input

(INC+ ) where the effects of the offset are highlighted by long runs of both 0’s and 1’s.

The input pulses decay, but a minimum difference is maintained and subsequently

amplified by the input stage. For compatibility with the hysteresis requirements of

LVDS [37] and other standards, the magnitude of this offset is set to ∼ 25 mV , thus

removing data reception errors caused by noise and line reflections.

The two receiver biases VB1 and VB2 are created on chip via ratioed resistors. With

this method of implementation, the biases can track supply variations as the receiver

voltages are tuned for low or high power operation. Transistors M1 − M4 are used

as the bias switches and are composed of thick gate PMOS devices to guard against

breakdown. To reduce the capacitive loading on the digital feedback, M1 − M4 are

implemented as small, high resistance switches with their RON integrated into the

24
 1.150

VB2
ΔVB
Voltage
1.100 VB1
Droop

Figure 2.7: Extracted simulation of the coupled input showing bias latching and
voltage droop due to feedback latency.

bias generation network. The switches are interdigitated to minimize unwanted bias

offsets caused by mismatch.

2.2.2 Level Shifting and CMFB

Following the input gain stage, two common collector buffers level-shift the data

down to CMOS levels. Of critical importance is the centering of the output common

mode on the inverter mid-rail voltage. Due to variations in PVT, the common mode

can drift away from this mid-rail, closing the receiver eye with duty cycle distortion,

as shown in Fig. 2.8. A CMFB amplifier, labeled in Fig. 2.6, is used to sense the

buffer common mode and compare it to a self-biased replica of the first inverter

stage. By adjusting the current, and thus the output level, of the input amplifier,

the buffer output is pinned to the mid-rail of the first inverter. Since the CMFB

only compensates for low-frequency variation, the bandwidth of the feedback loop is

kept below 50 MHz so that it does not interfere with the high speed bias control.

25
 Inverter TF Digital Output

Q4 M8
VCM Low CM

Mid-rail

R8 M9
High CM

Inverter Input
VCM

Figure 2.8: The receiver level shift and inverter input.

Additionally, the gain and phase margin of the CMFB are set to 28 dB and ∼ 60◦ ,

respectively, ensuring stable operation.

After the common collector buffer, a chain of inverters conditions the data and

drives the PMOS bias switches. The inverters are optimized for minimum feedback

latency, achieving a delay of ∼ 20 ps each. The effect of this feedback delay can be

seen in the input simulation of Fig. 2.7 where the incoming pulse droops below the

desired bias before the switches are toggled. While this voltage droop contributes

to the receiver output jitter, it is kept below 5 mV by an optimized feedback path,

ensuring operation up to 10 Gb/s.

2.2.3 Simulation

The receiver performance is verified through extracted simulation where the re-

ceiver is driven by a random bit generator via modeled wirebonds and transmission

lines, the output taken after the cascaded inverter chain. Figure 2.9 gives the receiver

output eye diagram after 104 random bits for both low power (VCC = 1.7 V ) and

26
 1.2
VCC = 1.7 V

Voltage [V]
0.8
7.5 Gb/s 15 ps
0.4

0
0 50 100 150 200 250
Time [ps]

1.5
Voltage [V]

VCC = 2.1 V
1.0 18 ps
10 Gb/s
0.5
0
0 40 80 120 160 200
Time [ps]

Figure 2.9: Extracted simulation of the receiver eye diagram at VCC = 1.7 V and
2.1 V , 7.5 Gb/s and 10 Gb/s respectively.

high power (VCC = 2.1 V ) operation. In the low voltage mode, data dependent jitter

caused by the bias feedback latency is evident in the output eye and results in a

peak-to-peak jitter of 15 ps. While this deterministic jitter decreases the eye opening,

it does not compromise receiver functionality. The high voltage mode exhibits this

behavior as well, but the increased data rate and random jitter of this operating point

obscures any data dependency and results is a simulated jitter of 18 ps, very close to

the estimated jitter of 20 ps calculated in Fig. 2.3.

27
2.3 LVDS Receiver Testing

The proposed LVDS pulse receiver is implemented in a 0.13 µm SiGe BiCMOS

process where it occupies 0.0115 mm2 . Dominated by the area of the MIM coupling

capacitors (0.00952 mm2 ), the receiver layout is placed between the two differential

input pads for high density integration, as shown in Fig. 2.10. To measure the receiver

performance, the captured data is looped back off-chip without clock alignment. This

is done so that the system jitter can be measured off-chip and a BER test can be

performed. A CML differential pair is used as a 50 Ω buffer, retransmitting the full-

scale receiver output. While this buffer is only 25% efficiency [56], it provides a simple,

robust means of data transmission. From simulation, the jitter added by the buffer

is negligible compared with that of the receiver, thus the measured system jitter is

assumed to be predominantly a result of the receiver.

The test chip containing the receiver and loop-back buffer is wire-bonded to a

two layer FR4 printed circuit board (PCB). Shown in Fig. 2.11, the first PCB layer

provides power, ground, and 2.5 cm 50 Ω transmission lines to SMA connectors. The

second layer is used only as a transmission line ground for the high-speed data lines,

ensuring matched line impedances. Matched 1 m cables are then used to connect the

design to a digital signal analyzer or BER tester for measurement.

28
 135 µm
Coupling Capacitors

85 µm
56 µm
LVDS Core

Figure 2.10: The receiver test chip.

Power
Header

Decoupling

RX
Input
Chip

TX
Output

Figure 2.11: The receiver test board.

29
 FR4 PCB Power Supply
PRBS Generator LVDS Chip V
2.5 cm
13.5 Gb/s Max GND
PRBS 223 – 1 RX RX VCC

TX RX VDD
TX VCC
1 Meter
Cables
2.5 cm

1 Meter
Cables

Bit Error Rate Tester Digital Signal Analyzer

13.5 Gb/s - Max 12GHz / 40 Gs/s

Figure 2.12: Receiver BER and eye testing.

2.3.1 Measurement Results

The loop-back testing depicted in Fig. 2.12 is accomplished with an input pseudo

random bit sequence (PRBS) of 223 − 1 bits, used to exercise the receiver with long

runs of invariant data. The design is tested under the two supply conditions outlined

in Table 2.2. In the low power mode, an analog voltage of 1.7 V and a digital voltage of

1.1 V are used, resulting in a total power consumption of 4 mW . Under this condition,

the receiver achieves a maximum data rate of 7.5 Gb/s with a BER of < 10−13 and an

efficiency of 0.53 mW/Gb/s. Figure 2.13 shows the output eye of the receiver/output

buffer system at 3 Gb/s and at 7.5 Gb/s. At these data rates, a peak-to-peak jitter of

31.1 ps and 45.6 ps is recorded.

30
 Table 2.2: Receiver Low and High Power Settings

Receiver Settings Low Power High Power

Analog Voltage (VCC ) 1.7 V 2.1 V
Digital Voltage (VDD ) 1.1 V 1.5 V
Power 4 mW 9.5 mW
Data Rate 7.5 Gb/s 10 Gb/s

At bit rates above 7.5 Gb/s, the receiver eye diagram begins to degrade and the

BER increases as a result. From simulation, the limiting factor in the low power

mode is the drive strength of the receiver output inverters. With only a 1.1 V supply,

these inverter buffers cannot drive the input capacitance of the CML transmitter at

speed. This issue is solved in the high-power mode by increasing both the analog and

digital supply voltage to 2.1 V and 1.5 V , respectively.

In the high power mode listed in Table 2.2, the maximum bit rate increases to

10 Gb/s while the receiver power consumption increases to 9.5 mW . Again, a BER

of < 10−13 is recorded while an efficiency of 0.95 mW/Gb/s is achieved. Figure 2.14

gives the measured eye diagrams of the system at 7 Gb/s and at 10 Gb/s. With the

higher supply voltages, the peak-to-peak jitter at these two data rates is 29.4 ps and

52.8 ps, respectively.

In Fig. 2.15, the peak-to-peak jitter measured during loop-back testing is plotted

as a percentage of the UI from 1 − 10 Gb/s (plots from Fig. 2.13 and Fig. 2.14 are

labeled). At low data rates, the low power jitter is less than that of the high power,

resulting in high-speed, power efficient data reception. The higher jitter present in

the high-power mode is due to its increased ∆VB from the raised supply voltage.

However, as data rates increase above 7 Gb/s, the low power jitter exceeds that of the

high power mode and the increased supply voltage is needed to maintain operation.

31
 PP Jitter PP Jitter

31.1 pS 45.6 pS

(a) (b)

Figure 2.13: Low power output eye of the receiver at (a) 3 Gb/s and at (b) 7.5 Gb/s.

PP Jitter PP Jitter
52.8 pS
29.4 pS

(a) (b)

Figure 2.14: High power output eye of the receiver/transmitter at (a) 7 Gb/s and at
(b) 10 Gb/s.

Fig. 2.14(b)

Fig. 2.13(b)

Fig. 2.14(a)

Fig. 2.13(a)

Figure 2.15: Peak-to-peak jitter measurements from 1 to 10 Gb/s in low and high
power mode.

32
2.3.2 Comparison

Table 2.3 compares the proposed architecture to other Gb/s pulse receivers. With

the exception of [51] which does not include the receivers on-chip buffer, the design

achieves the highest power and area efficiency. Additionally, the proposed receiver

is implemented with a single stage differential amplifier with CMFB, minimizing

mismatch errors and achieving an input data rate of 10 Gb/s. With this robust input

cell, the proposed ∆Σ DAC can be fed with real-time high-speed data, avoiding the

area consumption of highly parallel I/O or on-chip memory while also minimizing

design complexity by removing data encoding.

Table 2.3: Comparison of Gb/s Pulse Receivers

Ref. Technology Bit Rate BER P2P Jitter Power Pwr. Eff. Total Area A. Area Area Eff.
[nm] [Gb/s] [ps] [mW] [mW/Gb/s] [mm2 ] [mm2 ] [µm2 /Gb/s]

[41] 350 CMOS 2.5 Gb/s < 10−12 < 120 10.3 4.1 - - -
[47] 100 CMOS 1 Gb/s - - 2.7 2.7 0.0402 0.0281 28,050
[48] 350 CMOS 1.35 Gb/s < 10−12 - 3.6 2.7 - - -
[50] 180 CMOS 3 Gb/s < 10−12 < 120 10 3.33 0.0043 0.0007 225
[53] 90 CMOS 10 Gb/s - 35∗ 32 3.2 0.045 - -
180 CMOS 3.3 Gb/s - 55.6 40 12.1 0.97‡ - -
[54] 90 CMOS 13 Gb/s - 35∗ 26 2.0 0.6 - -
[51] 180 CMOS 10 Gb/s < 10−14 45∗ 2.7† 0.27† - 0.0012 120

This Work 130 0.0115 0.002

(LP) SiGe 7.5 < 10−13 45.6 4.0 0.54 261
(HP) BiCMOS 10 < 10−13 52.8 9.5 0.95 196
∗ † ‡
Estimated From Figure Buffer Not Included Includes Pads

33
 Chapter 3: The Interleaved, Multi-mode ∆Σ DAC

In the pursuit of increasingly digital transmitter architectures, both ∆Σ modula-

tion [57] and interleaving [58] have been explored as a means of improving the speed

and in-band performance of DACs through highly-scalable, digital topologies. Pre-

viously, these two concepts have been handled separately or together as a means of

increasing ∆Σ modulator (DSM) performance for baseband applications [29]. In this

work, these two techniques are for the first time independently combined in pursuit of

a reconfigurable method of direct digital-to-RF synthesis. As stated in Chapter 1.2.4,

the confluence of these two techniques provides a unique method of low-noise signal

generation which is suitable for a wide range of wireless applications. In this chapter,

the proposed DAC design is discussed in conceptual terms with the first section high-

lighting the reconfigurable error feedback DSM utilized by the design and the second

highlighting the ideal and non-ideal interleaving of independent ∆Σ modulated chan-

nels. Following this, a brief comparison of the proposed design and a typical Nyquist

rate architecture is given.

3.1 Reconfigurable ∆Σ Modulation

For ∆Σ modulation to be a viable part of a direct digital-to-RF system, the

DSM must support both GHz sample rates and frequency-agile passband synthesis.

34
 Input Qua ntization &
Summation Erro r G eneration
x[n] N+T u[n] y[n]
M N
ɛ1[n]
G(z)
Feedba ck
T
Filte r

Figure 3.1: The error feedback ∆Σ modulator

From the many ∆Σ topologies available, the error feedback DSM shown in Fig. 3.1

is used for this application as its simple architecture lends itself to high-speeds and

re-programmable outputs (i.e. short critical paths in feedback and straight-forward

digital implementation) [59]. Its structure is composed of three independent oper-

ations: quantization, feedback filtering, and input summation; all of which can be

implemented as reconfigurable digital blocks that are optimized for high-speed clock-

ing.

As an overview of the error feedback structure in Fig. 3.1, the modulator output

y1 [n] is composed of N bits and is derived from two internal relationships: the error

generation given in (3.1) and the input summation in (3.2).

ε1 [n] = y1 [n] − u1 [n] (3.1)

u1 [n] = x1 [n] − ε1 [n] · G (z) (3.2)

35
In these expressions, a uniform linear quantizer is assumed with the T -bit quantization

error represented by ε1 [n], the M -bit modulator input by x1 [n], and the N +T bit post-

summation signal by u1 [n]. By substituting (3.1) into (3.2), a relationship between

the modulator input and output is obtained in (3.3).

y1 [n] = x1 [n] + ε1 [n] (1 − G(z)) (3.3)

From this expression, it can be seen that x1 [n] appears at the modulator output

without distortion or delay1 while the noise transfer function (N T F = 1 − G (z))

shapes the frequency content of ε1 [n], creating a low-noise bandwidth. With proper

design, this shaping function can be used to create a low-noise RF passband in the

error spectrum. To achieve reconfigurable operation of this passband, several shaping

functions are implemented concurrently, differing by only delays (z −1 ) and polarity

(±). Selecting among these related functions allows a single DSM to realize a variety

of RF passbands with minimal overhead.

This section describes the operation of the error feedback DSM by highlighting the

three components of its architecture. Additionally, the reconfigurable noise shaping

achieved by the proposed design is detailed.

3.1.1 Digital Quantizer

At the output of the error feedback DSM is the quantization and error generation

block illustrated in Fig. 3.1. Since both the input and output of the quantizer are

digital, the quantization process can be viewed as a second quantization of an already

discrete signal. This accurately describes the loss of resolution which occurs between
1
x1 [n] experiences no latency in (3.3).

36
 Quantizer Truncation Quantizer
2N N
u1[n] y1[n] 2 -1

Digital Output
2N-1
2N-2
2N-2 ΔN

Overflow
2N-3
2N-3

Range
N+T N 3
2
3
1
2 Range
0
1
High Res. ΔN 0 Low Res. 1 2 3 2N-2 2N-1 2N
1
(c) Digital Input
2T
(a)
Truncation Error PMF

Probability
y1[n]
MSBs -1
u1[n] 2T
N
N+T
LSBs
0 -1 -2 -3 -2T+2 -2T+1
T 2T 2T 2T 2T 2T
(b) ɛ1[n] (d) Error Value

Figure 3.2: (a) A digital quantizer functioning over the range [0, 2N ) with a bin
width of ∆N = 1. The error values (the T LSBs) are considered fractional. (b)
Digital truncation, (c) the truncation transfer function, and (d) the probability mass
function (PMF) of ε1 [n] assuming a “busy” u1 [n].

the the N + T bit input and the N bit output, as shown in Fig. 3.2(a). Because of the

high sample rates needed for direct RF synthesis, quantization and error generation

are most efficiently accomplished by truncating the T least significant bits (LSBs) of

u1 [n]. Shown in Fig. 3.2(b), the discarded LSBs are subsequently used as the error

signal, greatly simplifying the error generation process [59].

The transfer function describing the truncation quantizer is given in Fig. 3.2(c),

having a valid input range2 of [0, 2N ). The values of ε[n] that result from truncation
2
The N MSBs are considered whole number while the T LSBs are considered fractional (N .T ).

37
are of the form −i/2T where i is an integer such that i  [0, 2T−1]. Assuming a modu-

lated or “busy” input (i.e. at any time its position within the quantizer interval ∆N

is essentially random) with T sufficiently large, the error can be considered stochastic

[60], exhibiting the probability mass function shown in Fig. 3.2(d). The error signal

can then be modeled as an additive white noise introduced by the truncation quan-

tizer (as done in (3.1)). The power of this added noise is given in (3.4) by calculating

the mean-squared value of Fig. 3.2(d) and removing its DC offset.

2T −1  2  T 2
1 X −i 2 −1 ∆2N ∆2N /22T
ε2RM S = T · − = − (3.4)
2 i=0 2T 2T +1 12 12

Since the truncation quantizer operates on a discrete signal, the expression in (3.4)

represents only the noise power introduced by truncation and not the total noise power

in the output y[n]. This introduced noise can be viewed as the difference between

the output noise (∆2N /12) and the quantization noise initially present in the discrete

input (∆2N +T /12), where ∆N +T = ∆N /2T . This distinction is of critical importance

given that the digital DSM can only shape the introduced noise (ε2RM S ) and not the

total noise power. For this reason, the M -bit input resolution of the DSM sets the

minimum attainable noise floor by determining the amount of unshaped noise in the

input x[n].

3.1.2 Feedback Filter

After truncation, the quantization error is passed through a feedback filter, shap-

ing it away from the desired passband. Because of its high rate of operation, the

feedback filter requires a simple design which lends itself to reconfigurable passband

synthesis. The lowpass (LP) filter function shown in (3.5) satisfies both of these

38
 N y1[n] N y1[n]
x1[n] N+T x1[n] N+T
T T
LSBs 2 LSBs

z-1 ɛ1[n]
z-1 z-1 ɛ1[n]
(a) α = 1 (b) α = 2

Figure 3.3: (a) First order and (b) second order error feedback DSMs.

requirements. By creating an α order filter with only whole-number, binomial coeffi-

cients, a digital implementation of (3.5) requires only adds and shifts which facilitates

a programmable high-speed design.

α
G (z)LP = 1 − 1 − z −1 (3.5)

Fig. 3.3 shows the realization of this feedback filter for both first and second

order designs while Fig. 3.4(a) depicts the noise shaping and pole/zero location that

characterize them. The shaped PSD in Fig. 3.4(a) is plotted as a function of the

system sample frequency fS (using the identity z = ej2πfS ) across the first two Nyquist

zones and is normalized by the unshaped power of ε1 [n]. In the first Nyquist zone,

the output spectrum exhibits a low-noise passband of width fB near DC while the

gain of the filter amplifies the out-of-band noise, reaching its maximum at fS /2.

Due to the sampled nature of the system, the frequency content of the first Nyquist

zone is mirrored about fS /2, producing additional passbands every multiple of fS .

While the first passband (labeled in Fig. 3.4(a)) is of little use for RF synthesis,

higher passbands easily reach into the RF domain for fS at GHz frequencies. These

higher Nyquist outputs hint at the DSMs ability to generate RF signals from image

39
 1st Nyquist Zone 2nd Nyquist Zone 1st Nyquist Zone 2nd Nyquist Zone

LP α=2 BP HP
Shaping Shaping Shaping

First α=2
Passband

α=1 α=1
fB No Shaping
fB fB fB
fS/4 fS/2 3fS/4 fS fS/4 fS/2 3fS/4 fS
Normalized Frequency Normalized Frequency
fS/4 fS/4
α=2 α=2 -z-2

-z-1
fS/2 DC fS/2 DC

(a) (b)
-fS/4 -fS/4

Figure 3.4: (a) Shaping of a first (dashed line) and second (solid line) order LP DSM
with pole/zero locations shown, fB representing the usable ∆Σ bandwidth. (b) BP
and HP DSM shaping with associated pole/zero locations.

replicas [26, 58]. Despite this potential for RF outputs, the filter function given in

(3.5) exhibits sparse spectrum coverage with large portions of the Nyquist band unfit

for RF synthesis due to high out-of-band noise. A DSM using only (3.5) as the

feedback filter would need to widely vary fS to achieve a reconfigurable RF output.

In addition to the inherent difficulties with generating a low-noise, widely-variable

system clock, this method of agile RF synthesis is problematic due to its large impact

on both the system sample rate and output bandwidth.

40
 Reconfigurable Filter
ɛ1[n]·G(z) GLP(z) ɛ1[n]
α=2
GBP(z)

GHP(z)

1st Nyquist Zone 2nd Nyquist Zone 3rd Nyquist Zone

fB fB 2fB fB 2fB fB

fS/4 fS/2 3fS/4 fS 5fS/4

Normalized Frequency

Figure 3.5: Reconfigurable feedback filter implementing LP, BP, and HP functions to
synthesize a variety of low-noise passbands with α = 2.

Instead, this work proposes the use of multiple filter functions to improve the

DSM’s coverage of the output spectrum and minimize the tuning of fS . Using the

substitutions z −1 → −z −2 and z −1 → −z −1 in (3.6) and (3.7), bandpass (BP) and

highpass (HP) filter functions can be synthesized, respectively, from the original LP

design. The shaping that results from these transforms is plotted in Fig. 3.4(b) and

depicts the filter passbands shifted to fS /4 and fS /2 in the first Nyquist zone. These

changes correspond to a rotation in the zero locations of the N T F , also shown in

Fig. 3.4(b).

α
G (z)BP = 1 − 1 + z −2 (3.6)

α
G (z)HP = 1 − 1 + z −1 (3.7)

41
 Taken as a whole, these three filters synthesize output bands at every multiple of

fS /4. This is illustrated in Fig. 3.5 where the feedback filter selects among the three

shaping functions to realize one of several RF passbands. Of note in the output of the

reconfigurable DSM are the contiguous passbands of the LP and HP filters. For these

two filter configurations, multi-Nyquist operation doubles their bandwidth as they are

now composed of passbands in adjacent Nyquist zones. While filter functions capable

of synthesizing other passbands (e.g. 5fS /8) are possible in this configuration [61],

they do not lend themselves to high-speed implementation due to their coefficients

and thus are not considered here.

Because of the similarity between the LP, BP, and HP filter functions, a recon-

figurable implementation is straight-forward. Figure 3.6 illustrates a reconfigurable

design of both the first and second order DSM previously shown in Fig. 3.3 (second

and fourth order in the BP case).

N y1[n] N y1[n]
x1[n] u[n] N+T x1[n] u[n] N+T
T T
M M
LSBs LSBs
LP LP
1 -1 -1 -1
z z 2 z
ɛ1[n] HP ɛ1[n]
HP HP
LP
-1 -2
BP
z-1 z-1 BP z-1
(a) α=1 (b) BP α=2

Figure 3.6: Block diagrams of (a) first order and (b) second order reconfigurable error
feedback DSMs.

42
3.1.3 Input Summation

After the shaping of the feedback filter, the quantization error is summed with

the modulator input, closing the feedback loop. Since this summation feeds directly

into the quantizer, as shown in Fig. 3.1, the resulting sum must lie completely within

the range of the quantizer. This is of critical importance if the quanitzer is realized

by truncation because overflow or underflow does not just saturate the quantizer; it

results in wrap-around and leads to inaccurate modulator outputs. To prevent this,

an upper limit is placed on the value of x[n] such that overflow becomes impossible

under any feedback condition.

Equation (3.8) gives this maximum input value, derived by rearranging the input

summation in (3.2) and substituting the maximum feedback value and quantizer

range. As before, the truncated LSBs are assumed fractional.

2N +T − 1 − (2α − 1) 2T − 1
xM AX = (3.8)
2T
From (3.8) it can be shown that xM AX will have a maximum bus width of N + T bits,

leading to the equivalence M = N + T . For negative values of xM AX , no amount of

backoff ensures proper quantizer operation. Because of this, the number of output

bits must be greater than or equal to the filter order (N ≥ α), resulting in a positive

maximum input. This can be seen in Fig. 3.7 where (3.8) is plotted as a percent of the

fullscale (FS) input. As α is increased, the amount of back-off needed also increases,

significantly reducing signal power for higher orders of noise shaping.

While this analysis assumes the inputs to the summation are positive, it is also

valid for negative inputs which result from the BP or HP filter coefficients. By

ensuring x[n] has some static offset value to guarantee a positive u[n], xM AX can be

43
 100

75

xMAX [% FS] 50
=1
25
=2
=3
0
1 2 3 4 5
Output Bits [N]

Figure 3.7: Maximum input, as a percent of FS, under which quantizer overflow is
eliminated. This is plotted across varying N and α, assuming T = 12.

viewed as a valid input range and the conditions described in (3.8) remain valid. In

this way, the input summation (or subtraction) is designed for all three filters and

guarantees proper modulator operation.

3.2 Multi-Nyquist Operation

As previously described in Section 3.1.3, the multi-Nyquist spectrum of the re-

configurable DSM exhibits low-noise passbands at multiples of fS /4. By setting fS in

the GHz range, these passbands are generated at select RF frequencies and achieve

low-noise outputs due to high OSRs. As an example of the operation of the reconfig-

urable modulator, Fig. 3.8(a) shows a BP-configured DSM generating passbands at

odd multiples of fS /4. Switching to an LP or HP configuration in Fig. 3.8(b) achieves

the same noise floor as the BP DSM but at double the bandwidth, placing passbands

at even or odd multiples of fS /2, respectively. As the DSM sample-rate increases,

44
the output frequency and OSR of each passband increase as well, widening the RF

bandwidth.

However, DAC replica images create a major obstacle to the use of multiple

Nyquist passbands. For an intended output of frequency f0 , there exists replicas

of this signal in every Nyquist band, the frequencies of which are represented by fI

in (3.9).

fI = kfS ± f0 [k = 1, 2, 3, ...] (3.9)

To remove these images, high-order bandpass filtering is typically required, in-

creasing size and complexity while limiting the reconfigurability of the system. In the

case of the BP-configured DSM in Fig. 3.8(a), the filtering can be relaxed by increas-

ing fS , offsetting the signal and image frequencies by fS /2. However, to make use of

the passbands which straddle a Nyquist boundary, the image cannot be pushed out

by increasing fS . As depicted by the HP shaping in Fig. 3.8(b), the output passband

is occupied by both the desired signal and the interfering image.

To mitigate this in-band replica, works such as [62] propose a modified DSM filter-

function to introduce a guard band between the image and the signal. This solution

sacrifices usable bandwidth while only slightly relaxing filter requirements. Instead,

recent works in Nyquist DAC interleaving [27, 63] are leveraged in the proposed

architecture to remove interfering images and reduce system filter requirements.

3.2.1 Interleaving

As described generally in [27] and specifically for a 2-channel system in [63], the

addition of parallel data paths increases the effective sample rate of a system without

45
 1st Nyquist Zone 2nd Nyquist Zone

Signal
fS/2 Image

y[n] PSD
(f0) (fI)
BP fB fB
Reconfigurable BP
DSM
(a)
M N
ΔΣ
fS/4 fS/2 3fS/4 fS
x[n] y[n]
1st Nyquist Zone 2nd Nyquist Zone
LP
fS Signal Image

y[n] PSD
HP (f0) (fI)
fB 2fB 2fB
HP LP

(b)
fS/4 fS/2 3fS/4 fS

Figure 3.8: The reconfigurable DSM: (a) depicts BP shaping with both the signal
and first image shown while (b) depicts LP (blue) and HP (red) shaping with the HP
signal and image in the same passband.

increasing the sample rate of any individual path. Along with this rate increase, it

then becomes possible to cancel all replica images up to the effective Nyquist-rate of

the system.

Unlike previous interleaved DSMs, the proposed architecture does not require error

values to be passed between parallel channels [29], keeping the modulators indepen-

dent of one another and removing inter-modulator speed and timing requirements.

Additionally, the independence of the interleaved channels allows the resulting output

to be easily summed, removing the need for high-speed multiplexing which unduly

increases the sample-rate of the down-stream DAC [29] and folds shaped out-of-band

46
 fS (0°) fS (0°)
x[n] x[2]
yCH1[ne]
x[0] x[1] Even x[ne] ΔΣ DAC
x[3] M N
x[4]
Channel 1
P=2 yT(t)
TS = 1/fS x[6] x[7] Channel 2
x[5]
Odd N
CLK1 fS (0°) x[no] ΔΣ DAC
M yCH1[no]
CLK2 fS (180°)
fS (180°) fS (180°)
(a) (b)

Signal
Shaped Noise Channel 1 DAC ZOH ZOH Shaping Ideal DAC
x[ne] PSD

Images
(f0) ɛCH1[ne] · (1-G(z)) Signal First Image Summed Noise
(f0) Canceled (+3 dB)
fS/2 fS 3fS/2
HP Image HP
fS/2 fS 3fS/2 fS/2 fS 3fS/2 2fS fS/2 fS 3fS/2

Signal Channel 2 ZOH Shaping Non-Ideal DAC

Shaped Noise
x[no] PSD

(f0) SIRR
fS/2 3fS/2 ɛCH2[no] · (1-G(z)) Signal [dB] Suppressed
Summed Noise
(f0) (+3 dB)
Image
fS
HP Image HP
Images DAC ZOH
fS/2 fS 3fS/2 fS/2 fS 3fS/2 2fS fS/2 fS 3fS/2

(c) (d)

Figure 3.9: For interleaved operation, (a) alternate data samples aligned to 180◦
clocks are fed into (b) two parallel DSM and DAC channels. (c) Each DSM output
spectrum is composed of the input signal x[ne,o ] and the uncorrelated error ε1,2 [ne,o ]
shaped by the loop filter. Upon D/A conversion and summation, (d) sinc shaping
resulting from the DAC zero-order-hold (ZOH) is applied to the output and the
unwanted (anti-phase) images are canceled.

noise back in-band [64]. Instead, the DSM and DAC are interleaved together, main-

taining a constant sample-rate throughout the digital and mixed-signal domains.

This scenario is depicted in Fig. 3.9(a-b) for the interleaved-by-two case. Here,

the number of parallel data paths P is set to 2, each path (or channel) consisting of

an independent DSM and DAC. As highlighted by Fig. 3.9(a), data is alternately fed

into each channel, the first channel taking the even indicied data x[ne ] and the second

taking the odd x[no ]. Both channels operate at a clock rate of fS but are phase-offset

47
from one another by 180◦ (360◦ /P ) to preserve the timing of the even and odd data

samples. After passing through the modulators, the channelized data is converted to

the analog/RF domain by the DACs, the outputs of which are summed together to

cancel the interfering images.

Before the D/A conversion depicted in Fig. 3.9(b), the outputs of the two DSMs

are represented by the discrete signals y1 [ne ] and y2 [no ] given in (3.10) and (3.11).

yCH1 [ne ] = x[ne ] + εCH1 [ne ] 1 − G (z) (3.10)

yCH2 [no ] = x[no ] + εCH2 [no ] 1 − G (z) (3.11)

Mirroring the output expression in (3.3), both (3.10) and (3.11) are comprised of two

parts: the original inputs (x[ne ] and x[no ]) and the quantization errors (εCH1 [ne ] and

εCH2 [nx ]) shaped by their respective loop filters. For clarity, the spectrums of these

signals are depicted separately in Fig. 3.9(c), their sums giving rise to the spectrums

of yCH1 [ne ] and yCH2 [no ].

In Fig. 3.9(c), the spectrums of x[ne ] and x[no ] are composed of the desired output

signal and its associated replica images. Due to interleaved sampling, the phases of

these images are rotated by the sampling clock. For the 180◦ clock, the kth image

in the x[no ] spectrum is rotated by k · 180◦ while the image phases in the x[ne ]

spectrum are derived from the 0◦ clock and remain unrotated [27]. As for the noise,

the spectrums of εCH1 [ne ] and εCH2 [no ] have the same power density and shaping,

as seen in Fig. 3.9(c), but are uncorrelated with one another due to the stochastic

nature of the two quantization errors.

48
 6 dB Signal Single DAC
0
Increase Interleaved DACs

Power [dBm]
-30
α=2 Signal Canceled
-60 Image

-90
-120 3 dB Noise N=3
Increase Δ = 1 mA
-150
0.45 0.5 0.55
Normalized Frequency [f S]

Figure 3.10: Simulation comparing a single HP DSM and DAC with an interleaved-
by-two architecture. Interleaving cancels the in-band image, increasing the signal
power by 6 dB and the noise floor by 3 dB.

Fed into the interleaved DACs, these DSM outputs are shaped by the hold function

of the D/A conversion, which is assumed in Fig. 3.9(d) to be a zero-order-hold (ZOH).

For ideal D/A conversion and summation, the desired signal and the even images

add constructively, increasing their output power by 6 dB, while the odd images

are antiphase and cancel. The addition of the quantization error is treated as the

summation of two additive noises, raising the output noise density by 3 dB.

To demonstrate these effects, simulation3 results of the interleaved-by-two archi-

tecture are shown in Fig. 3.10. Using an ideal 3-bit DAC (N = 3) with a 1 mA ILSB

and second order HP shaping, the simulation demonstrates complete image cancella-

tion. In addition, the predicted increases to both the desired signal and noise power

are seen in the output spectrum.

3
The ideal and non-ideal simulation results are obtained from the model given in Appendix A

49
 In general, parallel DSM and DAC channels cancel the first P − 1 images, clearing

their respective Nyquist zones for RF synthesis. Additionally, the signal power of the

interleaved ∆Σ DAC increases by 20 log10 P dB due to the coherent summation of

the signal while the noise density increases by 10 log10 P dB. The difference between

the increase in signal power and noise density causes an increases the resolution of

the interleaved architecture by 0.5(P − 1) bits [27].

3.2.2 Inter-DAC Amplitude and Timing Errors

The rejection of unwanted images by the interleaved DSM and DAC is heavily

dependent on the accuracy of the channel D/A conversion and output summation.

Depicted in Fig. 3.9(d), variations in signal amplitude or timing between the inter-

leaved paths results in non-ideal image suppression. This non-ideality is quantified by

the signal-to-image replica ratio (SIRR), expressed in (3.12) as the difference between

the signal power and the suppressed image power. Based on the similarity observed in

[65] between the interleaved-by-two architecture and an image reject mixer [66], (3.12)

takes into account the error in timing, δt, between the 180◦ system clocks as well as

the amplitude ratio, γ, between the two DAC outputs (ideally γ = 1). The values f0

and fI are once again the signal frequency and the image frequency, respectively.

γ 2 + 1 + 2γ cos(πf0 δt)
 
SIRR = 10 log [dB] (3.12)
γ 2 + 1 − 2γ cos(πfI δt)

In (3.12), it is assumed that the signal and image are frequency adjacent (f0 ≈ fI )

and both undergo the same hold-shaping. While this is a good approximation in the

HP case since f0 and fI are within the same passband, signals and images with

a significant frequency offset experience different magnitudes of hold shaping. To

50
account for this, the ratio between the signal and image shaping is calculated in (3.13)

and applied as a correction to the SIRR value in (3.14); a DAC ZOH is assumed.

   
fI sin (πf0 /fS ) fI
SZOH = 20 log = 20 log [dB] (3.13)
f0 sin (πfI /fS ) f0

SIRRZOH = SIRR + SZOH (3.14)

To verify this expression, Fig. 3.11 shows a simulation4 of the interleaved architec-

ture with amplitude and timing errors injected into one of the interleaved channels.

In this simulation, a variety of error values are simulated for both types of system-

atic mismatch and the resulting outputs are overlayed. As before, these simulations

assume second order HP DSMs with 3-bit DACs, the LSB current of each set to

1 mA.

For comparison, the simulated SIRR values from Fig. 3.11 are plotted in Fig. 3.12(a)

alongside the values calculated by (3.14). The same is also done for a BP-configured

DSM with the results compared in Fig. 3.12(b). In both cases, the simulated values

confirm the validity of the analytical model which describes the system performance

under systematic amplitude and timing errors. A comparison with the LP-configured

DSM is not shown due to the high attenuation of the ZOH shaping for this passband.

4
Refer to Appendix A

51
 Amplitude Mismatch SIRR
26 dB: γ = 0.9
46 dB: γ = 0.99
Signals
66 dB: γ = 0.999
86 dB: γ = 0.9999
HP

Images

(a)

Timing Mismatch SIRR

22 dB: δt = .1/fS
42 dB: δt = .01/fS
Signals 62 dB: δt = .001/fS
82 dB: δt = .0001/fS
HP

Images

(b)

Figure 3.11: Simulation of a second order interleaved HP DSM and DAC (3-bits with
1 mA ILSB ) showing the SIRR for systematic (a) amplitude and (b) timing errors
between the two DACs. The error magnitudes of the overlayed simulations are given
alongside each SIRR.

52
 f0 = 0.49 fS

(a)

f0 = 0.75 fS

(b)

Figure 3.12: A comparison between the calulated and simulated SIRR values for both
(a) the HP-configured DSM and (b) the BP-configured DSM. The percent error of
the timing mismatch is given relative to fS .

53
3.2.3 Intra-DAC Errors

In addition to systematic error between channels, the interleaved design can also

experience amplitude and timing errors within each DAC. In addition to limiting the

SIRR, these non-idealities not only limit SIRR, they also result in non-linear DAC

outputs which reduce the DAC spurious-free dynamic range (SFDR), increase inter-

modulation tones, and corrupt the ∆Σ passband noise-floor. These effects can also

be simulated with the model in Appendix A. Figure 3.13 demonstrates the perfor-

mance degradation due to mismatch errors of 0.0%, 0.3%, and 3.0% within one of

the interleaved DACs. As shown, the DAC images reappear due to imperfect DAC

matching while higher harmonics and noise are folded in-band due to the non-linear

DAC operation.

No Error
0.3% Error
Signals Images 3.0% Error
Harmonic

HP
.45 .475 .5 .525 .55
Normalized Frequency [f/fS]

Figure 3.13: Simulated spectrum with varying current-cell mismatch within one DAC.

54
3.3 Comparison to Nyquist-Rate Architecture

A precise comparison between the proposed ∆Σ DAC and a Nyquist-rate mixing

DACs is critical to the understanding of the trade-offs between the two architectures.

Due to the oversampling and noise shaping of the ∆Σ DAC, a comparison of the

architectures across a large bandwidth is difficult. Instead, the metrics of in-band

SNR and noise power-density are utilized for their relevance to RF signal synthesis.

3.3.1 In-band SNR and ENOB

For a Nyquist-rate DAC (Fig. 3.14(a)), an increase in the number of bits, NN , re-

duces the total quantization noise power throughout the Nyquist band. Additionally,

oversampling can be applied by increasing the sampling frequency, fSN , above the

Nyquist rate to further improve the SNR by spreading the quantization noise outside

of the desired signal band. The in-band SNR of a Nyquist-rate DAC is given by [67]

SN RN = 6.02NN + 1.76 + 10 log10 [OSRN ] [dB] (3.15)

where
fSN
OSRN = (3.16)
2fB

In contrast to Nyquist-rate baseband or mixing DACs, the in-band SNR of the pro-

posed ∆Σ DAC (Fig. 3.14(b)) is determined by several factors: M , N , OSR∆Σ , and

α. Assuming a dual Nyquist zone output and an OSR∆Σ  1, the shaped in-band

noise power of an ideal interleaved-by-two LP or HP DSM and DAC is expressed in

[59]
2 2 π 2α ε2rms
qrms,LP = qrms,HP = 2α+1 (3.17)
22α−1 (2α + 1) OSR∆Σ

55
 Digital Analog RF Digital RF

DAC ΔΣ DAC
NN M N
LPF BPF
fSN LO LO fS fS

LPF
Signal
DAC Output

DAC Output
Increasing
Signal
OSR
(fB) Increasing Increasing
Quant.
Resolution Sample-Rate (fB)
Noise Shaped
Noise

0 fSN1/2 fSN2/2 0 fS1/2 fS2/2

fSN1 < fSN2 (a) fS1 < fS2 (b)

Figure 3.14: Analog synthesis and up-conversion of a signal bandwidth fB showing

the effects of increased resolution and sample-rate for (a) a baseband Nyquist-rate
DAC and (b) the proposed ∆Σ RF-DAC.

where
fS∆Σ
OSR∆Σ = (3.18)
2fB

For the BP-configured DSM, the shaped in-band noise power is given in (3.19) [68].

2 π 2α ε2rms
qrms,BP = 22α+1 2α+1 (3.19)
(2α + 1) · OSR∆Σ

Note that the passband for a BP DSM is located in the middle of the Nyquist zone

such that multi-Nyquist operation does not impact the in-band noise power. The

quantization noise at the input of the ∆Σ DAC due to finite M is added to the

shaped quantization noise to yield a total in-band noise power of

∆2N 1
Q2rms = 2
qrms + 2 · (3.20)
6 (2M −N ) OSR∆Σ

The signal power of the interleaved-by-two ∆Σ DAC is given in (3.21) and is derived

from the maximum DSM input range xM AX , previously defined in (3.8), and the

56
quantization bin width ∆N .
2 ∆2N · x2M AX
Xrms = (3.21)
2
Combining (3.21) and (3.20) yields the in-band SNR of the ∆Σ DAC as expressed in

(3.22).
2
 
Xrms
SN R∆Σ = 10 log10 [dB] (3.22)
Q2rms
For a synthesized bandwidth, fB , a Nyquist-rate mixing DAC and the proposed ∆Σ

DAC can be compared by relating both to the equivalent number of bits (ENOB) in

a critically-sampled converter, as given in (3.23) [67].

SN R − 6.02
EN OB = [bits] (3.23)
1.76

A Nyquist-rate mixing DAC is theoretically interchangeable with a ∆Σ DAC over

a given bandwidth if both DACs exhibit a similar ENOB. Combining (3.15) and

(3.22) into (3.23), the resulting ENOB is shown in Fig. 3.15 for both a Nyquist-

rate and an HP-configured ∆Σ DAC with varying values of N and α5 across OSR6 .

As shown, Nyquist-rate mixing DACs benefit more from increasing NN than from

increasing OSRN . As a result of the difficulty in achieving sufficient linearity with

high fSN and large NN , such systems have historically been limited to a few GHz,

effectively limiting OSRN [11, 12, 24]. In contrast, ∆Σ DACs can achieve a similar

ENOB as Nyquist-rate DACs with fewer bits at the output (N  NN ), facilitating

the use of higher sampling rates and thus larger OSRs [20, 22, 26, 30]. To illustrate

the effect of this difference in OSR, sampling rates of fS∆Σ = 4fSN and fS∆Σ = 8fSN

are used in Fig. 3.15(d) to compare the ENOB of a ∆Σ DAC to that of a Nyquist-

rate DAC (OSRN = OSR∆Σ /4 and OSRN = OSR∆Σ /8). A ∆Σ DAC with α = 2
5
To prevent overflow, N ≥ α.
6 2
The qrms approximation assumes OSR∆Σ  1.

57
 NN=16
22 22
NN=14
NN=12
18 18

ENOB
ENOB
NN=10
14 14
N=5
N=4
10 10
N=3
α=2 N=2
6 6
0 5 10 15 20 0 20 40 60 80
OSRN OSR
(a) (b)

22 22

18 18
ENOB

ENOB
14 14
NN = 14: OSRN = OSR/4
N=5 NN = 14: OSRN = OSR/8
10 10
N=4 N = 3;  = 2
α=3 N=3 N = 4;  = 3
6 6
0 20 40 60 80 0 20 40 60 80
OSR OSR
(c) (d)

Figure 3.15: Theoretical performance of (a) the oversampled Nyquist-rate DAC with
varying number of bits NN , (b) a multi-Nyquist LP or HP ∆Σ DAC with α = 2,
(c) α = 3, and (d) comparison of the ∆Σ DAC and a 14-bit Nyquist-rate DAC with
OSRN = OSR∆Σ /4 and OSRN = OSR∆Σ /8.

can theoretically exceed the performance of a 14-bit Nyquist-rate DAC given that

OSRN = OSR∆Σ /4 > 40 or OSRN = OSR∆Σ /8 > 30. For α = 3, an OSR∆Σ > 10

is sufficient to exceed the Nyquist-rate DAC performance for OSR∆Σ /4 > OSRN .

From this analysis, it is evident that the ENOB (i.e. the noise floor performance)

of the ∆Σ DAC can exceed that of a Nyquist rate design within a given RF passband.

While this analysis does not take into account jitter or non-linearity when estimating

58
ENOB, it can be assumed that a lower resolution design (N < NN ) will be smaller

and experience less non-idealites.

3.3.2 Noise Floor

In addition to the in-band ENOB, a comparison between the in-band noise power-

density of the ∆Σ DAC and that of the Nyquist-rate mixer DAC can be made.

Equation (3.24) gives the noise PSD of the proposed architecture at any frequency f .

In this equation, both the noise shaped by the DSM and the unshaped input noise are

considered. The expression |1−G(f )| represents the magnitude of the reconfigureable

noise transfer functions where G(f ) is one of the filter functions given previously in

(3.5)-(3.7) and where z −1 = e−j2πf /fS∆Σ . Substituting (3.21) and (3.24) into (3.25)

gives the noise power-density in dBc/Hz.

2ε2rms ∆2N
   
2 1
N F (f ) = |1 − G(f )| + (3.24)
fS∆Σ 6 (2M −N )2 fS∆Σ

 
N F (f )
N FdBc (f ) = 10 log10 2
[dBc/Hz] (3.25)
Xrms

Fig. 3.16 plots (3.25) for both HP and BP-configured DSMs, comparing their in-

band noise performance to an ideally up-converted 14-bit Nyquist-rate DAC. For the

∆Σ DAC, variations in α are plotted with fS∆Σ = 2 GHz and N = 3 bits, while

fS∆Σ = 4fSN and fS∆Σ = 8fSN are plotted for the Nyquist design. Due to the noise

shaping and the typically higher oversampling of the DSM, the proposed architecture

achieves a much lower in-band noise PSD than its Nyquist-rate counterparts, meeting

ultra-low in-band noise specifications at the expense of out-of-band noise filtering.

59
 -120 -120

NFdBc [dBc/Hz] -140 -140

NFdBc [dBc/Hz]
N=3 N=3
M = 18 M = 18
-160 fSΔΣ = 2 GHz fSN = 0.25 GHz -160 fSΔΣ = 2 GHz fSN = 0.25 GHz

fSN = 0.5 GHz fSN = 0.5 GHz

-180 =1 -180 =1
=2 =2
=3 NN = 14 =3 NN = 14
-200 -200
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7
Frequency [GHz] Frequency [GHz]
(a) (b)

Figure 3.16: The noise PSD of the proposed ∆Σ DAC for (a) a HP-configured DSM
and (b) a BP-configured DSM in the 2nd Nyquist zone (fS∆Σ = 2 GHz and N = 3).
The noise PSD of an ideally up-converted 14-bit Nyquist DAC is also plotted for
comparison (4fSN = fS∆Σ and 8fSN = fS∆Σ ).

Another important performance metric of the proposed architecture is the average

in-band PSD of the DAC output, found in (3.26) by taking the mean noise PSD of

the output over bandwidth fB .

Q2rms
 
N FAvg dBc = 10 log10 2
[dBc/Hz] (3.26)
fB · Xrms

This average power density mirrors the trends in Fig. 3.15 and is plotted for

varying α and OSR in Fig. 3.17(a). The bandwidth is set to 50 MHz to give absolute

noise-floor values. The performance of a 14-bit Nyquist-rate converter is plotted

alongside that of the proposed architecture, again showing the benefit of the ∆Σ DAC

for increasing OSR and α. Additionally, from this plot we can determine the OSR∆Σ

which gives an equivalent average noise-density to that of a Nyquist-rate converter.

These results are summarized in Fig. 3.17(b) which shows the oversampling ratio

60
 80
NN = 14: OSRN = OSR/4 OSRN = OSR/4

Avg. Noise Density [dBc/Hz]

-130
NN = 14: OSRN = OSR/8
OSRN = OSR/8
60
N = 3;  = 2
-150 fB = 50 MHz
N = 4;  = 3

OSR
40
-170

-190 20
N=3
fB = 50 MHz α=2
-210 0
0 10 20 30 40 50 60 70 80 10 12 14 16
OSR N [bits]
N

(a) (b)

Figure 3.17: (a) The average in-band PSD of the proposed ∆Σ DAC compared
with that of a 14-bit Nyquist-rate design for fB = 50 MHz. In the plot, OSRN =
OSR∆Σ /4 and OSRN = OSR∆Σ /8. (b) The OSR∆Σ needed to achieve equivalent
in-band noise performance to that of an NN resolution Nyquist-rate converter.

required to achieve the equivalent noise floor performance of an NN -bit Nyquist-rate

DAC.

3.3.3 ∆Σ Output Efficiency

In addition to the ENOB and noise floor of the proposed ∆Σ DAC, the efficiency

of the architecture can also be compared to that of a Nyquist-rate design. To do this,

the DAC is assumed to consist of several Class A current cells of various weights,

arrayed to synthesize waveforms from an incoming bit stream. Current sources in

each cell set the current swing of each cell with the output signal realized across

a pair of load resisters. As the current of each cell is increased (and consequently

the output power) the output impedance of each current source is reduced, limiting

the overall DAC linearity. Cascoding is often used to raise current source output

61
 DAC Efficiency Model
VDD VDD
IQ(AC)
OUTP IQ+(DC) IQ-(DC)
RL RL Maximum
Output
Cell i OUTN Signal

Di+ Cell 1 D0-

Cell 0
Transistor
D0+ Network D0- Minimum
D0+ Transistor D0- Voltage
Network
Transistor Overhead
VQ0 V
Network Q0
(VQMIN)
VQ0 VQ0
VQ0 VQ0

Figure 3.18: Model of current-steering DAC used for efficiency calculations.

impedance at the expense of increased voltage overhead. In order to analyze the

impact of this overhead on efficiency, the Class A current-steering DAC model in

Fig. 3.18 is adopted. Two resistors (RL ) represent the DAC output load and ideal

current sources model the transistor network, modulating the output current, IQ .

The voltage VQ is the potential across the transistor network with VQM IN being the

minimum overhead required for linear operation. Equation (3.27) relates the Nyquist

DAC drain efficiency to the DAC LSB current (ILSB ), DAC resolution (NN bits), and

VQM IN .

ILSB RL 2N
N −1
ηClassA = (3.27)
4 (ILSB RL (2N
N − 1) − VQM IN )

The relationship shown in (3.27) demonstrates that the ideal efficiency of a current

steering DAC is 25% with a resistive load (50% with an inductive load) assuming no

62
 ΔΣ Efficiency
Ideal Efficiency Approaches Ideal Efficiency
Class A
Increasing Resolution
Decreasing Order

IQ = 50 [mA]
RL = 50 [Ω]
POUT = 15 [dBm]

(a) (b)

Figure 3.19: Comparison of (a) Class A DAC and (b) ∆Σ DAC efficiency across
VQM IN .

voltage overhead is required (VQM IN = 0). Note that the sampling and frequency

dependent effects of ZOH spectrum shaping are not included in this analysis.

As previously discussed, applying ∆Σ modulation to the DAC input reduces the

number of DAC current cells while enabling low in-band noise. In this scheme, how-

ever, the time-domain results of noise shaping must consume a portion of the output

range, limiting the effective signal amplitude. The voltage overhead required for

quantization noise shaping is directly related to the amplitude backoff value given in

(3.8). Applying (3.8) to (3.27) yields the drain efficiency of the ∆Σ DAC in (3.28).

ILSB RL 2N − 1 x2M AX
η∆Σ = (3.28)
4 (ILSB RL (2N − 1) − VQM IN )

Figure 3.19 illustrates the efficiency of both the Class A (a) Nyquist and (b)

∆Σ DACs. As expected, the efficiency of the Nyquist rate design decreases with

increasing VQM IN . In the ∆Σ design, efficiency approaches that of a Nyquist DAC as

quantization bits (N ) increase (due to reduced overhead required for noise shaping)

or the modulator order decreases (reducing the gain of the noise shaping).

63
 While Class A current-steering architectures remain the preferred choice for high

linearity DACs and modulators, both Class A designs perform poorly when efficiency

is considered (< 25%). The impact of VQM IN on efficiency favors the reduced over-

head of switched mode designs over saturated transistor architectures. This can be

accomplished when the triode conductance of the transistor is utilized to create the

cell current instead of the device transconductance. However, as explain in Chapter

5.1.3, this choice would limit the output impedance of the overall design, leading to

a trade-off between efficiency and linearity similar to that seen in PA design. Given

the stringent IM3 and ACLR requirements of modern communication systems, the

high-linearity Class A topology is favored over that of a more efficient design.

64
 Chapter 4: ∆Σ DAC - First Revision

The goal of the initial RF-DAC implementation is singular: the verification of

the ∆Σ interleaving proposed in Chapter 3. To this end, the first-pass design is

kept simple, relying on conventional circuit building-blocks to prove the concept.

With the design experience and testing results of this revision, subsequent versions

of the proposed RF-DAC can be further optimized for RF performance. This section

outlines this design and its testing, concluding with a discussion of the measurement

results.

4.1 Circuit Design

While the focus of this design is the validation of the concepts in Chapter 3, the

infrastructure needed in support of this goal is also critical to the success of this

endeavor. For this reason, both the DAC design and other supporting structures are

discussed herein.

4.1.1 DAC and Data Retiming

Any implementation of the proposed RF-DAC must have as its first objective

the elimination of both inter-DAC timing (δt) and amplitude (γ) variations so as to

maximize the DAC SIRR. To achieve this, two identical DACs with matched clock

65
distribution and data retiming comprise the core of the design, as shown in Fig. 4.1(a).

Additionally, the identical (unary weighted) DAC current cells in Fig. 4.1(b) are

implemented to further reduce susceptibility to process mismatch [69]. For Nyquist

DACs, this design choice typically leads to a large layout area, increasing timing

errors. The proposed architecture avoids this by limiting the ∆Σ RF-DAC to N = 3

bits.

In addition to these design choices, the current cells in each DAC utilize the avail-

able BiCMOS process to improve high-speed performance. The CMOS transistor

M1 is used as a current source for its low voltage overhead, minimizing power dis-

sipation. Cascoding with M2 improves the linearity of the DAC by increasing the

output resistance of the current source, reducing drain-induced current errors and

data-dependent glitches. The data-switching pair, Q1 and Q2 , are implemented with

SiGe HBTs. Their high fT ensures the cell current is fully commutated within one

clock period. An additional cascode pair, Q3 and Q4 , increases the output impedance

of the current cell, reducing DAC output impedance variations. The SiGe HBTs

exhibit superior output impedance and switching speed compared to their 130 nm

CMOS counterparts, making them the optimum choice for the DAC data path.

66
 LVDS RX Single DAC (b) 50Ω
D02

Retime
Therm
D01
D00
DAC0

3.3V
fS(0°)
D12
VOUT

Retime
Therm
D11
DAC1 50Ω
D10

(c)
ILSB1
fS(180°)
Ref. ILSB0
2·fS /2 Test Chip PCB
(a)

Current Cell
IOUTp IOUTn IOUTp
DFF Driver Current Cell
D D Q Q3 Q4
IOUTn VB3
fS-0º Q
D Q1 Q2 D
DAC0 – 7 Cells

Devices W L VB2 M2
M1,M2 30 um 500 nm 1 mA
Q1,Q2 120 nm 2 um VB1 M1
Q3,Q4 120 nm 3 um
(b)

Bias CMOS Inverter Buffers

Latch
D Digital
Level
Diff Output
100Ω

Shifting
Amp
Buffer
D
Bias
On-Chip Latch
Data Feedback
AC Coupling
Single Channel LVDS RX
(c)

Figure 4.1: (a) The block diagram of the interleaved RF-DAC. The (b) schematic of
DAC0 and (c) the diagram of one LVDS channel.

67
4.1.2 Data I/O and Loopback Testing

The previously designed LVDS receiver, pictured in Fig. 4.1(c), enables the high-

speed input of BP and HP ∆Σ modulated data into the DAC. Given the 3-bit res-

olution of each interleaved DAC, only six LVDS receivers are needed to feed the

design. With its small on-chip capacitor, the design replaces several bulky, on-board

capacitors with fully integrated ones consuming less than 0.06 mm2 . As detailed in

Chapter 2, the AC coupled RZ input of the pulse receiver minimizes baseline wan-

der and requires no data encoding. This simplifies the DAC test-setup requirements,

enabling a singular focus on the designs interleaved performance. In addition to

the pulse receivers, the transmitter used for LVDS loop-back testing is also included

alongside the DAC. In this way, the on-chip data latching of the design can be tested

separately from the DAC, allowing the design to be validated in stages and aiding

any debugging procedures.

4.2 Measurement

As with the LVDS receiver, the first revision of the proposed ∆Σ RF-DAC is

fabricated in a 0.13 µm SiGe BiCMOS technology. Interleaved clock generation, clock

routing, and both 3-bit DACs are implemented on-chip while the ∆Σ modulation

is located off-chip, accomplished via pre-compiled ∆Σ data created within Matlab.

For testing, this data is loaded into an FPGA and fed into the design through the

previously-verified LVDS receivers. From this architecture, the intrinsic amplitude

and timing accuracy of the design can be tested without the added overhead of an

on-chip DSM. Additionally in this revision, the inclusion of calibration circuitry is

foregone in favor of a simple first proof-of-concept. This test-setup is depicted in

68
 FPGA LVDS RX 50Ω
D12

Retime
Therm
ΔΣ Data N=3 D11
(DSM1) D10
DAC1

3.3V
fS(0°)
D22
VOUT

Retime
Therm
ΔΣ Data N=3 D21
(DSM2) DAC2 50Ω
D20

ILSB1
fS(180°)
Ref. ILSB0
2fS /2 BiCMOS Test Chip
2fS PCB
Clock

Figure 4.2: Test setup of the first ∆Σ RF-DAC revision.

Fig. 4.2, showing the data generation, FPGA input, and DAC functionality of the

design.

4.2.1 Test Infrastructure

The flip-chip die (Fig. 4.3) is mounted onto a custom 4-layer PCB (Fig. 4.4). This

board mediates all chip connections; the LVDS data is brought in from the east and

west, clock input from the south, and the DAC output is routed north. Due to limited

board space, the loopback clock and data are routed vertically off the board. Chip

voltages are connected through on-board header pins and careful attention is paid to

decoupling. Large (µF ) decoupling capacitances are used at the header inputs and

smaller capacitances (nF and pF ) are located next to the chip for close-in voltage

conditioning. For signal integrity, all high-speed lines are routed on the top layer with

50 Ω lines. Internal layers are used for high capacitance power routing and the bottom

layer carries low frequency signals and biases. Input current biases are created from

69
 4 mm

LVDS RX LVDS RX
2 mm Clocking
0.6 mm

0.3 mm

Interleaved DACs

Figure 4.3: Photograph of the first ∆Σ DAC prototype showing LVDS input, clock
generation, and the 0.18 mm2 DAC core.

high-precision potentiometers (labeled) and switched in via SPDT DIP switches. Off

board, the LVDS lines are connected to a VC707 Virtex 7 evaluation board on which

second-order ∆Σ modulated data is loaded and fed into the design.

As shown in Fig. 4.2, the 180◦ clocks necessary for interleaving are generated

by dividing the off-chip reference. Coarse timing adjustment is available on-chip to

ensure accurate data/clock alignment. However, phase accuracy between the two

clocks (δt in (3.12)) is determined by layout symmetry. One available adjustment is

the LSB current of each DAC, which can be set independently, allowing for manual

tuning of γ. At the DAC output, the interleaved design is connected to an on-board

bias-T to seperate the input DC bias from the output RF which is measured with an

Agilent PXA spectrum analyzer.

70
 DAC Output
Loopback Loopback
DAC1 LVDS Input

DAC0 LVDS Input

Voltage Bias-T
Header Chip
Current Bias
POTs

Voltage
Clock Input Header

Figure 4.4: First Revision test board on which the interleaved DAC is mounted.

4.2.2 Results

Figure 4.5(a-b) demonstrates all three configurations of the proposed RF-DAC: (a)

BP outputs at either fS /4 or 3fS /4 and (b) a HP output at fS /2. Evident in the plots

is the distinctive noise shaping of the DSMs and the ZOH sinc response, attenuating

the fS /2 output by ≈ 3 dB and the 3fS /4 output by ≈ 10 dB. At fS = 2 GHz, the

integrated DAC core consumes a total of 55 mW from a 3.3 V source.

In Fig. 4.5(c), the HP output spectrum around fS /2 is given for both a single and

interleaved DAC. Since the signal lies at the Nyquist boundary in this ∆Σ configura-

tion, a single DAC produces an in-band image (red). For the interleaved case (black),

71
an SIRR of 65 dB is measured without calibration, validating the intrinsic matching

between the two DACs and within the clock routing. Independently adjusting ILSB0

improves gain matching, bringing the SIRR up to 72 dB. With γ now assumed ideal,

the SIRR measurement corresponds to an inter-DAC timing error of δt < 80 f s.

While the inter-DAC gain and phase error determine the SIRR, intra-DAC mis-

matches set the in-band SFDR and noise performance (previously shown in Fig. 3.13).

In the implementation of the proposed ∆Σ RF-DAC, a linearity of 99% is obtained

(Fig. 4.6) while an SFDR of 58.5 dB and an SNR of 54.5 dB are achieved over a band-

width of 50 M Hz. The SNR performance, as well as the output frequency, output

power, and DSM type are compared to the second prototype and to other published

designed in Table 5.2.

72
 1st Nyquist Zone 2nd Nyquist Zone 1st Nyquist Zone 2nd Nyquist Zone
-10 -10
ZOH ZOH
Sinc Sinc
-30 -30
Power [dBm]

Power [dBm]
(c)
-50 -50
HP: fS/2
-70 BP: fS/4 -70
fS = 2 GHz
BP: 3fS/4 RBW = 5 MHz fS = 2 GHz
RBW = 5 MHz
-90 -90
0 0.5 1 1.5 2 0 0.5 1 1.5 2
Freqeuncy [GHz]
Frequency Freqeuncy [GHz]
Frequency
(a) (b)

1st Nyquist Zone 2nd Nyquist Zone

Single DAC
-10
Interleaved DACs
-11 dBm
-30
Power [dBm]

SFDR:
Signal Image 58.5 dB
-50
RBW = 100 kHz SIRR: Suppressed
fS = 2 GHz 72 dB Image
-70

-90

0.98 0.99 1 1.01 1.02

Frequency [GHz]
(c)

Figure 4.5: Measured spectrums at fS = 2 GHz. (a) BP and (b) HP outputs from 0-2
GHz. (c) Close-in HP spectrum showing both single DAC and interleaved outputs.
(Not de-embedded)

73
 DAC0 Cells - Error
2

Percent Error
0

-2
1 2 3 4 5 6 7
Cell Number
DAC1 Cells - Error
2
Percent Error

-2
1 2 3 4 5 6 7
Cell Number

Figure 4.6: The current error of each DAC.

4.2.3 Take Aways

The test results of the first prototype verify both the theory behind the interleaved

∆Σ architecture as well as its practical implementation. Without the aid of on-chip

calibration, the system SIRR is well in excess of 60 dB, pushed above 70 dB with

systematic DAC amplitude adjustment. However, the IM3 and SFDR of the design

are both below 60 dB, requiring improvement in the second revision of the DAC. For

the low SFDR depicted in Fig. 4.5, the degradation is a result of a third harmonic

tone folding back in-band. This tone is traced back to deterministic jitter in the

retiming FF, alleviated in the subsequent revision by the CML architecture discussed

in Chapter 5.1.3. The poor IM3 of this design arises from static current-cell non-

linearities, removed by amplitude calibration in the second iteration. Additionally,

the marginal SNR performance arises from stochastic jitter in the full-scale (inverter)

74
clock drivers, remedied with high-power, low-jitter CML clock drivers. Also of note in

the first DAC revision is the low (≈ 80 f s) timing error attainable through careful on-

chip layout. This error value is later used in the design of the second revision timing

calibration (Chapter 5.1.3), ensuring a minimum SIRR performance equivalent to

that of the first revision.

75
 Chapter 5: ∆Σ DAC - Second Revision

Given both the success and the shortcomings of the first revision, the second

DAC prototype adds additional capability to the design, such as an on-chip DSM

and per-cell DAC calibration, as well as remedy several issues which effected the

SFDR, IM3, and SNDR performance. This revision (Fig. 5.1) is comprised of two

parallel data paths, each aligned to separate 180◦ clocks derived from an off-chip

2x source. Interleaved samples are received from an FPGA through seven LVDS

channels parallelized into two 14-bit buses to accommodate the data rate required by

the now on-chip DSM. Incoming data is offset off-chip to account for the pipelining

of the DSM computation. A data path bypassing the DSM is also implemented

to enable stand-alone DAC testing (as in the first revision) and calibration. After

∆Σ modulation, the 3-bit DSM outputs are thermometer encoded, re-timed by clean

clocks, and driven into the DAC current cells. To ensure accurate interleaving and

linear DAC performance, fine amplitude and timing adjustments are also implemented

via SPI register control.

76
 Time-Interleaved, Reconfigurable ΔΣ DAC
LVDS 3 ΔΣ Bypass
Bias-T 50 Ω
Alignment MASH
Channel 1 7 7 14 3 Binary DAC &
& ΔΣ to
Data Data Path
S2P Thermo
α
BP/HP AMP
Balun
fS (0°) RFOUT
Channel 1
÷2
Channel 2
fS (180°)
LVDS 2·fS
α AMP
Alignment BP/HP
Channel 2 7 7 14 3 Binary DAC &
& MASH to
Data Data Path
S2P ΔΣ Thermo

Bias-T 50 Ω
3

SPI Interface Clock Input

Figure 5.1: Block diagram of the implemented DSM and DAC

5.1 Circuit Design

With the increased size and complexity of the second DAC, several new circuits are

included on-chip. These are highlighted in the following section with special attention

payed to the redesigned data retiming and DAC core.

5.1.1 Serial Data Input

Since the on-chip ∆Σ function operates at the DAC GS/s rate, the architec-

ture requires significant I/O bandwidth for each interleaved 14-bit data stream. To

meet this requirement, the low-power LVDS receivers discussed in Chapter 2 are

implemented on-chip. Despite the high-speed capability of the asynchronous LVDS

receivers (10 Gb/s), the speed through each channel is limited due to the need for

77
 Bias Data Feedback
1.4 pF Latch Delay Line D Q xi+1[n]
IN
Level

100Ω
Diff
Shifting
Amp 16-tap
Buffer
IN
Bias
D Q xi[n]
1.4 pF
Latch CLK (fS)
On-Chip
AC Coupling LVDS Receiver

Figure 5.2: LVDS receiver and serial-to-parallel operation.

alignment and sampling of the incoming data. Because of this, the data I/O is de-

signed to receive at least a 4 Gb/s double-data rate input stream, enabling fourteen

2 Gb/s data input channels with 7 receivers per DAC. In addition, three LVDS chan-

nels can be configured to bypass the DSM for standalone DAC testing. As before,

the receiver is AC coupled on-chip with 1.4 pF capacitors, minimizing layout area.

Following the receiver, incoming data is passed through a 16-tap adjustable delay line

to compensate for off-chip clock-to-data skews of up to 1.2 ns, as shown in Fig. 5.2.

Once data is correctly aligned to the on-chip clock, the 4 Gb/s data from each channel

is latched and separated into two 2 Gb/s streams via two flip-flops (FF) operating on

opposite clock edges.

5.1.2 ∆Σ Modulator

Given the fundamental link between sample rate and bandwidth in ∆Σ modula-

tion, a significant focus of recent DSM work has been the high-speed (GS/s) operation

of DSMs, achieved through a combination of novel digital architectures [18, 20], phase

78
unrolling [70], pipelining [71], and time interleaving [29, 30]. However, existing archi-

tectures target baseband synthesis, utilizing LP DSMs to generate near-DC signals.

In contrast, this chip implements a time-interleaved design which includes both the

DSM and DAC, as discussed in Chapter 3. This architecture increases the effec-

tive sample rate of the system without requiring a high-speed mux and a subsequent

higher-frequency clock domain to reconstruct the modulated signal. The proposed

DSM also leverages its all-digital architecture to switch between multiple filter func-

tions and shaping orders.

Architecture

For the proposed DSM to switch between multiple filter functions while achieving

RF sample rates, a MASH-11 architecture, depicted in Fig. 5.3, is used to pipeline

the order of the design. Two first order stages, consisting of single tap filters (5.4(a)),

reduce feedback latency compared with a higher-order, single stage DSM. As in 3.3,

the first MASH stage shapes the quantization error ε1 [n]. This error is also passed to

the second stage whose output is given by

y2 [n] = ε1 [n] + ε2 [n] (1 − G(z)) (5.1)

Multiplying this output by H(z) allows y2 [n] to be scaled such that ε1 [n] is com-

pletely canceled in the DSM output summation and the remaining error ε2 [n] is

shaped with a higher order NTF [59]. By setting H(z) = G(z) − 1, the MASH output

becomes

y[n] = x[n] − ε2 [n] (1 − G(z))2 (5.2)

79
 Switching between the second stage output and zero, as depicted by the output

combining in Fig. 5.3, allows the design to be configured for first or second order

shaping. To further maximize the speed of the modulator, each MASH stage is itself

pipelined using 1-bit unit cells. In this way, the logic operation performed during a

single clock period is reduced to that of a 1-bit subtractor with the borrow propagated

via a ripple architecture. A total of eleven of these cells [0:10] are used to shape the

LSB quantization error in each MASH stage while MSB cells account for any borrow

signal emerging from the noise shaping.

Within the LSB cells and the output combining, reconfigurable feedback filters

are used to realize both BP and HP shaping. Since the desired filter functions differ

by a single delay, as highlighted in Chapter 3.1.2, implementing both simply requires

alternating between two delay values (Fig. 5.3(b)). Altogether, the pipelined structure

allows the proposed DSM to synthesize the outputs depicted to Fig. 5.3(c): first and

second order shaping of both BP and HP passbands. While this architecture requires

staggered data input and several alignment stages, increasing the power, area, and

latency through the design, it also creates a robust, highly modular architecture based

on the design of a single bit cell.

80
 Reconfigurable MASH-11
2nd Order

3 Bit ΔΣ
Output (y[n]) HPHP
-1 -1
1st Order z-1z z-1z
BP
BP
H(z)
MASH-11 3
Stage Combining
Architecture z-2
-2

y[n] Stage 1 [11:13] zz-2

z-1
x[n] y1[n] Stage 2 [11]
st
1 Order 3 MSBs x13 z-14 3
x11:13[n] x12 z-13
-ɛ1[n] 2nd x11 z-12
G(z) y1[n] y2[n]
Order
Stage 1 Ripple Borrow
z-1 z-1
Ripple Feedback
H(z)
Filter
y2[n] x10 z-11 z-1
-ɛ2[n]
G(z) 11 LSBs G(z) G(z)
x1:10[n] z-1 z-1
Stage 2

x1 z-2 z-1

z-1 G(z) z-1 G(z)

x0 z-1 z-1
G(z) G(z)

Stage 1 [0:10] Stage 2 [0:10]

Figure 5.3: MASH-11 modulator pipelined with 1-bit unit cells. The bit cells and
MASH stages can be configured for BP or HP outputs and for first and second order
shaping.

1st Nyquist Zone 2nd Nyquist Zone

Borrow
Signal Image
y[n] PSD

Cascaded Cells
(f0) fS/2 (fI)
-ɛ1[n] Critical
x1 z-1 Path BP fB fB
1 α=2
HP α=1
z-1 z-1 fS/4 fS/2 3fS/4 fS
z-1 BP
α=1 G(z)
Borrow
1st Nyquist Zone 2nd Nyquist Zone
-ɛ2[n]
x0
y[n] PSD

1 Signal Image
HP (f0) (fI)
HP 2fB
z-1 z-1 α=2
BP α=1
α=1 G(z)

fS/4 fS/2 3fS/4 fS

(a) (b)

Figure 5.4: (a) Two reconfigurable bit cells, and (b) multimode ∆Σ shaping with
both the signal and first image shown.

81
DSM Bit Cell

As previously mentioned, the 14-bit on-chip DSM is pipelined using 1-bit unit cells.

This approach allows an increase of the DSM speed up to the latency of the feedback

(FB) path. Shown in Fig. 5.5, this critical path consists of only the subtract logic and

the HP/BP switches. For low latency, the subtraction is computed with an optimized

1-bit ripple carry add [72] with the borrow logic implemented in parallel. In the

subtraction, the final inversion of S̄ to S is relocated from directly after the function

(grey) to after the delay FFs, allowing the BP and HP switches to be implemented

with tri-state inverters (black) instead of slower, un-driven transmission gates (grey).

Minimum area and power true single phase clock (TSPC) FFs [73] are driven by the

tri-state inverters, reducing the FB latency by 40 ps in simulation, increasing the

timing margin by 8% of the clock period at 2 GS/s.

Next Cell
xi[n] B_In

Borrow D Q
Borrow Logic B_Out
xi[n] TSPC
FB
B_In B_Out S
D Q
TSPC
Critical Path
HP
Subtract Logic xi[n]
FB T-Gate
xi[n] B_In
FB
FB HP_EN
B_In S Q D
T-Gate BP
BP_EN TSPC

Figure 5.5: The single bit feedback cell used to pipeline the proposed reconfigurable
DSM and showing the relocation of the S̄ inversion.

82
5.1.3 Data Path and DAC

Due to the digital nature of the DSM, the noise shaping and linearity of the

modulator output are ideal. However, the subsequent DAC core limits the fidelity of

the RF output, directly determining the SFDR and SNDR performance of the RF

signal. This requires a DAC core design which achieves much higher linearity than a

standard 3-bit Nyquist design. Shown in Fig. 5.6, the core of each interleaved DAC

is comprised of seven unary-weighted current switching cells. The unary architecture

exhibits low data-dependent glitches at the DAC output and relaxes the constraints

on current matching compared to the conventional binary and segmented schemes [69,

74].

DAC Current Cells

The proposed design uses SiGe HBTs, mitigating nonlinearities caused by data-

dependent impedance modulation [75]. Though SiGe HBTs are large, the DAC core

comprises only seven unary cells allowing for a compact layout with reduced routing

parasitics [76] and timing skew [77].

The current source in the DAC cell is implemented via CMOS transistors and

placed outside the DAC cell array for compact interdigitation and optimized matching

as shown in Fig. 5.6. The output of each current source is routed to an individual

cell, where it is cascoded with an HBT just before the data switches, providing high

output impedance for the switched pair by shielding them from the interconnect

capacitance. The data switches are implemented using HBTs to provide superior

switching speed and output impedance as compared to their CMOS counterparts.

Additionally, cascoded HBTs shield the data switches from the DAC output, further

83
increasing the cell output impedance. A CMOS bleed current (35 µA) is added to each

cascode to improve SFDR by keeping the cascode transistors “on”, thereby reducing

the data-dependency of the cell output impedance and reducing the settling time

when the corresponding data switch is turned off [17].

VDIG VDIG VDIG VDIG VA VA VCBIAS

VA VA
P P Q Q IBLEED
VA QD QD
Regenerative
Latch QD QD
D D P P VCCS Unary Bit Cell
Q Q
9 Bit I CAL
CLK CLK CLK CLK
VDBIAS VCS 1 mA
VDBIAS
VBIAS VBIAS
CML Retiming FF CML Data Driver Calibrated Current Source

Dac Core
Binary to
Therm.

3 Bit ΔΣ D0 Q0 QD 0
Input D Q D Q
QD 0 QD 0
tCAL D0 Q0 QD 0
Clean D Q D Q
CLKIN CLK ___
CLK ILSB

ICAL

200 mV
400 fs 130 fs 15 fs 45 fs

260 μm

Data Path 1 Data Path 2

Matched
Clock 250 μm Current Clock
Buffer Routing Buffer
Decoupling Decoupling
Capacitors Capacitors

DAC
220 μm Core
Inter-digitated
Current Sources
500 μm

Current Source
Calibration

Figure 5.6: Schematic and layout of the data path and DAC current cells highlighting
the minimized deterministic jitter.

84
Data Path

To maximize the linearity and noise performance of the DAC current cell, any data

dependent timing effects on the data inputs to the cell must be minmized. While the

impact of deterministic jitter has been analyzed in Nyquist DACs [78], to the author’s

knowledge, no such analysis has been published for ∆Σ DACs. Figure 5.7(a) shows

behavioral simulations of the DAC in the presence of deterministic jitter at the input

to each current cell. A peak-to-peak deterministic jitter of just 1% of the clock period

(3.3 ps at 3 GS/s) results in degradation in SFDR and SNR of nearly 20 dB and 6

dB, respectively. To minimize this effect, the data path, shown in Fig. 5.6, utilizes

CML structures to re-time the data and drive appropriate levels to the data switches

in the current cell. Full-scale CMOS data from the thermometer encoder drives the

first CML latch. While this stage removes much of the data dependent jitter induced

by the encoder and preceding circuitry, some remains (≈ 130 fs of p-to-p jitter) due to

the unbalanced differential input created by the inverter delay and due to the CMOS

inputs overdriving the CML latch, pushing it out of saturation. The remaining jitter

is nearly eliminated by a second CML latch tha tis driven with all CML signals. The

re-timing latches are followed by two stages of CML buffers. These buffers slightly

increase the deterministic jitter because they are not clocked, however, they reduce

the clock feedthrough from the latches and provide a voltage swing that is designed

to minimize data-dependent jitter in the current cell switches [79]. Supply voltage

induced deterministic jitter is mitigated by separating the power supply for the re-

timing data path and clock drivers from the rest of the digital circuitry on the chip.

Figure 5.6 shows the simulated eye diagram at the outputs of the second data driver

85
 SFDR SFDR SFDR

SFDR / SNR (dB)

SNR SNR SNR

Peak-to-peak Jitter (% of Period) Current Mismatch σI/I (%) Timing Mismatch σt/t (%)
(a) (b) (c)

Figure 5.7: SFDR and SNR performance across variations in (a) deterministic jitter,
(b) static current mismatches and (c) static timing mismatches.

in the data path. The deterministic jitter is reduced to 45 fSP P (0.014%), resulting

in a negligible degradation in SFDR and SNR.

Amplitude and Timing Calibration

Even with the size and matching benefits of a low-bit ∆Σ DAC, the proposed

multi-bit design (N = 3) still faces stringent requirements on linearity and timing to

ensure that the rejected image and other spurious tones do not degrade the SNDR

of the system. Static current mismatch within one DAC can manifest as spurious

tones in the output while current mismatch between the interleaved DACs decreases

the effectiveness of image cancellation, as described in (3.12). A Monte Carlo (MC)

simulation performed on the interleaved ∆Σ DACs identifies the impact of static cur-

rent mismatches, yielding the SFDR (including the replica image spur) in Fig. 5.7(b).

Each MC run includes 1500 iterations, and the 97.7% yield line is plotted using a

95% confidence level. To ensure an SFDR above 70 dB, a mismatch tolerance of

σI /ILSB = 0.03% is required. To achieve this in a reasonable area, the CMOS current

86
source is designed for a 0.3% mismatch, and a 9-bit calibration DAC is used to fine

tune the current of each cell. Similarly, static timing mismatches in the DACs can

also degrade the SFDR and SIRR. Fig. 5.7(c) gives the MC results of DAC SFDR

for various static timing mismatches between cells. As shown, a timing mismatch of

0.013% is required to achieve 70 dB of SFDR. To account for this possible mismatch,

a 5-bit timing adjustment circuit is implemented via the interpolative clock buffer

shown in Fig. 5.8. In this design, CLKIN and CLK IN are separately weighted by

the current adjustment and then summed at the output node, allowing the design to

shift the clock in ≈ 90pS steps across a range of < 2.8 ps.

Clock Jitter

While mismatches dramatically affect the DAC SFDR, they have less impact

on in-band noise performance. This is highlighted in Fig. 5.7(b-c) where the ∆Σ

DAC SNR is plotted with respect to MC mismatch for a 5% bandwidth (0.05 · fS ).

However, dynamic effects, such as clock jitter, significantly affect SNR performance.

To demonstrate this, Fig. 5.8 plots the SNR for two cases: that of global clock jitter

(all DAC cells experiencing the same jitter) and local clock jitter (each DAC cell

has statistically independent jitter). For low RMS jitter, the SNR of both global

and individual clock jitter approach an ideal value set by the noise shaping of the

DSM. As jitter increases, the effects of global jitter add coherently and degrade the

SNR more severely than that of individual cell jitter, which adds incoherently. This

difference is leveraged in the design of the CML clock buffer tree by locating all

timing adjustment wihin each DAC cell, as shown in Fig. 5.8, minimizing its effect on

global clock jitter. Additional improvements in SNR can be obtained by allocating

more of the clock distribution to local clock buffers, however, this would significantly

87
 VCLK VCLK VCLK VCLK
2.8 ps
Local Buffer
Delay
Tuning
CLK
CLK

CLKIN CLKIN CLKIN CLKIN

VCBIAS VCBIAS 5 Bit VCBIAS

tCAL
Differential Weighting
(7 buffers,1 per bit cell)

Ideal: No Jitter
Local Buffers

9 Driver Stages
CML RMS Jitter: 0.63 ps
1 GHz

2 GHz

Global 3 GHz
Buffers HP SNR BW: 5% fS
(7 Stages,
2.1mm Clock Jitter: Global Driver
routing) Clock Jitter: Local Driver
9-Stage CML Driver

÷2
Chip Clock Input
Clock Distribution

Figure 5.8: The DAC clock distribution scheme and simulation of SNR for both local
and global drivers.

increase the power consumption of the chip and is thus avoided in this design. For

the implemented 9-stage buffering, extrated simulation estimates a total RMS jitter

of 0.63 ps, plotted in Fig. 5.8 for 1 GHz, 2 GHz, and 3 GHz operation. The model

used for this simulation is given in Appendix B.

As shown by the preceding analysis, the capability added to the second DAC revi-

sion aims to significantly improve the DACs RF performance, leveraging the learning

of the first revision to produce a high quality direct digital-to-RF system.

88
 Analyzer

RF IN

3 mm x 5 mm
Output
Virtex 7 TX Virtex 7 TX
DAC1 DAC2

600 x 600 µm Current 600 x 600 µm

Sources
DAC

7 channels
7 channels

750 x 750 µm
DSM1 DSM2

Clock
Gen.
LVDS LVDS
RX x7 RX x7
SPI

2x Clock Input

Figure 5.9: Photograph of the 3 mm x 5 mm test chip.

5.2 Measurement

The second revision of the proposed ∆Σ DAC is again fabricated in a C4-bumped

0.13 µm BiCMOS process and packaged flip-chip-on-board for testing. The 3 mm x

5 mm chip, pictured in Fig. 5.9, integrates fourteen LVDS receivers, two reconfigurable

DSMs, the CML data path, and the interleaved 3-bit DAC core along with divide-

by-two clock generation and digital SPI control, depicted in the functional diagram

in Fig. 5.10.

5.2.1 Test Infrastruction

A second board revision builds on the first design, mirroring the on-chip additions

of the second chip. Pictured in Fig. 5.11, the board adds additional LVDS inputs,

SPI control pins, divided clock output, and more accurate current biasing. The test

89
 DAC Output
Per Channel Per Channel
7 Channel Input 7 Channel Input
Data Delay CLK Data Delay
LVDS LVDS
Calibration LO
LVDS Adjustment Measurement LVDS

7 7
7 Gb/s Max Adjustment 7 Gb/s Max
DeMux DeMux
1 and Calibration Per Cell Amplitude Per Cell Amplitude 1
7 7 7 7
Output Adjustment Adjustment Output
Select Select
3 3

Σ Modulator Retiming Retiming Σ Modulator

14 Bits In; 3 Bits Out DAC DAC 3
14 Bits In; 3 Bits Out
Order = 1-3; HP & BP 3 Data Select Data Select Order = 1-3; HP & BP

Calibration Calibration
Shift Register Shift Register
Per Cell Clock Clock Phase Per Cell Clock
Adjustment Adjustment Adjustment
CLK CLK
2 16
SPI Interface
Aug 2014 Clock Input Interleaved Σ DAC Chip

Figure 5.10: Functional diagram of the second DAC revision.

setup for this design, shown in Fig. 5.12, utilizes a VC7215 Virtex 7 evaluation board

to feed interleaved data samples into the DAC at double the on-chip data rate. DAC

waveform data is created from custom Matlab scripts and preloaded into the FPGA.

After the D/A operation, the differential DAC output is taken from board mounted

SMAs, converted to a single-ended output with a Picosecond Pulse Labs 5310A balun,

and measured using a spectrum analyzer. A more detailed overview of the testing

procedure is given in Appendix C with the SPI register functions and controls given

in Appendix D.

90
 DAC Output

Bias-T

DAC1 LVDS Input

DAC0 LVDS Input

Loopback Loopback

Chip
Current
Bias
SPI Header

Div. Clock Voltage

Out Header
Clock In

Figure 5.11: Revision 2 test board on which the interleaved DAC is mounted.

Spectrum Analyzer

FPGA Clock
Input

2x Clock
Source

VC7215 5310A PPL

Virtex 7 Balun
SPI
Control Flip-Chip ΔΣ DAC PCB

Figure 5.12: Test setup of the interleaved ∆Σ DAC.

91
Figure 5.13: Measured 100 MHz HP passband at 1.0 GHz showing (a) single and (b)
two-tone tests as well as the 50 MHz passband at 1.5 GHz with (c) single and (d)
two tone tests. The results include a measurement loss of ≈ 7 dB

5.2.2 Results

In Fig. 5.13, the variable shaping of the on-chip DSM is demonstrated at a sample

rate of 2 GS/s, showing first and second order shaping for the HP and both BP

passbands. These outputs are attenuated by the sinc shaping of the DAC zero-order

hold, resulting in a ≈ 10 dB attenuation of the second BP passband. Ideal second

order shaping highlights the in-band noise floor of the design which is limited by the

jitter and non-linearity of the DAC, folding noise back in-band. Figure 5.14(a) shows

a single tone output spectrum of the DAC at a sample rate of 2 GS/s and with second

order HP shaping. Since the design is implemented without reconstruction filtering,

measurements are taken within the ∆Σ passband, a 100 MHz bandwidth (5% of

fS ). The uncalibrated DAC exhibits an SIRR of 45.9 dB, the image dominating the

spurious free dynamic range. To calibrate the DAC amplitude, the output power of

92
 Single DAC
-7.6 dBm Interleaved DACs -13.6 dBm
Calibrated
Performance Interleaved with Cal.
Image Calibrated
fS = 2 GHz Performance
RBW = 100 KHz Image w/o Cal:
fS = 2 GHz
-53.5 dBm
SFDR: 76.2 dB RBW = 30 KHz
SIRR: 76.2 dB IM3: 80.3 dB
Image w/ Cal:
SNDR: 59.5 dB -83.8 dBm

-95.2 dBm -93.9 dBm

-84.1 dBm

(a) (b)

Calibrated -17.5 dBm -24.1 dBm

Performance
fS = 2 GHz Calibrated
RBW = 100 KHz Performance
SFDR: 65.4 dB fS = 2 GHz
SNDR: 56 dB RBW = 30 KHz
IM3: 67.9 dB

-82.9 dBm -92 dBm -92.8 dBm

(c) (d)

Figure 5.14: Measured 100 MHz HP passband at 1.0 GHz showing (a) single and (b)
two-tone tests as well as the 50 MHz passband at 1.5 GHz with (c) single and (d)
two tone tests. The results include a measurement loss of ≈ 7 dB

each cell is measured off-chip and set to a common power reference while the timing

of each cell is adjusted to minimize the system SIRR.

After amplitude and timing calibration, the interleaved performance improves sig-

nificantly, achieving an SFDR and SIRR of 76.2 dB, as well as an SNDR of 59.5 dB for

a 0.997 GHz output. The SNDR performance correlates very well with the simulation

results of Fig. 5.8, indicating that random jitter from the clock buffering is the dom-

inating factor. Including ≈ 7 dB of measurement loss, an output power of −7.6 dBm

93
Figure 5.15: Measured second order HP output spectrum across an 800 MHz band-
width at a sample rate of 2 GS/s. The noise density is labeled at 100 MHz steps and
ideal noise shaping is overlaid for reference.

is recorded, closely matching extracted simulation results. Within the same HP band-

width, Fig. 5.14(b) shows a calibrated IM3 of −80.3 dBc from a two tone test with

1 M Hz spaced inputs. In Fig. 5.14(c-d), one and two tone tests are also shown for the

second BP output. Within a 50 M Hz bandwidth (2.5% of fS ), the calibrated DAC

achieves an SFDR of 65.4 dB and in-band SNDR of 56 dB while measuring an IM3

of −67.9 dBc. Note that the BP results are slightly degraded compared to the HP

mode, due to the large zero-order hold attenuation in the second Nyquist zone. In

Fig. 5.15, a wideband plot of the second order HP output is given. Over the 800 MHz

bandwidth, the measured noise density is labeled at 100 MHz intervals and compared

well to an ideal ∆Σ noise floor.

94
 BP Modulation SFDR
IM3
ACLR

SFDR
SIRR
IM3
ACLR HP Modulation

(a) (b)

Figure 5.16: DAC performance across varying frequencies for (a) HP mode and (b)
BP mode.

The performance of the DAC across sample rate for second order HP modulation

is shown in Fig. 5.16(a). Interleaving achieves a minimum SIRR of 73.5 dB due to ac-

curate amplitude and timing calibration between each DAC. The SFDR performance

remains above 65 dB up to an output frequency of 1.5 GHz. The IM3 is measured at

a minimum of −80.3 dBc up to 1 GHz and increases to −67 dBc at 1.5 GHz. Figure

5.16(b) shows the measured results of the BP modulation using the second passband,

yielding an SFDR above 65 dB and IM3 better than −62 dBc across the frequency

band.

In Fig. 5.17, the DAC sample rate is set to 3 GS/s, utilizing both the HP and BP

output bands to synthesize 5 M Hz WCDMA signals at 1.5 GHz and 2.25 GHz, re-

spectively. The DAC achieves an ACLR of −65.4 dBc in the HP mode, and −59.3 dBc

in the BP mode. Figure 5.16(a-b) plots the DAC WCDMA ACLR performance

across sample rate for a 5 M Hz bandwidth in both the HP and BP passbands. In

Fig. 5.16(b), a sample rate of 2.6 GS/s is used to create a BP 1.95 GHz WCDMA out-

put achieving an ACLR of −60.2 dBc. Figure 5.18 shows the generation of a 20 M Hz

95
Figure 5.17: ACLR of a 5 MHz WCDMA signal at 3 GS/s in the (a) 1.5 GHz HP
band and (b) 2.25 GHz BP band.

LTE signal at 1 GHz (HP, 2 GS/s) and 1.95 GHz (BP, 2.6 GS/s), yielding an ACLR

of −66.4 dBc and −59.2 dBc, respectively.

In Table 5.1, the power consumption of the primary functional blocks is given at

2 GS/s along with the respective layout area. The 9-stage low jitter CML buffers

consume 342 mW with the layout distributed across chip while the two pipelined

DSMs use a combined 218 mW . With technology scaling beyond 0.13 µm, the power

96
Figure 5.18: ACLR of a 20 MHz LTE bandwidth in the (a) 1 GHz HP band and (b)
1.95 GHz BP band.

consumption of the DSMs and drivers is expected to drop considerably due to both

lower supply voltage and reduced digital loading. The low-distortion DAC current

cells consume 53 mW from a 3.3 V supply while the retiming path consumes 174 mW

divided between a 1.5 V digital supply and a 2 V driver supply. The input LVDS

consumes a total of 56 mW for all fourteen input receivers.

97
 Table 5.1: Power Consumption at 2 GS/s and Active Area Breakdown

Block Pwr. @ 2 GS/s Area

[mW ] [mm2 ]
Current Cells (3.3 V ) 53 0.255
Retiming Data Path 174 0.130
DSM (1.5 V ) 109 (x2) 0.360 (x2)
CML Clocking (2.3 V ) 342 -
LVDS RX (1.8 V ) 4 (x14) 0.0115 (x14)
Total Chip 843 15

5.2.3 Comparison

Table 5.2 compares the interleaved ∆Σ DAC performance at 2 GS/s and 3 GS/s

with other ∆Σ mixing-DACs and transmitters. Among the designs, the proposed

architecture uniquely enables the use of HP ∆Σ modulation by suppressing the first

DAC image below −76 dBc. For sample rates above 1 GS/s and bandwidths above

15 M Hz, the proposed DAC exhbits the highest SFDR, IM3, and SNDR among

previously reported ∆Σ DACs. Due to its excellent linearity, the highest WCDMA

ACLR is achieved, while first reporting an LTE ACLR of −66.4 dBc for a 1 GHz

output.
Table 5.2: ∆Σ RF-DAC Measurement Comparison

Proc. ∆Σ Sample Out. Out. SFDR IM3 SNDR BW ACLR Core

Ref. Tech. Arch. Mod Rate Freq. Pwr. [dB] [dBc] [dB] [M Hz] WCDMA/LTE Pwr.
[nm] [GS/s] [GHz] [dBm] [dBc] [mW ]

[19] 180 Mix. LP 0.514 0.942 -14.65 75 -70.8 53 ‡ 17.5 -/- 36

CMOS DAC
[20] 130 Mix. LP 2.625 5.25 -8 52 - 49 200 -/- 10
CMOS DAC
[21] 250 Mix. BP 0.25 1.062 -5.4 75 -64.7 72 ‡ 15 -/- 12.75
CMOS DAC
[26] 90 Direct LP 4.0 1.0 3.1 - - 53.5 50 -53.6/- 71
CMOS TX LP† 2.6 1.95 -8.6 - - 46.5 30 -44.3/- 39

Rev 180 Direct HP 2.0 1.0 -7.5∗ 58.5 52.5 54.5‡ 50 -62/-59.8 55
1 BiCMOS TX BP† 1.5 -13.8∗ 73 -55.2 51.6‡ 50 -/-

Rev 180 Direct HP 2.0 1.0 -0.6∗ 76.2 -80.0 59.5 100 -67.2/-66.4 53
2 BiCMOS TX 3.0 1.5 -5.5∗ 69.0 -67.3 55.7 150 -65.4/-
†
BP 2.0 1.5 -10.5∗ 65.5 -67.9 56.0 50 -63.0/-
3.0 2.25 -16.6∗ 65.2 -62.0 53.3 75 -59.3/-
† nd ‡ ∗
2 Nyquist Zone SNR Testing losses removed

98
 In contrast with the first ∆Σ DAC revision, the second design displays across-

the-board performance gains (with the exception of data path power consumption

owing to the CML topology in revision 2). The improved SNR is a direct result of

the low jitter clock and data paths, the reduced IM3 is due to improved matching

from calibration, and the SFDR increase is a result of low data dependency of the

output timing. Overall, the interleaved ∆Σ architecture is validated by the two

design revisions which show predictable RF performance allowing for incremental

design improvement. With increased scaling, the topology will see commensurate

improvements in speed, power, and RF performance.

99
 Chapter 6: Conclusion and Future Work

6.1 Work Summary and Conclusion

This work describes the theory, design, application, and testing of an interleaved,

multi-mode ∆Σ DAC, developed as a means of direct digital-to-RF synthesis for

highly configurable transmitters. The design demonstrates reconfigurable RF syn-

thesis via a high-speed, low-resolution DAC fed with ∆Σ modulated data. Utilizing

differential parallel data paths, the design cancels the first DAC image, leveraging

the 1st and 2nd Nyquist zones for RF output. The interleaved architecture uniquely

facilitates the use of HP ∆Σ modulation by canceling the image replica that falls

in-band, enabling the wide HP passband for RF output. The DAC can also be con-

figured for BP modulation to enable signal generation in the first or second Nyquist

zone.

The implementation of this design is enabled by a novel LVDS pulse receiver. The

fully integrated receiver architecture utilizes on-chip AC coupling to remove stringent

common-mode standards, facilitate optimum sense-amp biasing, and reduce the area

consumed by the AC coupling capacitors. By accurately sizing the input capacitors,

the receiver is able to attenuate incoming data, creating return-to-zero pulses which

limit ISI jitter without compromising sensitivity. The design implements a latch

100
within the receiver amplifier using a toggled bias structure which holds long runs

of invariant data without decay. In this way, the design removes the need for data

encoding, simplifying the high-speed data input of the proposed DAC. To verify its

operation, the proposed pulse receiver is tested from 1-10 Gb/s and achieves a BER

of < 10−13 at a peak efficiency of 0.54 mW/Gb/s.

With the means of high-speed data I/O verified, the proposed DAC is implemented

in two revisions. The first version of the DAC, integrating only the clock generation

and low-resolution DACs, achieves an SIRR of 72 dB, validating the proposed image

cancellation. However, the design performs only moderately with respect to SFDR,

IM3, and SNDR. To improve upon this performance, the deficiencies of the first design

are analyzed and a second revision is implemented.

In the redesigned DAC, per-cell amplitude and timing calibration is used to min-

imize mismatch and improve IM3; the architecture leverages SiGe HBTs with CML

drivers in the DAC core to further maximize the system linearity and improve SFDR

(due to reduced data-dependent jitter). A CML clock distribution is also used to

reduce random timing jitter, significantly improving the output SNDR. The DAC

achieves an interleaved image cancellation above 76 dB with both BP and HP ∆Σ

shaping validated. At a sample rate of 2 GS/s, the proposed design achieves an

in-band SFDR of 76.2 dB, IM3 of -80 dBc, and SNDR of 59.5 dB over a 100 MHz

bandwidth. The high spectral purity allows the DAC to generate WCDMA and LTE

signals with an ACLR of -67.2 dBc and -66.4 dBc, respectively, at 1 GHz. Compared

to recently reported ∆Σ DACs, the results show the highest linearity performance

when using sample rates greater than 1 GHz, and bandwidths greater than 15 MHz.

101
6.2 Future Work

The interleaved, multi-mode ∆Σ RF-DAC described in this work promises ex-

panded bandwidth and greater flexibility over current ∆Σ RF-DAC designs. As scal-

ing continues to reduce power consumption and improve on-chip digital processing,

such all-digital methods of RF synthesis will become a crucial part of SDR trans-

mitters. Critical to the development and integration of this work into larger wireless

systems are two broad categories of future research: the improvement of the cur-

rent design with advanced process technology and the optimization of the design for

system integration.

6.2.1 Scaling Improvements

While the proposed design achieves state-of-the-art performance for a direct digital-

to-RF architecture, much can be gained from its implementation in a more advanced

process technology. As is commonly known, CMOS technology scaling has two great

advantages - the reduction of power consumption via reduced supply voltage (and

smaller circuit loading) and the increased processing speed due to decreased para-

sitic capacitances. If the topology were designed into such processes, it would see

significant improvements in system performance.

First, the reduced power consumption of a 65 nm or 45 nm technology would

greatly reduce the ∼ 800 mW of power consumption, especially in the high-speed

DSM, the low-jitter CML clock distribution, and the CML data path. This improve-

ment would make the architecture more suitable for low-power mobile applications.

Second, the reduced capacitive loading of an advanced process would allow the in-

tegrated DSM to either 1) dramatically increase its sample rate or 2) implement

102
 High Speed Improved
Implementation Configurability

Data
ΔΣ
ΔΣ DAC
DAC
MOD 3-bit
3-bit
Rx MOD Output
Spectrum
Reduced
Power

Figure 6.1: Advantages of process scaling

complex filter functions capable of more passband frequencies. Currently, the design

is limited to 3 notch frequencies while operating up to 3 GS/s. Such advancement

would go a long way in boosting the flexibility and performance of the proposed ar-

chitecture. While highly-linear SiGe HBTs are not currently available in the cited

process nodes, circuit techniques such as return-to-zero outputs can be used to reduce

the non-linear effects of standard CMOS devices.

6.2.2 System Integration

Further afield, for the proposed RF-DAC to be successfully integrated into a high-

functioning wireless system, several key steps need to be taken:

ˆ DAC Resolution Trade-Off Analysis

ˆ High-Power (or III-V) Implementation

ˆ High-Speed Digital Mixing

ˆ Reconfigurable Filter Design

103
Resolution Analysis

In the preceding work, a 3-bit design has been assumed for both its simple imple-

mentation and also its challenges (non-linearity and matching requirements) which

require significant design work to overcome. However, by leaving the DAC resolution

static, many design trade-offs such as in-band/out-of-band SNR and reconstruction

filter requirements were ignored. An analysis of this trade space, while design specific,

would be necessary for future development.

High-Power Design

The ultimate goal of many digital transmitters is the complete removal of all

analog/RF signal conditioning, including the power amplifier. However, as discussed

in this work, the efficiency of this architecture does not lend itself to high power

(watt level) outputs. Instead, the end goal of this design would be to drive a high-

power PA without the need for any buffering. To accomplish this, the power of the ∆Σ

modulated output needs to be increased from 0 dBm to around 10−15 dBm. This can

be done in one of several ways, but the most ideal would be a III-V implementation of

the RF-DAC. Given the unique low-resolution topology of the design, it is uniquely

suited for a high-power process technology which are typically susceptible to high

mismatch and poor integration levels. Key to this implementation would be a high

speed CMOS to III-V digital interface capable of transporting the ∆Σ modulated

data across the voltage domain barrier.

Mixing

Assumed in the RF-DAC design is an up-converted data source preceding the

DSM, pictured in Fig. 6.2. This operation, typically implemented with a clocked

104
LO and an AND gate, takes a baseband signal up to RF frequencies. For system

level integration, such a block would be implemented on-chip before the DSM. The

practicalities of such up-conversion, however, have not yet been explored for the

proposed design.

Filtering

Data
ΔΣ
ΔΣ DAC
DAC
MOD 3-bit
3-bit
Rx MOD Output
High Power Spectrum
Up-conversion Optimized Output
Resolution

Figure 6.2: Future work for system integration

Reconfigurable Filtering

Finally, and probably most importantly, the post-DAC reconstruction filtering

must be addressed before system integration. Currently, the in-band performance of

the RF-DAC meets the noise floor, spectrum mask, and spurious tone requirements

of many wireless systems, but the out-of-band noise does not. This high noise is

a result of the DSM shaping and would corrupt surrounding transmissions if left

unattenuated. The challenge of this filter lies in its need for reconfigurable operation

matching that of the DSM feedback filter. Several possibilities for the filter design

exist (e.g. N-path filtering, semi-digital filtering, reconfigurable LC filtering), but

such a design has yet to be implemented for the proposed RF-DAC.

105
6.3 Final Thoughts

Altogether, this work gives only a glimpse into the potential of direct digital-to-

RF synthesis as a means of reconfigurable transmitter design. With future work,

and as digital processing becomes simultaneously cheaper and more powerful, digital

radio systems will become increasingly useful for both their adaptability in changing

environments and their ease of deployment. Though we may look beyond specifica-

tions and speculate about the future capabilities of such systems, their true power

will only be comprehended in hind-sight. Through the presented paradigm or others,

highly digital architectures will continue to revolutionize the capability and ubiquity

of wireless communications.

106
 Appendix A: ∆Σ DAC Model

This appendix contains the Matlab/Simulink model used to test the ideal perfor-

mance of the interleaved, ∆Σ DAC as well as the DAC performance under ampli-

tude, phase, and current cell mismatch. The DSM output is calculated by a Simulink

model, given in Fig. A.1, and the mismatch and channel summation are subsequently

accomplished in code.

Matlab Script:
1
2 clear all; % reset everything
3
4 %% Simulation Variables
5

6 nmod = (2ˆ18)/2ˆ3; % number of samples

7 kmod = 1024; % number of startup samples to remove
8 acmag = 5; % Input AC mag (DC = 5, Max Peak <= 10)
9 tQ = 25e-11; % Simulink sample rate (2*fs of singlel DAC)
10 Bin Num = 8135*8+5; % Frequency of signal by bin: 8022*8+1
11 % 8033*8+5 8042*8+1 8135*8+5 8072*8+7
12 % 8072+9 8022+1 7967+7 8135+7
13 % BP: 4020+1 12020+1 12050+1 12210+1
14 M = 3; % Number of output bits DS
15 T = 15; % Number of truncated bits DS
16
17 Mode = 0; % Mode = 0 HP - Mode = 1 BP
18
19 delta = .001; % ILSB [A]
20 R = 50; % Single Ended Termination [Ohms]
21 Offset = 2ˆ(M+T-1)+2ˆ(M+T-2); % DS static offset
22
23 % Calculated Signal Power
24 P Signal = ((2ˆ(M+T-1)-1)/(2ˆT)*delta/2ˆ.5*acmag/5)ˆ2*R*2/.001;
25
26 if Mode == 0
27 delay = 2;

107
28 elseif Mode == 1
29 delay = 4;
30 end
31
32 fmod = Bin Num / (nmod*tQ); % Input Frequency
33
34 %% Mismatch Control Variables
35

36 % Toggle on/off Phase and Gain mismatch in the DACs

37 PhaseMismatch toggle = 0; %[0 = off; 1 = on]
38 GainMismatch toggle = 0; %[0 = off; 1 = on]
39
40 % Gain Mismatch
41 if GainMismatch toggle == 1
42
43 % Overall Gain of DAC0
44 G0 = 1.001;
45
46 % Cell by cell gain of DAC0 (size must be equal to DAC
47 % resolution due to assumption of fully unary architecture)
48 %G0SYS = [1 1 1 1 1 1 1];
49 G0SYS = [1 1.0012 .9886 .9966 .9897 .9977 1.0035];
50
51 % Could add random Num function here for random mismatch
52 G0RND = [1 1 1 1 1 1 1];
53

54 % Overall Gain of DAC1

55 G1 = 1;
56
57 % Cell by cell gain of DAC1 (size must be equal to DAC
58 % resolution due to assumption of fully unary architecture)
59 %G1SYS = [1 1 1 1 1 1 1];
60 G1SYS = [1 1.0046 .9931 .9874 1.0023 1.0006 1.009];
61
62 % Could add random Num function here for random mismatch
63 G1RND = [1 1 1 1 1 1 1];
64 end
65
66 if PhaseMismatch toggle == 1
67
68 % Amount of oversampling determines resolution of phase error
69 % High oversampling values consume large amounts of memory
70 Oversample = 10;
71

72 % Systematic DAC0 phase error

73 PHI0 = 1;
74
75 % Per cell phase error
76 PHI0SYS = [0 0 0 0 0 0 0];
77

78 % Random function could be added here

108
 79 PHI0RND = [0 0 0 0 0 0 0];
80

81 % Systematic DAC1 phase error

82 PHI1 = 0;
83
84 % Per cell phase error
85 PHI1SYS = [0 0 0 0 0 0 0];
86

87 % Random function could be added here

88 PHI1RND = [0 0 0 0 0 0 0];
89
90 else
91 % No oversampling needed if there is no phase error
92 Oversample = 1;
93 end
94
95 %% Run Simulink
96
97 sim('DS DAC HP Interleaved Model3 Nbit'); %Error subtraction DS
98

99 % This model does not check for overflow and handles it ideally by
100 % expanding the value of the output past the resolution of the DAC
101 %(+ or -)
102
103 %% Adding Mismatch
104

105 % Systematic and Cell Timing Error - Waveform adjusted for error
106 if PhaseMismatch toggle == 1
107 HP DS RFDAC0P = zeros(1,Oversample*length(HP DS RFDAC0));
108 HP DS RFDAC1P = zeros(1,Oversample*length(HP DS RFDAC1));
109
110 for x = 1:length(HP DS RFDAC0)
111 for y = 1:Oversample
112 for z = 1:2ˆM-1
113
114 % First DAC
115 if HP DS RFDAC0(x) >= z*delta && ((x-1)*...
116 Oversample + y+PHI0+PHI0SYS(z)+PHI0RND(z)) ...
117 <= (Oversample*length(HP DS RFDAC0))
118
119 HP DS RFDAC0P((x-1)*Oversample + ...
120 y+PHI0+PHI0SYS(z) + PHI0RND(z)) = delta + ...
121 HP DS RFDAC0P((x-1)*Oversample + ...
122 y+PHI0+PHI0SYS(z)+PHI0RND(z));
123 end
124
125 % Second DAC
126 if HP DS RFDAC1(x) >= z*delta && ((x-1)*...
127 Oversample + y+PHI1+PHI1SYS(z)+ ...
128 PHI1RND(z)) <= (Oversample*...
129 length(HP DS RFDAC1))

109
130
131 HP DS RFDAC1P((x-1)*Oversample + ...
132 y+PHI1+PHI1SYS(z) + PHI1RND(z)) =...
133 delta + HP DS RFDAC1P((x-1)*...
134 Oversample + y+PHI1+PHI1SYS(z)+PHI1RND(z));
135 end
136 end
137 end
138 end
139
140 HP DS RFDAC0 = HP DS RFDAC0P;
141 HP DS RFDAC1 = HP DS RFDAC1P;
142
143 clear HP DS RFDAC1P HP DS RFDAC0P
144 end
145
146 % Systematic and Cell Gain Error - Waveform adjusted for error
147 if GainMismatch toggle == 1
148 for x = 1:length(HP DS RFDAC0)
149 for z = 1:2ˆM-1
150
151 if HP DS RFDAC0(x) == z*delta
152 HP DS RFDAC0(x) = delta * sum(G0SYS(1:z).*...
153 G0RND(1:z))*G0;
154 end
155

156 if HP DS RFDAC1(x) == z*delta

157 HP DS RFDAC1(x) = delta * sum(G1SYS(1:z).*...
158 G1RND(1:z))*G1;
159 end
160 end
161 end
162 end
163
164 %% Computing PSD
165
166 HP DS RFDAC = 2*R.*(HP DS RFDAC0(1:Oversample*...
167 ((nmod+kmod)*2)+1) + HP DS RFDAC1(1:Oversample*...
168 ((nmod+kmod)*2)+1));
169
170 RBW = (.5/tQ)/(nmod/2); % Desired plotting RBW
171
172 % Truncate Model Output
173 last HP DS RFDAC = HP DS RFDAC(length(HP DS RFDAC)-nmod * ...
174 Oversample+1:length(HP DS RFDAC));
175
176 % FFT Calculation
177 FFT HP DS RFDAC = fft(last HP DS RFDAC, nmod*Oversample);
178
179 % PSD Calculation
180 FFT V = FFT HP DS RFDAC(1:nmod*Oversample/2+1);

110
181 PSD = abs(FFT V/(nmod*Oversample)).ˆ2./(2*R*.001);
182 %PSD = (tQ/Oversample)/(nmod*Oversample)*...
183 %abs(FFT V).ˆ2./(2*R*.001);
184
185 PSD(2:end-1) = 2*PSD(2:end-1);
186
187 % To dB
188 dB Pout = 10*log10(PSD);
189
190 % Frequency - X Axis
191 F = (0:nmod*Oversample/2) / (nmod*tQ);
192
193 %% Analytical Output - can be compared with Simulated Spectrum
194

195 Erms = delta*R*4/(12)ˆ.5*(tQ)ˆ.5;

196
197 NTF HP 2 =(4) .* (exp(-2i.*pi.*F.*tQ)) .* cos(2*pi.*F.*tQ) .* ...
198 cos(2*pi.*F.*tQ)*Erms;
199 NTF HP 2(Bin Num+1) = (P Signal)ˆ.5;
200 NTF HP 2 = NTF HP 2. *sin(2*pi.*F.*tQ)./(2*pi.*F.*tQ);
201
202 Power HP 2 = (abs(NTF HP 2)).ˆ2./(R*.001)*RBW;
203 Power HP 2(Bin Num+1) = Power HP 2(Bin Num+1)*(R*.001)/RBW;
204
205 %% SNR Calculation: assumes signal is within bandwidth
206

207 SNR BW = 50e6; % SNR Bandwidth for Calculation

208
209 BinWidth = 1/(nmod*tQ);
210 CenterF = max(F)/2;
211 LowF = CenterF - SNR BW/2;
212 HighF = CenterF + SNR BW/2;
213
214 IndexLow = find(F >= LowF,1);
215 IndexHigh = find(F >= HighF,1);
216
217 NoiseP Calc = sum(Power HP 2(IndexLow:IndexHigh)./...
218 RBW.*BinWidth) - Power HP 2(Bin Num+1)./RBW.*BinWidth;
219 SignalP Calc = Power HP 2(Bin Num+1);
220 SNR Calc = 10*log10(SignalP Calc)-10*log10(NoiseP Calc);
221
222 ImageP Sim = 0;
223 if PhaseMismatch toggle == 1 | | GainMismatch toggle == 1
224 ImageP Sim = PSD(nmod/2-Bin Num+1);
225 end
226
227 NoiseP Sim = sum(abs(PSD(IndexLow:IndexHigh))./RBW.*BinWidth);
228 SignalP Sim = PSD(Bin Num+1);
229 SNR Sim = 10*log10(SignalP Sim)-10*log10(NoiseP Sim - ...
230 (SignalP Sim+ImageP Sim)*BinWidth);
231

111
232 %% Plotting Result
233

234 % Plot First two Nyquist zones

235 figure('Color',[1.0 1.0 1.0],'Position',[1 1 1111 599])
236
237 plot(F/1e9,dB Pout,'LineWidth',3,'Color', [200/255 0 0])
238 hold on
239 plot(F/1e9,10*log10(Power HP 2),'LineWidth',3,'Color', [0 0 0])
240
241 grid on;
242 set(gca, 'Box', 'on', 'Linewidth', 2,'fontname','Arial',...
243 'fontsize',32);
244 %set(gca,'Color',[.941 .941 .941])
245 set(gca,'XLim',[0,1/tQ/2e9])
246 set(gca,'YLim',[-150,10])
247
248 xlabel('Frequency [GHz]')
249 ylabel('Power [dBm]')
250 title('RF-DAC Spectrum')
251

252 h = legend('Simulated: Non-Ideal','Analytic: Ideal',...

253 'Location','SouthWest');
254
255 % Plot close in Spectrum
256 figure('Color',[1.0 1.0 1.0],'Position',[1 1 1111 599])
257

258 plot(F/1e9,dB Pout,'LineWidth',3,'Color', [200/255 0 0])

259 hold on
260 plot(F/1e9,10*log10(Power HP 2),'LineWidth',3,'Color', [0 0 0])
261
262 grid on;
263 set(gca, 'Box', 'on', 'Linewidth', 2,'fontname','Arial',...
264 'fontsize',32);
265 %set(gca,'Color',[.941 .941 .941])
266 if Mode == 0
267 set(gca,'XLim',[0.45/tQ/2e9,0.55/tQ/2e9])
268 elseif Mode == 1
269 set(gca,'XLim',[0.2/tQ/2e9,0.3/tQ/2e9])
270 end
271 set(gca,'YLim',[-160,20])
272
273 xlabel('Frequency [GHz]')
274 ylabel('Power [dBm]')
275 title('RF-DAC Spectrum')
276
277 % Calculate Spectrum Characteristics
278 OutputPower = max(dB Pout(2:end));
279
280 NF = 10.*log10(mean(10.ˆ(dB Pout(Bin Num+3:Bin Num+103)./10))) ...
281 - 10*log10(RBW);
282 SIRR = dB Pout(Bin Num+1) - dB Pout(2*(nmod/4+1-Bin Num-1)...

112
283 +Bin Num+1);
284 SFDR 3rd = dB Pout(Bin Num+1) - dB Pout(4*(nmod/4+1-Bin Num-1)...
285 +Bin Num+1);
286
287 % Display values
288 text(0.45/tQ/2e9+.001,-10,['P {OUT} = ' num2str(round(...
289 OutputPower*10)/10) ' dBm'], 'FontSize', 14, ...
290 'BackgroundColor', [1 1 1]);
291 text(0.45/tQ/2e9+.001,-25,['NF = ' num2str(round(NF*10)/10)...
292 ' dBm/Hz'], 'FontSize', 14, 'BackgroundColor', [1 1 1]);
293 text(0.45/tQ/2e9+.001,-40,['SIRR = ' num2str(round(SIRR*10)/10)...
294 ' dB'], 'FontSize', 14, 'BackgroundColor', [1 1 1]);
295 text(0.45/tQ/2e9+.001,-55,['SFDR 3 r d = ' num2str(round(...
296 SFDR 3rd*10)/10) ' dB'], 'FontSize', 14, ...
297 'BackgroundColor', [1 1 1]);
298
299 h = legend('Simulated: Non-Ideal','Analytic: Ideal',...
300 'Location','NorthEast');

113
Figure A.1: Simulink model of the multi-mode, interleaved ∆Σ DAC.

114
 Appendix B: ∆Σ DAC Random Jitter Model

This appendix contains the Matlab model used to test the SNR performance of

the interleaved, ∆Σ DAC with random data jitter. The DSM output is computed,

oversampled, and then random jitter is applied systematically to each DAC or indi-

vidually to each DAC cell.

Matlab Script:
1 function [SNR Ideal, SNR AllJitter, SNR DACJitter, ...
2 SNR CellJitter] = DS 2ndOrderHP Jitter1(...
3 Num Samples, R0, ILSB, Resolution, Bits,...
4 Fs, Bin, SNR BW, OSR, Per Cell,...
5 Cell Systematic Timing Error1, ...
6 Cell Systematic Timing Error2, ...
7 Cell Systematic Amplitude Error1, ...
8 Cell Systematic Amplitude Error2, Sigma, Plot)
9

10 % Simulation of 2nd Order, High Pass DS DAC with Clock Jitter

11 % Must be run by Run DS 2nd OrderHP Jitter1.m
12 % Can put an % before function to use as regular .m script
13 % Created by: Jamin McCue
14

15 %% Beginning Calculations
16
17 % Frequency of Sine wave
18 Fsine = Fs*Bin/Num Samples;
19
20 % Samples per Sine Wave
21 % # of Samples / Samples per Cycle = Integer
22 % ie. (80*512*2 - 1) / 4.0959 = 10000
23 Samples per Cycle = Fs/Fsine;
24
25 %% Interleaved Signal Generation
26

27 % Starting Phase
28 Phase = 0;
29

115
30 % Signal Backoff for DS and setting of DC
31 if Bits == 4
32 Signal Amplitude = .74; % N = 4
33 Signal DC = (2ˆResolution-1)/2 + 2ˆ(Resolution-4);
34 elseif Bits == 3
35 Signal Amplitude = .62; % N = 3
36 Signal DC = (2ˆResolution-1)/2 + 2ˆ(Resolution-3)+ ...
37 2ˆ(Resolution-4);
38 elseif Bits == 2
39 Signal Amplitude = .25; % N = 2
40 Signal DC = (2ˆResolution-1)/2 + 2ˆ(Resolution-2) + ...
41 2ˆ(Resolution-4) + 2ˆ(Resolution-5) + 2ˆ(Resolution-6);
42 end
43

44 % Phase Increment of Sine Wave

45 Phase inc = 2*pi/Samples per Cycle;
46 % Initialize Variable
47 Output = zeros(1,Num Samples);
48 % Initial Input: Sine Wave
49 for x = 1:length(Output)
50
51 Output(x) = round(Signal Amplitude*(2ˆResolution-1)/2* ...
52 sin(Phase + (x-1)*Phase inc)+Signal DC);
53 end
54
55 % Error bits are Fractional
56 Output = Output / 2ˆ(Resolution - Bits);
57 % Creation of the two channel data
58 Output1 = Output(1:2:end);
59 Output2 = Output(2:2:end);
60
61 %% Plot Sine Wave
62 figcnt = 1;
63 if Plot
64 hfig = figure(figcnt); figcnt = figcnt+1;
65
66 set(gcf, 'PaperUnits', 'inches', ...
67 'PaperPosition', [0 0 4 3], ...
68 'PaperSize', [4 3], ...
69 'Color', [1 1 1], ...
70 'Position',[1 1 650 500]);
71 plot((0:1/Fs:1/Fs*length(Output)-1/Fs).*1e9,Output, '-k', ...
72 'Linewidth',4, 'MarkerEdgeColor', 'k', ...
73 'MarkerFaceColor', 'w', 'MarkerSize', 8);
74 hold on
75 plot((0:2/Fs:2/Fs*length(Output1)-1/Fs).*1e9,Output1,'o', ...
76 'Linewidth',4, 'MarkerEdgeColor', [0 0 200/255], ...
77 'MarkerFaceColor', 'w', 'MarkerSize', 8);
78 plot((1/Fs:2/Fs:2/Fs*length(Output2)).*1e9,Output2,'o', ...
79 'Linewidth',4, 'MarkerEdgeColor', [200/255 0 0], ...
80 'MarkerFaceColor', 'w', 'MarkerSize', 8);

116
 81
82 set(gca,'fontsize', 18,'fontname','Arial');
83 set(gca, 'Box', 'on', 'Linewidth', 3);
84 xlabel('Time [ns]'); ylabel('[V]');
85 set(gca, 'XTick', [0:50:2ˆ10/Fs*1e9]); set(gca, 'YTick',...
86 [0:1:2ˆBits+1]);
87 axis([0 2ˆ10/Fs*1e9 0 2ˆBits+1]);
88 grid on;
89 h = legend('Input Sine','Data: Chan1','Data: Chan2', ...
90 'Location','NorthEast');
91 set(h, 'LineWidth', 2)
92 end
93
94 %% DS Modulation
95
96 % DC offset of DS Modualtor input
97 Offset = 0;
98
99 % Initializing feedback memory
100 Quant1a = zeros(1, length(Output)/2);
101 Quant1b = zeros(1, length(Output)/2);
102 Quant2a = zeros(1, length(Output)/2);
103 Quant2b = zeros(1, length(Output)/2);
104
105 % Initializing DS Outputs
106 DS Output1 = zeros(1, length(Output)/2);
107 DS Output2 = zeros(1, length(Output)/2);
108 % Initializing Sum/Diff Outputs
109 Sum1 = zeros(1, length(Output)/2);
110 Sum2 = zeros(1, length(Output)/2);
111
112 % Implementation of DS Modulation: 2nd Order HP
113 for x = 1:length(Output1)
114 % Output of Sum/Diff
115 Sum1(x) = Output1(x) - 2*Quant1a(x) - Quant1b(x) + Offset;
116 Sum2(x) = Output2(x) - 2*Quant2a(x) - Quant2b(x) + Offset;
117
118 % MSBs (Bits after truncation)
119 DS Output1(x) = fix(Output1(x) - 2*Quant1a(x) - Quant1b(x)...
120 + Offset);
121 DS Output2(x) = fix(Output2(x) - 2*Quant2a(x) - Quant2b(x)...
122 + Offset);
123
124 % Loading of feedback memory with Truncated LSBs
125 if x ~= length(Output1)-1
126 % Quant @ x = length(Output1) could be used
127 % for magnitude of wrap-around error
128 Quant1a(x+1) = Sum1(x) - DS Output1(x);
129 Quant1b(x+1) = Quant1a(x);
130 Quant2a(x+1) = Sum2(x) - DS Output2(x);
131 Quant2b(x+1) = Quant2a(x);

117
132 end
133 end
134
135 % Repeat Bits so that signals have proper phase
136 % alignment during addition
137 Output1(1:2:length(Output)) = DS Output1(1:end);
138 Output1(2:2:length(Output)) = DS Output1(1:end);
139 Output2(2:2:length(Output)) = DS Output2(1:end);
140 Output2(3:2:length(Output)) = DS Output2(1:end-1);
141 Output2(1) = DS Output2(end);
142
143 % If Per Cell is on, determine output of each DAC cell
144 if Per Cell
145 Output Bit1 = zeros(2ˆBits-1,length(Output1));
146 Output Bit2 = zeros(2ˆBits-1,length(Output2));
147
148 for x = 1:length(Output1)
149 if Output1(x) > 0
150 Output Bit1(1:Output1(x),x) = 1;
151 end
152 if Output2(x) > 0
153 Output Bit2(1:Output2(x),x) = 1;
154 end
155 end
156 end
157

158 % Check for Overflow

159 if max(Output1) > 2ˆBits-1 | | max(Output2) > 2ˆBits-1
160
161 disp('Error: Delta Sigma Overflow Occured - Output')
162 end
163 if min(Quant1a) < 0 | | min(Quant1b) < 0 ...
164 | | min(Quant2a) < 0 | | min(Quant2b) < 0
165 disp('Error: Delta Sigma Overflow Occured - Error Feedback')
166 end
167
168 % Addition of the two channels before jitter
169 DS Output = Output1 + Output2;
170
171 %% Plot DS Output
172
173 if Plot
174 hfig = figure(figcnt); figcnt = figcnt+1;
175 set(gcf, 'PaperUnits', 'inches', ...
176 'PaperPosition', [0 0 4 3], ...
177 'PaperSize', [4 3], ...
178 'Color', [1 1 1], ...
179 'Position',[1 1 650 500]);
180 plot((0:1/Fs:1/Fs*length(DS Output)-1/Fs).*1e9,DS Output,...
181 '-k', 'Linewidth',4, 'MarkerEdgeColor', 'k', ...
182 'MarkerFaceColor', 'w', 'MarkerSize', 8);

118
183 hold on
184 plot((0:2/Fs:2/Fs*length(Output1)-1/Fs).*1e9,Output1,'-', ...
185 'Color', [0 0 200/255],'Linewidth', 4);
186 plot((1/Fs:2/Fs:2/Fs*length(Output2)).*1e9,Output2,'-', ...
187 'Color', [200/255 0 0],'Linewidth', 4);
188
189 set(gca,'fontsize', 18,'fontname','Arial');
190 set(gca, 'Box', 'on', 'Linewidth', 3);
191 xlabel('Time [ns]'); ylabel('X \cdot I L S B [A]');
192 set(gca, 'XTick', [0:50:2ˆ10/Fs*1e9]);
193 set(gca, 'YTick', [0:2:2ˆ(Bits+1)-1]);
194 axis([0 2ˆ10/Fs*1e9 0 2ˆ(Bits+1)-1]);
195 grid on;
196 h = legend('Interleaved Output','Channel1 Output',...
197 'Channel2 Output', 'Location','NorthEast');
198 set(h, 'LineWidth', 2)
199 end
200
201 %% Plot Ideal DS Output: Frequency Domain
202

203 [psdestx1,Fxx1] = periodogram(Output1*2*R0*ILSB, ...

204 hanning(length(Output1)),length(Output1),Fs/1e9,'power');
205 %);
206 [psdestx2,Fxx2] = periodogram(Output2*2*R0*ILSB, ...
207 hanning(length(Output2)),length(Output2),Fs/1e9,'power');
208 %);
209 [psdestx,Fxx] = periodogram(DS Output*2*R0*ILSB, ...
210 hanning(length(DS Output)),length(DS Output),Fs/1e9,'power');
211 %);
212
213 if Plot
214 hfig = figure(figcnt); figcnt = figcnt+1;
215 set(gcf, 'PaperUnits', 'inches', ...
216 'PaperPosition', [0 0 4 3], ...
217 'PaperSize', [4 3], ...
218 'Color', [1 1 1], ...
219 'Position',[1 1 750 500]);
220 plot(Fxx,10*log10(psdestx), '-k', ...
221 'Linewidth',4, 'MarkerEdgeColor', 'k', ...
222 'MarkerFaceColor', 'w', 'MarkerSize', 8);
223 hold on
224 plot(Fxx1,10*log10(psdestx1),'-', ...
225 'Color', [0 0 200/255],'Linewidth', 4);
226 plot(Fxx2,10*log10(psdestx2),'-', ...
227 'Color', [200/255 0 0],'Linewidth', 4);
228
229 set(gca,'fontsize', 18,'fontname','Arial');
230 set(gca, 'Box', 'on', 'Linewidth', 3);
231 xlabel('Frequency [GHz]'); ylabel('Power [dBm]');
232 set(gca, 'XTick', [0:.25:max(Fxx)]); set(gca, 'YTick',...
233 [-150:25:50]);

119
234 axis([0 max(Fxx) -125 25]);
235 grid on;
236 h = legend('Interleaved Output','Channel1 Output',...
237 'Channel2 Output', 'Location','NorthEast');
238 set(h, 'LineWidth', 2)
239 end
240
241 %% Calculate Ideal SNR
242
243 % Lower Frequency Limit
244 F L = Fs/4 - Fs/4 * SNR BW/2;
245 % Upper Frequency Limit
246 F U = Fs/4 + Fs/4 * SNR BW/2;
247 % FFT bin for low end
248 Bin L = floor(F L * Num Samples / Fs) + 1;
249 % FFT bin for high end
250 Bin U = ceil(F U * Num Samples / Fs) + 1;
251 % Total Power in SNR BW
252 BW Pwr Ideal = sum(psdestx(Bin L:Bin U));
253 % Signal Power in SNR BW
254 Signal Pwr Ideal = sum(psdestx(Bin:Bin+2));
255 % Noise Power in SNR BW
256 Noise Pwr Ideal = BW Pwr Ideal - Signal Pwr Ideal;
257 % SNR
258 SNR Ideal = 10*log10(Signal Pwr Ideal/Noise Pwr Ideal);
259

260 if Plot
261 % Plot Markers showing limit of SNR BW
262 plot(Fxx(Bin U),10*log10(psdestx(Bin U)), 'o', ...
263 'Linewidth',4, 'MarkerEdgeColor', [200/255 0 0], ...
264 'MarkerFaceColor', 'w', 'MarkerSize', 8);
265 plot(Fxx(Bin L),10*log10(psdestx(Bin L)), 'o', ...
266 'Linewidth',4, 'MarkerEdgeColor', [200/255 0 0], ...
267 'MarkerFaceColor', 'w', 'MarkerSize', 8);
268 end
269
270 clear psdestx psdestx2 Fxx2 psdestx1 Fxx1 F L F U
271 clear BW Pwr Ideal Signal Pwr Ideal Noise Pwr Ideal
272
273 %% Oversampling
274
275 % Initializing Oversampled Outputs
276 OS DS Output = zeros(1,length(DS Output)*OSR);
277 OS DS Output1 = zeros(1,length(Output1)*OSR);
278 OS DS Output2 = zeros(1,length(Output2)*OSR);
279
280 % Vectors containing the normally distributed jitter
281 % Rounded to integers for use as indices
282 Jitter = round(normrnd(0, Sigma*(Fs*OSR),1,length(DS Output)));
283 Jitter1 = round(normrnd(0, Sigma*(Fs*OSR),1,length(Output1)));
284 Jitter2 = round(normrnd(0, Sigma*(Fs*OSR),1,length(Output2)));

120
285
286 % Prevent negative index
287 Jitter(1) = 0;
288 Jitter1(1) = 0;
289 Jitter2(1) = 0;
290
291 % For Individual Cell Analysis
292 if Per Cell
293 OS DS Output Bit1 = zeros(2ˆBits-1,length(Output Bit1)*OSR);
294 OS DS Output Bit2 = zeros(2ˆBits-1,length(Output Bit2)*OSR);
295
296 Jitter Bit1 = round(normrnd(0, Sigma*(Fs*OSR),2ˆBits-1, ...
297 length(Output Bit1)));
298 Jitter Bit2 = round(normrnd(0, Sigma*(Fs*OSR),2ˆBits-1, ...
299 length(Output Bit2)));
300
301 % Add in timing error
302 Jitter Bit1 = bsxfun(@plus,Jitter Bit1, ...
303 Cell Systematic Timing Error1');
304 Jitter Bit2 = bsxfun(@plus,Jitter Bit2, ...
305 Cell Systematic Timing Error2');
306
307 Jitter Bit1(:,1) = 0;
308 Jitter Bit2(:,1) = 0;
309 end
310

311 % Add jitter to data transitions

312 for x = 2:length(DS Output)
313
314 if x < length(DS Output)
315 OS DS Output(1+OSR*(x-2)+Jitter(x-1):1+OSR*(x-1)...
316 +Jitter(x)) = DS Output(x);
317 OS DS Output1(1+OSR*(x-2)+Jitter1(x-1):1+OSR*(x-1)...
318 +Jitter1(x)) = Output1(x);
319 OS DS Output2(1+OSR*(x-2)+Jitter2(x-1):1+OSR*(x-1)...
320 +Jitter2(x)) = Output2(x);
321
322 % If Per Cell is on, populate Jittery Bit Cell data
323 if Per Cell
324 for y = 1:2ˆBits-1
325
326 OS DS Output Bit1(y,1+OSR*(x-2)+...
327 Jitter Bit1(y,x-1):1+OSR*(x-1)+...
328 Jitter Bit1(y,x)) = Output Bit1(y,x);
329
330 OS DS Output Bit2(y,1+OSR*(x-2)+...
331 Jitter Bit2(y,x-1):1+OSR*(x-1)+...
332 Jitter Bit2(y,x)) = Output Bit2(y,x);
333 end
334 end
335

121
336 % Last Sample must have Jitter of 0 to keep array length equal
337 elseif x == length(DS Output)
338 OS DS Output(1+OSR*(x-2)+Jitter(x-1):1+OSR*(x-1)) = ...
339 DS Output(x);
340 OS DS Output1(1+OSR*(x-2)+Jitter1(x-1):1+OSR*(x-1)) = ...
341 Output1(x);
342 OS DS Output2(1+OSR*(x-2)+Jitter2(x-1):1+OSR*(x-1)) = ...
343 Output2(x);
344
345 % Clear variables for memory purposes
346 clear Jitter1 Jitter2 Output2 Output1 DS Output Output
347
348 % If Per Cell is on, finish Bit Cell array
349 if Per Cell
350 for y = 1:2ˆBits-1
351
352 OS DS Output Bit1(y,1+OSR*(x-2)+...
353 Jitter Bit1(y,x-1):1+OSR*(x-1))...
354 = Output Bit1(x);
355 OS DS Output Bit2(y,1+OSR*(x-2)+...
356 Jitter Bit2(y,x-1):1+OSR*(x-1))...
357 = Output Bit2(x);
358 end
359 % Clear variables for memory purposes
360 clear Jitter Bit1 Jitter Bit2 Output Bit2 Output Bit1
361 end
362 end
363 end
364
365 % Multiply in Per Cell Amplitude error
366 if Per Cell
367

368 OS DS Output Bit1 = bsxfun(@times,OS DS Output Bit1, ...

369 Cell Systematic Amplitude Error1');
370 OS DS Output Bit2 = bsxfun(@times,OS DS Output Bit2, ...
371 Cell Systematic Amplitude Error2');
372 end
373

374 %% Plot Histogram of Jitter

375
376 hfig = figure(figcnt); figcnt = figcnt+1;
377 set(gcf, 'PaperUnits', 'inches', ...
378 'PaperPosition', [0 0 4 3], ...
379 'PaperSize', [4 3], ...
380 'Color', [1 1 1], ...
381 'Position',[1 1 750 500]);
382 % Array Representing Histogram Bars to use
383 Bars = 1/(Fs.*OSR).*(-100:100).*1e12;
384 hist(Jitter./(Fs.*OSR).*1e12, Bars)
385

386 set(gca,'fontsize', 18,'fontname','Arial');

122
387 set(gca, 'Box', 'on', 'Linewidth', 3);
388 xlabel('Data Jitter [ps]'); ylabel('Number');
389 %set(gca, 'XTick', [0:.25:max(Fxx)]);
390 %set(gca, 'YTick', [-150:25:50]);
391 %axis([0 max(Fxx) -125 25]);
392 grid on;
393 h = legend('Jitter Dist.', 'Location','NorthEast');
394 set(h, 'LineWidth', 2)
395
396 clear Jitter
397
398 %% Plot DS Jitter Output: Frequency Domain
399
400 % Frequency Domain of Jittery Outputs
401 [OS psdestx1,OS Fxx1] = periodogram(OS DS Output1 *2*R0*ILSB, ...
402 hanning(length(OS DS Output1)),length(OS DS Output1), ...
403 OSR*Fs/1e9,'power');
404 %);
405 [OS psdestx2,OS Fxx2] = periodogram(OS DS Output2 *2*R0*ILSB, ...
406 hanning(length(OS DS Output2)),length(OS DS Output2), ...
407 OSR*Fs/1e9,'power');
408 %);
409 [OS psdestx,OS Fxx] = periodogram(OS DS Output *2*R0*ILSB, ...
410 hanning(length(OS DS Output)),length(OS DS Output), ...
411 OSR*Fs/1e9,'power');
412 %);
413 [OS psdestx add,OS Fxx add] = ...
414 periodogram(OS DS Output1. *2.*R0.*ILSB + ...
415 OS DS Output2. *2.*R0.*ILSB,...
416 hanning(length(OS DS Output1)), ...
417 length(OS DS Output),OSR*Fs/1e9,'power');
418 %);
419
420 if Per Cell
421 OS DS Output Bit = zeros(1,length(OS DS Output Bit1(1,:)));
422
423 % Add all of the individual bit cells together
424 for x = 1:2ˆBits-1
425 OS DS Output Bit = OS DS Output Bit1(x,:) +...
426 OS DS Output Bit2(x,:)+ ...
427 OS DS Output Bit;
428 end
429
430 [OS psdestx Bit,OS Fxx Bit] = ...
431 periodogram(OS DS Output Bit. *2.*R0.*ILSB,...
432 hanning(length(OS DS Output1)), ...
433 length(OS DS Output),OSR*Fs/1e9,'power');
434 %);
435 end
436

437 RBW = (OS Fxx(2)-OS Fxx(1)).*1e9;

123
438
439 if Plot
440 hfig = figure(figcnt); figcnt = figcnt+1;
441 set(gcf, 'PaperUnits', 'inches', ...
442 'PaperPosition', [0 0 4 3], ...
443 'PaperSize', [4 3], ...
444 'Color', [1 1 1], ...
445 'Position',[1 1 750 500]);
446 hold off
447 plot(OS Fxx,10*log10(OS psdestx), '-k', ...
448 'Linewidth',4, 'MarkerEdgeColor', 'k', ...
449 'MarkerFaceColor', 'w', 'MarkerSize', 8);
450 hold on
451 plot(OS Fxx1,10*log10(OS psdestx1),'-', ...
452 'Color', [0 0 200/255],'Linewidth', 4);
453 plot(OS Fxx2,10*log10(OS psdestx2),'-', ...
454 'Color', [200/255 0 0],'Linewidth', 4);
455 plot(OS Fxx add,10*log10(OS psdestx add), '-',...
456 'Color', [0 200/255 0], ...
457 'Linewidth',4, 'MarkerEdgeColor', 'k', ...
458 'MarkerFaceColor', 'w', 'MarkerSize', 8);
459
460 if Per Cell
461
462 plot(OS Fxx Bit,10*log10(OS psdestx Bit), '-',...
463 'Color', [1 200/255 0], ...
464 'Linewidth',4, 'MarkerEdgeColor', 'k', ...
465 'MarkerFaceColor', 'w', 'MarkerSize', 8);
466 end
467
468 set(gca,'fontsize', 18,'fontname','Arial');
469 set(gca, 'Box', 'on', 'Linewidth', 3);
470 xlabel('Frequency [GHz]'); ylabel('Power [dBm]');
471 set(gca, 'XTick', [0:.25:max(Fxx)]);
472 set(gca, 'YTick', [-150:25:50]);
473 axis([0 max(Fxx) -125 25]);
474 grid on;
475 h = legend('Interleaved Output: Top Jitter',...
476 'Channel1 Output', 'Channel2 Output', ...
477 'Interleaved Output: 2 Channel Jitter', ...
478 'Per Bit Jitter','Location','NorthEast');
479 set(h, 'LineWidth', 2)
480 end
481
482 %% SNR Calculations
483 % Total Power in SNR BW
484 BW Pwr AllJitter = sum(OS psdestx(Bin L:Bin U));
485 BW Pwr DACJitter = sum(OS psdestx add(Bin L:Bin U));
486
487 % Signal Power in SNR BW
488 Signal Pwr AllJitter = sum(OS psdestx(Bin:Bin+2));

124
489 Signal Pwr DACJitter = sum(OS psdestx add(Bin:Bin+2));
490

491 % Noise Power in SNR BW

492 Noise Pwr AllJitter = BW Pwr AllJitter - Signal Pwr AllJitter;
493 Noise Pwr DACJitter = BW Pwr DACJitter - Signal Pwr DACJitter;
494
495 % SNR
496 SNR AllJitter = 10*log10(Signal Pwr AllJitter/Noise Pwr AllJitter);
497 SNR DACJitter = 10*log10(Signal Pwr DACJitter/Noise Pwr DACJitter);
498
499 % If Per Cell is ON, Calc SNR
500 if Per Cell
501
502 BW Pwr CellJitter = sum(OS psdestx Bit(Bin L:Bin U));
503 Signal Pwr CellJitter = sum(OS psdestx Bit(Bin:Bin+2));
504 Noise Pwr CellJitter = BW Pwr CellJitter - ...
505 Signal Pwr CellJitter;
506 SNR CellJitter = 10*log10(Signal Pwr CellJitter/...
507 Noise Pwr CellJitter);
508 else
509
510 SNR CellJitter = 0;
511
512 end
513
514 clear OS Fxx OS Fxx2 OS Fxx1 OS Fxx add Fxx
515 clear OS psdestx add OS psdestx Bit OS psdestx2 OS psdestx1
516
517 % Clear variables for memory
518 if Per Cell
519 clear OS Fxx Bit OS psdestx Bit
520 end
521
522 %% Output Simulation Data
523
524 disp(' ');
525 disp('--- Run Data ------');
526 disp(['Eff. Sample Rate: ' num2str(Fs/1e9) ' GHz']);
527 disp(['Single DAC Rate: ' num2str(Fs/2/1e9) ' GHz']);
528 disp(['Num. of Samples: ' num2str(Num Samples)]);
529 disp(['Jitter OSR: ' num2str(OSR)]);
530 disp(['DS Resolution: ' num2str(Resolution)]);
531 disp(['DAC Resolution: ' num2str(Bits)]);
532 disp(['Output Bin: ' num2str(Bin)]);
533 disp(['Signal Amplitude: ' num2str(Signal Amplitude)]);
534
535 if Per Cell == 1
536 disp('Per Cell Jitter: On');
537 elseif Per Cell == 0
538 disp('Per Cell Jitter: Off');
539 else

125
540 disp('Per Cell Jitter: ?');
541 end
542
543 disp(' ');
544 disp('------ SNR --------');
545
546 if Bin < Bin L+2 | | Bin > Bin U-2
547 disp('Signal is not within the SNR BW')
548 else
549 disp(['SNR Bandwidth: ' num2str(Fs/4 * SNR BW/1e9) ' GHz']);
550 disp(['Jitter Sigma: ' num2str(Sigma*1e12) ' ps']);
551 disp(['Ideal SNR: ' num2str(SNR Ideal) ' dB']);
552 disp(['Sys Jitter SNR: ' num2str(SNR AllJitter) ' dB']);
553 disp(['DAC Jitter SNR: ' num2str(SNR DACJitter) ' dB']);
554
555 if Per Cell
556 disp(['Cell Jitter SNR: ' num2str(SNR CellJitter) ' dB']);
557
558 end
559 disp(' ');
560 disp(' ');
561 end

126
 Appendix C: Testing Methodology - Rev. 2

The following appendix gives an overview of the testing of the final ∆Σ DAC

revision, highlighting the setup and a few of the tests performed on the proposed

design.

C.1 Test Equipment

The DAC testing, again pictured in Fig. C.1, is accomplished with the following

equipment:

ˆ A VC7215 Virtex 7 Evaluation Board providing high-speed data input via four-

teen LVDS channels

ˆ A signal generator providing the FPGA clock reference (-10 dBm)

ˆ A second signal generator for the external (x2) DAC clock. Due to high fre-

quency attenuation, the clock input power must scale with frequency.

ˆ Local computer for FPGA control and programming

ˆ SPI register control enabled by a Spartan 6 FPGA on an Opal Kelly board.

ˆ High frequency, wide-band balun for (optional) differential measurement

ˆ PXA Signal Analyzer for spectrum measurement

ˆ DC Power supplies

127
 Spectrum Analyzer

FPGA Clock
Input

2x Clock
Source

VC7215 5310A PPL

Virtex 7 Balun
SPI
Control Flip-Chip ΔΣ DAC PCB

Figure C.1: Test setup of the interleaved ∆Σ DAC.

C.2 Performance and Verification Tests

DC Testing

Board and chip integrity can be ensured with a DC test. By connecting the

power supplies to the voltage header, shown in Fig. C.2, the board connectivity

can be validated by comparing the current draw to the expected values given in

Table C.1. Due to clock buffering, the digital current draw scales with clock frequency

and requires an increased digital supply to overcome on-board voltage droop due to

the ohmic loss of the power cables.

Data and Clock Testing

On-chip clock functionality can be verified by bringing a divided down clock signal

back off-chip. The divide-by ratio is control by the CLK CTL1 register through the SPI

interface and can be observed on the differential SMA outputs on the south of the

128
 DAC Output

Bias-T

DAC1 LVDS Input

DAC0 LVDS Input

Loopback Loopback

Chip
Current
Bias
SPI Header

Div. Clock Voltage

Out Header
Clock In

Figure C.2: Revision 2 test board on which the interleaved DAC is mounted.

Table C.1: Nominal Board Voltages with Range

Supply Nominal (V ) Range (V ) Current (mA) Description

V1P5 1.5 1.4 - 1.6 300 - 600 Digital Supply
V1P52 1.5 1.4 - 1.6 ∼ 50 Clean Digital Supply
VCLK 2.3 2.1 - 2.5 ∼ 140 CML Clock Supply
VDDA 2.0 1.8 - 2.1 ∼ 50 DAC Driver Supply
CBIAS 2.8 2.6 - 2.9 < 10 DAC Cascode Bias
VDAC 3.3 3.2 - 3.5 ∼ 60 DAC Supply
LVDSA 1.8 1.7 - 2.1 ∼ 20 LVDS Analog Supply
LVDSD 1.1 0.9 - 1.5 < 10 LVDS Digital Supply

board. Once the on-chip clock is functional, the chip can receiver LVDS data inputs

(which should be 100 - 200 mV in amplitude). The data inputs can be routed off-chip

one-at-a-time using the LOOPBACKx registers to control channel selection with power

jumpers in-place to enable the on-chip LVDS transmitters. The data for one channel

can be viewed on the vertical SMAs. This is critical for confirming data latching and

proper alignment before the integrated DSM (Fig. C.3).

129
 Figure C.3: Functional diagram of the clock and loopback testing.

Calibration

Bypassing the on-chip DSM, data can be sent directly to the DAC by setting the

DS CTL register. This is useful for calibration since each unary DAC cell can be inde-

pendently toggled and its output power compared to a reference. The current of each

cell can then be adjusted such that each DAC cell has the same magnitude. This is

accomplished by setting CAL DAC DATA SELx for manual input and then adjusting the

currents via CAL DAC DATAx S. Likewise the timing of each cell can be adjusted by set-

ting CAL TADJ DATA SELx to manual and then tuning through the CAL TADJ DATAx S

registers. To test for intrinsic accuracy, the calibration DACs can be turned off, but

calibration is aided with a mid-level starting value.

General timing between the parallel DACs can be altered with the individual tim-

ing adjustment listed above. In addition, the timing between channels can also be

control with the CLK CTLx and CLK ALIGN registers, demonstrating the dependence

130
of SIRR on inter-channel timing. Since this inter-channel timing is controlled with

switched varactors, small adjustments to the clock voltage supply also tune the tim-

ing between channels, allowing the two DACs to be more precisely aligned. While

enabling fine tuning, this feature adds jitter to the DAC design and is to be removed

in subsequent revisions. The diagram for this testing is given in Fig. C.4.

Figure C.4: Functional diagram of the DSM by-pass testing.

DSM By-pass Testing

After calibration, pre-computed ∆Σ modulated data can be passed directly to the

DAC using the same configuration as that of calibration. This testing allows for SIRR,

SFDR, IM3, and ACLR performance extraction without directly passing through

the on-chip DSM, greatly increasing testing efficiency. Performance before and after

calibration can be shown in addition to single versus interleaved DAC operation.

131
DSM Testing

Once the DAC operation has been verified, the DSM can be tested. This requires

two 7 channel LVDS inputs consisting of doubled-data-rate sine wave samples. The

sample bits must be pre-aligned off-chip to account for the pipelined architecture.

This can be confirmed on-chip using the previously mentioned loopback testing to

directly observed the data. To adjust data alignment, the DATA ARR register can be

used to properly position the MSB and LSB of each channel. During DSM operation,

static offsets can be added to the incoming samples using the DS OFFSETx registers.

This functionality is to ensure the DSM bit cells do not experience overflow. The

testing is depicted by the digram given in Fig. C.5.

Figure C.5: Functional diagram of the full DSM and DAC testing.

132
 Appendix D: SPI Register Definitions

D.1 Register Map

Table D.1: Register Map for DAC Serial Interface

Address Name R/W Description
1
0x0000 - 0x0001 DAC CTLx R/W DAC calibration control bits
0x0004 DAC STATUS R DAC calibration status bits
0x0008 - 0x0009 LOOPBACKx1 R/W Data loopback test: channel select
0x0010 - 0x001D DATA RX ADJx1 R/W Data RX phase adjustment
0x0040 CAL CUT L R Generated cell-under-test for cal.
0x0050 CAL LO ADJ R/W Phase adjust for calibration LO
0x0051 CAL LO DATA L R Generated data pattern for calibration LO
0x0052 CAL LO DATA S R/W Manual data pattern for calibration LO
0x0058 CAL MEAS DELAY R/W Delay before taking measurement
0x0060 CAL OS L R Generated measurement offset
0x0061 CAL GE L R Generated gain error measurement
0x0064 CAL TARGET A R/W Amplitude calibration target
0x0065 CAL TARGET T R/W Timing calibration target
0x0070 - 0x007D CAL I RESx1 R Result of current measurement
0x00C0 CAL DATA SELx1 R/W Calibration data pattern select
0x00C8 CAL DAC DATA SELx1 R/W Cal. DAC data (Manual Over-ride)
0x00CC CAL TADJ DATA SELx1 R/W Cal. timing data (Manual Over-ride)
0x00D0 - 0x00DF CAL DATAx L1 R Generated data patterns for cal.
0x0100 - 0x010F CAL DAC DATAx L1 R Generated data for each CALDAC
0x0130 - 0x013F CAL TADJ DATAx L1 R Generated timing adjustments
0x0170 - 0x017D CAL T RESx1 R Result of timing measurement
0x0240 CAL CUT S R/W Manual cell-under-test for cal.
0x0260 CAL OS S R/W Manual measurement offset
0x0261 CAL GE S R/W Manual gain error adjust
0x02D0 - 0x02DF CAL DATAx S1 R/W Manual data patterns for cal.
0x0300 - 0x030F CAL DAC DATAx S1 R/W Manual data for each CALDAC
0x0330 - 0x033F CAL TADJ DATAx S1 R/W Manual data for timing adj.
0x0400 DS CTL R/W DS modulator control bits
0x0401 - 0x0402 CLK CTLx1 R/W Clock phase control bits
0x0410 - 0x0415 DS OFFSETx1 R/W DS modulator DC offset
0x0440 CLK ALIGN R/W CML and CMOS clock alignment
0x0450 DATA ARR R/W Interleaved data arrangement

1
For registers listed with multiple addresses, the register name is specified by x = 0 . . . N − 1,
where N is the number of 16-bit addresses

133
D.2 Register Definitions
DAC CTLx Register

The DAC CTLx registers contain various bits to set the operation mode of the DAC.

15 14 13 12 11 10 9 8
NS SEL Reserved MANCUT LOSEL

7 6 5 4 3 2 1 0
CSSEL CDEN CLKDIV CALMIX CALST MEAS CALEN

Figure D.1: DAC CTL0 Register Fields

Table D.2: DAC CTL0 Register Description

Bit Field Reset Description
15 - 12 NS SEL 0x0 Number of calibration samples per measurement
(NS = 216+N SEL )
11 - 10 Reserved 0x0 Reserved
9 MANCUT 0x0 Enable manual overried for CUT
8 LOSEL 0x0 Calibration LO data select. Selects between manual
or generated LO data patterns
7 CSSEL 0x0 Cell select override. Allows for manually overriding
the cell select in order to load in calibration data.
6 CDEN 0x0 Calibration data enable. Bypasses input data and
drives the DAC with calibration data.
5-4 CLKDIV 0x0 Clock select
for calibration circuitry*
fDAT A
fCAL = 2(5+CLKDIV )
3 CALMIX 0x0 Enable the calibration mixer.
0b = Mixer enabled
1b = Mixer disabled
2 CALST 0x0 Start the full calibration process when set from 0b
to 1b. Automatically set to 0b when calibration is
finished.
1 MEAS 0x0 Start a single calibration measurement when set from
0b to 1b.
0 CALEN 0x0 Enable calibration circuitry
1b = Calibration circuitry enabled
0b = Calibration circuitry disabled
* Divided clock is coupling to the output; changing divide reduces coupling

134
 15 14 13 12 11 10 9 8
Reserved

7 6 5 4 3 2 1 0
Reserved

Figure D.2: DAC CTL1 Register Fields

Table D.3: DAC CTL1 Register Description

Bit Field Reset Description
15 - 0 Reserved 0x0 Reserved

DAC STATUS Register

The DAC STATUS register is a read-only register that contains status bits pertaining

to the current state of the calibration.

15 14 13 12 11 10 9 8
N/A

7 6 5 4 3 2 1 0
N/A BUSY

Figure D.3: DAC STATUS Register Fields

135
 Table D.4: DAC STATUS Register Description
Bit Field Reset Description
15 - 1 Reserved 0x0 Reserved
0 BUSY 0x0 Status of DAC calibration circuitry. Do not write
to any registers if a calibration or measurement is in
progress.
0b = Idle
1b = Calibration in progress

LOOPBACKx Register

The LOOPBACKx registers select the data channels for loopback.

15 14 13 12 11 10 9 8
N/A

7 6 5 4 3 2 1 0
N/A LBSEL

Figure D.4: LOOPBACKx Register Fields

Table D.5: LOOPBACKx Register Description

Bit Field Reset Description
15 - 4 Reserved 0x0 Reserved
3-0 LBSEL 0x0 Select the data channel for loopback

DATA RX ADJx Register

The DATA RX ADJx registers are a group of registers that control the phases of the

incoming data to ensure that each data channel is properly aligned with the data

clock.

136
 15 14 13 12 11 10 9 8
N/A

7 6 5 4 3 2 1 0
N/A ADJ

Figure D.5: DATA RX ADJx Register Fields

Table D.6: DATA RX ADJx Register Description

Bit Field Reset Description
15 - 4 Reserved 0x0 Reserved
3 - 0 ADJ 0x8 RX phase adjustment for data bit x

CAL CUT L Register

The CAL CUT L register holds the cell-under-test as generated by the calibration

logic.
15 14 13 12 11 10 9 8
N/A

7 6 5 4 3 2 1 0
N/A Reserved CUTIDX

Figure D.6: CAL CUT L Register Fields

Table D.7: CAL CUT L Register Description

Bit Field Reset Description
15 - 4 Reserved 0x0 Reserved
3 - 0 CUTIDX 0x0 Index for the CUT

137
CAL CUT S Register

The CAL CUT S register allows for manually specify a cell-under-test for performing

a calibration measurement. Setting the corresponding cell index in this register allows

for manually performing a single calibration on any of the DAC cells without having

to run a full calibration.

15 14 13 12 11 10 9 8
N/A

7 6 5 4 3 2 1 0
N/A Reserved CUTIDX

Figure D.7: CAL CUT S Register Fields

Table D.8: CAL CUT S Register Description

Bit Field Reset Description
15 - 4 Reserved 0x0 Reserved
3 - 0 CUTIDX 0x0 Index for the CUT

CAL LO ADJ Register

The CAL LO ADJ register adjusts the phase of the LO for the calibration mixer and

is used to align the LO with the phase of the cell-under-test.

15 14 13 12 11 10 9 8
N/A

7 6 5 4 3 2 1 0
N/A ADJ

Figure D.8: CAL LO ADJ Register Fields

138
 Table D.9: CAL LO ADJ Register Description
Bit Field Reset Description
15 - 4 Reserved 0x0 Reserved
3 - 0 ADJ 0x8 Phase adjustment for the calibration mixer LO

CAL LO DATA L Register

The CAL LO DATA L register holds a data pattern that is used to generate the LO

for the calibration mixer.

15 14 13 12 11 10 9 8
DATAL

7 6 5 4 3 2 1 0
DATAL

Figure D.9: CAL LO DATA L Register Fields

Table D.10: CAL LO DATA L Register Description

Bit Field Reset Description
15 - 0 DATAL 0x0 Generated data pattern for cell x

CAL LO DATA S Register

The CAL LO DATA S register is used to manually set a data pattern used to generate

the calibration mixer LO.

15 14 13 12 11 10 9 8
DATAS

7 6 5 4 3 2 1 0
DATAS

Figure D.10: CAL LO DATA S Register Fields

139
 Table D.11: CAL LO DATA S Register Description
Bit Field Reset Description
15 - 0 DATAS 0x0 Manual data pattern for cell x

CAL MEAS DELAY Register

The CAL MEAS DELAY register sets the number of calibration cycles to wait before

a measurement is taken. This allows time for the ∆Σ modulator to settle before

measuring the output of the DAC.

15 14 13 12 11 10 9 8
CALDLY

7 6 5 4 3 2 1 0
CALDLY

Figure D.11: CAL MEAS DELAY Register Fields

Table D.12: CAL MEAS DELAY Register Description

Bit Field Reset Description
15 - 0 CALDLY 0x00FF Number of delay cycles

CAL OS L Register

The CAL OS L register holds the measured offset of the calibration measurement

circuitry that is then subtracted from the measurement results.

140
 15 14 13 12 11 10 9 8
N/A CALOSL

7 6 5 4 3 2 1 0
CALOSL

Figure D.12: CAL OS L Register Fields

Table D.13: CAL OS L Register Description

Bit Field Reset Description
15 - 14 Reserved 0x0 Reserved
13 - 0 CALOSL 0x0 Measured offset

CAL OS S Register

The CAL OS S register holds a manual offset that can be optionally subtracted

from the calibration measurement.

15 14 13 12 11 10 9 8
N/A CALOSS

7 6 5 4 3 2 1 0
CALOSS

Figure D.13: CAL OS S Register Fields

Table D.14: CAL OS S Register Description

Bit Field Reset Description
15-14 Reserved 0x0 Reserved
13 - 0 CALOSS 0x0 Manual offset

141
CAL GE L Register

The CAL GE L register holds the measured gain error of the calibration measure-

ment circuitry that is then de-embedded from the calibration measurement.

15 14 13 12 11 10 9 8
N/A CALGEL

7 6 5 4 3 2 1 0
CALGEL

Figure D.14: CAL GE L Register Fields

Table D.15: CAL GE L Register Description

Bit Field Reset Description
15 - 14 Reserved 0x0 Reserved
13 - 0 CALGEL 0x0 Measured gain error

CAL GE S Register

The CAL GE S register holds a manual gain error compensation value that can be

optionally de-embedded from the calibration measurement.

15 14 13 12 11 10 9 8
N/A CALGES

7 6 5 4 3 2 1 0
CALGES

Figure D.15: CAL GE S Register Fields

Table D.16: CAL GE S Register Description

Bit Field Reset Description
15-14 Reserved 0x0 Reserved
13 - 0 CALGES 0x0 Manual gain error adjustment

142
CAL TARGET A Register

The CAL TARGET A register sets the target amplitude to which each DAC current

cell is calibrated.
15 14 13 12 11 10 9 8
N/A ATGT

7 6 5 4 3 2 1 0
ATGT

Figure D.16: CAL TARGET A Register Fields

Table D.17: CAL TARGET A Register Description

Bit Field Reset Description
15 - 14 Reserved 0x0 Reserved
13 - 0 ATGT 0x2000 Target calibration amplitude

CAL TARGET T Register

The CAL TARGET T register sets the target timing offset to which all cells are cali-

brated.
15 14 13 12 11 10 9 8
N/A TTGT

7 6 5 4 3 2 1 0
TTGT

Figure D.17: CAL TARGET T Register Fields

Table D.18: CAL TARGET T Register Description

Bit Field Reset Description
15 - 14 Reserved 0x0 Reserved
13 - 0 TTGT 0x0 Target calibration timing

143
CAL I RESx Register

The CAL I RESx registers are a group of read-only registers that contain the results

of the calibration current measurement for each cell.

15 14 13 12 11 10 9 8
N/A IRES

7 6 5 4 3 2 1 0
IRES

Figure D.18: CAL I RESx Register Fields

Table D.19: CAL I RESx Register Description

Bit Field Reset Description
15 - 14 Reserved 0x0 Reserved
13 - 0 IRES 0x0 Current measurement result for cell x.

CAL T RESx Register

The CAL T RESx registers are a group of read-only registers that contain the results

of the calibration timing measurement for each cell.

15 14 13 12 11 10 9 8
N/A TRES

7 6 5 4 3 2 1 0
TRES

Figure D.19: CAL T RESx Register Fields

Table D.20: CAL T RESx Register Description

Bit Field Reset Description
15 - 14 Reserved 0x0 Reserved
13 - 0 TRES 0x0 Timing measurement result for cell x.

144
CAL DATA SELx Register

The CAL DATA SELx registers are used to select between the CALDAC data that

are generated by the calibration logic and the data that are manually specified through

the SPI.

15 14 13 12 11 10 9 8
DS15 DS14 DS13 DS12 DS11 DS10 DS9 DS8

7 6 5 4 3 2 1 0
DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS0

Figure D.20: CAL DATA SEL0 Register Fields

Table D.21: CAL DATA SEL0 Register Description

Bit Field Reset Description
15 - 0 DSn 0x0 Data select for cell n
0b = Use pattern generated by calibration logic
1b = Use pattern specified by SPI

CAL DAC DATA SELx Register

The CAL DAC DATA SELx registers are used to select between the CALDAC data

that are generated by the calibration logic and data that are manually specified

through the SPI.

145
 15 14 13 12 11 10 9 8
DS15 DS14 DS13 DS12 DS11 DS10 DS9 DS8

7 6 5 4 3 2 1 0
DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS0

Figure D.21: CAL DAC DATA SEL0 Register Fields

Table D.22: CAL DAC DATA SEL0 Register Description

Bit Field Reset Description
15 - 0 DSn 0x0 Data select for cell n
0b = Use pattern generated by calibration logic
1b = Use pattern specified by SPI

CAL TADJ DATA SELx Register

The CAL TADJ DATA SELx registers are used to select between timing adjustments

that are generated by the calibration logic and patterns that are manually specified

through the SPI.

15 14 13 12 11 10 9 8
DS15 DS14 DS13 DS12 DS11 DS10 DS9 DS8

7 6 5 4 3 2 1 0
DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS0

Figure D.22: CAL TADJ DATA SEL0 Register Fields

146
 Table D.23: CAL TADJ DATA SEL0 Register Description
Bit Field Reset Description
15 - 0 DSn 0x0 Data select for cell n
0b = Use pattern generated by calibration logic
1b = Use pattern specified by SPI

CAL DATAx L Register

The CAL DATAx L registers are a group of registers that hold a data pattern for

each cell that is generated by the calibration logic. During a calibration measurement,

each DAC cell will cycle through its corresponding data pattern.
15 14 13 12 11 10 9 8
DATAL

7 6 5 4 3 2 1 0
DATAL

Figure D.23: CAL DATAx L Register Fields

Table D.24: CAL DATAx L Register Description

Bit Field Reset Description
15 - 0 DATAL 0x0 Generated data pattern for cell x

CAL DATAx S Register

The CAL DATAx S registers are a group of registers that are used to manually set

a data pattern for each cell. During a calibration measurement, each DAC cell will

cycle through its corresponding data pattern.

147
 15 14 13 12 11 10 9 8
DATAS

7 6 5 4 3 2 1 0
DATAS

Figure D.24: CAL DATAx S Register Fields

Table D.25: CAL DATAx S Register Description

Bit Field Reset Description
15 - 0 DATAS 0x0 Manual data pattern for cell x

CAL DAC DATAx L Register

The CAL DAC DATAx L registers are a group of registers contain the automatically

generated calibration DAC data that sets the calibration current for each cell via the

calibration DACs.
15 14 13 12 11 10 9 8
N/A DATA

7 6 5 4 3 2 1 0
DATA

Figure D.25: CAL DAC DATAx L Register Fields

Table D.26: CAL DAC DATAx L Register Description

Bit Field Reset Description
15 - 7 Reserved 0x0 Reserved
8 - 0 DATA 0x8 Data for the calibration DAC for cell x

148
CAL DAC DATAx S Register

The CAL DAC DATAx S registers are a group of registers contain the manually spec-

ified calibration DAC data that sets the calibration current for each cell via the

calibration DACs.
15 14 13 12 11 10 9 8
N/A DATA

7 6 5 4 3 2 1 0
DATA

Figure D.26: CAL DAC DATAx S Register Fields

Table D.27: CAL DAC DATAx S Register Description

Bit Field Reset Description
15 - 7 Reserved 0x0 Reserved
8 - 0 DATA 0x8 Data for the calibration DAC for cell x

CAL TADJ DATAx L Register

The CAL TADJ DATAx L registers are a group of registers that contain the auto-

matically generated bits that set the timing adjustment for each cell via the local RZ

drivers.
15 14 13 12 11 10 9 8
N/A

7 6 5 4 3 2 1 0
N/A DATA

Figure D.27: CAL TADJ DATAx L Register Fields

149
 Table D.28: CAL TADJ DATAx L Register Description
Bit Field Reset Description
15 - 5 Reserved 0x0 Reserved
4 - 0 DATA 0x8 Data for the calibration DAC for cell x

CAL TADJ DATAx S Register

The CAL TADJ DATAx S registers are a group of registers that contain the manually

specified bits that set the timing adjustment for each cell via the local RZ drivers.
15 14 13 12 11 10 9 8
N/A

7 6 5 4 3 2 1 0
N/A DATA

Figure D.28: CAL TADJ DATAx S Register Fields

Table D.29: CAL TADJ DATAx S Register Description

Bit Field Reset Description
15 - 5 Reserved 0x0 Reserved
4 - 0 DATA 0x8 Data for the calibration DAC for cell x

DS CTL Register

The DS CTL register holds the control bits for the on chip DS Modulators.
15 14 13 12 11 10 9 8
N/A

7 6 5 4 3 2 1 0
N/A DAC SEL BP/HP ORDER

Figure D.29: DS CTL Register Fields

150
 Table D.30: DS CTL Register Description
Bit Field Reset Description
15 - 5 Reserved 0x0 Reserved
3 DAC SEL 0x0 Select between DAC0 and DAC1 for calibration
2 BP/HP 0x0 Highpass or Bandpass DS Modulation
0b = Highpass
1b = Bandpass
1-0 ORDER 0x0 DS Modulation Order
00b = Pass Through
01b = 1st Order
10b = 2nd Order
11b = 3rd Order

CLK CTLx Register

The CLK CTLx registers are a group of registers that control the on-chip clock

phase adjustment.
15 14 13 12 11 10 9 8
N/A CLKOUTDIV CMLx PHADJ

7 6 5 4 3 2 1 0
INVx PHADJ

Figure D.30: CLK CTLx Register Fields

Table D.31: CLK CTLx Register Description

Bit Field Reset Description
15 - 14 Reserved 0x0 Reserved
13 - 10 CLKOUTDIV 0x0 Clock Output Divide
Only one on at a time
Only in CLK CTL1
9-8 CMLx PHADJ 0x0 CML Clock Phase Adjustment
7-0 INVx PHADJ 0x0 Inverter (Digital) Fine Phase Adjustment

151
DS OFFSETx Register

The DS OFFSETx registers are a group of registers that hold the DC offset for a

stage of the DS Modulator.

15 14 13 12 11 10 9 8
N/A Offset

7 6 5 4 3 2 1 0
Offset

Figure D.31: DS OFFSETx Register Fields

Table D.32: DS CTL Register Description

Bit Field Reset Description
15 - 14 Reserved 0x0 Reserved
13 OFFSET 0x2000 DC offset value

CLK ALIGN Register

The CLK ALIGN controls the alignment between CML and CMOS clocks.
15 14 13 12 11 10 9 8
N/A

7 6 5 4 3 2 1 0
N/A CML1 ADJ CML0 ADJ CML ST2 INV CML ST1

Figure D.32: CLK ALIGN Register Fields

152
 Table D.33: CLK ALIGN Register Description
Bit Field Reset Description
15 - 7 Reserved 0x0 Reserved
6-5 CML1 ADJ 0x0 DAC1 CML clock adjust
4-3 CML0 ADJ 0x0 DAC0 CML clock adjust
2 CML ST2 0x0 CML Stage two 180◦ phase shift
1 INV 0x0 Digital (inverter buffer) 180◦ phase shift
0 CML ST1 0x0 CML Stage one 180◦ phase shift

DATA ARR Register

The DATA ARR toggles the arrangement (LSB/MSB) of the incoming serial data.
15 14 13 12 11 10 9 8
N/A DATAARR

7 6 5 4 3 2 1 0
DATAARR

Figure D.33: DATA ARR Register Fields

Table D.34: DATA ARR Register Description

Bit Field Reset Description
15 - 14 Reserved 0x0 Reserved
13 - 0 DATAARR 0x0 DATA arrangement control

153
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