PSD813F2V, PSD833F2V

PSD853F2V, PSD854F2V
Flash In-System Programmable (ISP)
Peripherals for 8-bit MCUs, 3V
PRELIMINARY DATA

FEATURES SUMMARY
■ FLASH IN-SYSTEM PROGRAMMABLE (ISP) Figure 1. Packages
PERIPHERAL FOR 8-BIT MCUS
■ DUAL BANK FLASH MEMORIES
– UP TO 2 Mbit OF PRIMARY FLASH
MEMORY (8 Uniform Sectors, 32K x8)
– UP TO 256 Kbit SECONDARY FLASH
MEMORY (4 Uniform Sectors)
– Concurrent operation: READ from one PQFP52 (M)
memory while erasing and writing the
other
■ UP TO 256 Kbit BATTERY-BACKED SRAM
■ 27 RECONFIGURABLE I/O PORTS
■ ENHANCED JTAG SERIAL PORT
■ PLD WITH MACROCELLS
– Over 3000 Gates of PLD: CPLD and
DPLD
– CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
– DPLD - user defined internal chip select PLCC52 (J)
decoding
■ 27 INDIVIDUALLY CONFIGURABLE I/O
PORT PINS
The can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– 16 of the I/O ports may be configured as TQFP64 (U)
open-drain outputs.
■ IN-SYSTEM PROGRAMMING (ISP) WITH
JTAG
– Built-in JTAG compliant serial port allows
full-chip In-System Programmability
– Efficient manufacturing allow easy
product testing and programming ■ HIGH ENDURANCE:
– Use low cost FlashLINK cable with PC – 100,000 Erase/WRITE Cycles of Flash
■ PAGE REGISTER Memory
– Internal page register that can be used to – 1,000 Erase/WRITE Cycles of PLD
expand the microcontroller address space – 15 Year Data Retention
by a factor of 256 ■ 3.3V±10% SINGLE SUPPLY VOLTAGE
■ PROGRAMMABLE POWER MANAGEMENT ■ STANDBY CURRENT AS LOW AS 25µA

June 2004 1/110

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PSD Register Description and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . . 20
Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Primary Flash Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reading the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data Polling Flag (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Toggle Flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Error Flag (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Erase Time-out Flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x, PSD854F2x) . . . . . . . . . . . . . . . . . . . . 26

ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset (RESET) Signal (on the PSD83xF2 and PSD85xF2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SECTOR SELECT AND SRAM SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . . 30
Configuration Modes for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . . 30

PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Data Byte Enable Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
OMC Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Port C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
For Users of the HC11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... . . . . 67
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... . . . . 67
I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... . . . . 67
Reset of Flash Memory Erase and Program Cycles (on the PSD834Fx) . ...... ...... . . . . 67

PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 69

Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

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PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

APPENDIX A.PQFP52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

APPENDIX B.PLCC52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

APPENDIX C.TQFP64 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

SUMMARY DESCRIPTION
The PSD8XXFX family of memory systems for mi- The innovative PSD8XXFX family solves key
crocontrollers (MCUs) brings In-System-Program- problems faced by designers when managing dis-
mability (ISP) to Flash memory and programmable crete Flash memory devices, such as:
logic. The result is a simple and flexible solution for – First-time In-System Programming (ISP)
embedded designs. PSD devices combine many
of the peripheral functions found in MCU based – Complex address decoding
applications. – Simultaneous read and write to the device.
Table 1 summarizes all the devices in the The JTAG Serial Interface block allows In-System
PSD834F2, PSD853F2, PSD854F2. Programming (ISP), and eliminates the need for
The CPLD in the PSD devices features an opti- an external Boot EPROM, or an external program-
mized macrocell logic architecture. The PSD mac- mer. To simplify Flash memory updates, program
execution is performed from a secondary Flash
rocell was created to address the unique
memory while the primary Flash memory is being
requirements of embedded system designs. It al-
lows direct connection between the system ad- updated. This solution avoids the complicated
hardware and software overhead necessary to im-
dress/data bus, and the internal PSD registers, to
plement IAP.
simplify communication between the MCU and
other supporting devices. ST makes available a software development tool,
The PSD device includes a JTAG Serial Program- PSDsoft Express, that generates ANSI-C compli-
ming interface, to allow In-System Programming ant code for use with your target MCU. This code
allows you to manipulate the non-volatile memory
(ISP) of the entire device. This feature reduces de-
(NVM) within the PSD. Code examples are also
velopment time, simplifies the manufacturing flow,
and dramatically lowers the cost of field upgrades. provided for:
Using ST’s special Fast-JTAG programming, a de- – Flash memory IAP via the UART of the host
sign can be rapidly programmed into the PSD in as MCU
little as seven seconds. – Memory paging to execute code across
several PSD memory pages
– Loading, reading, and manipulation of PSD
macrocells by the MCU.

Table 1. Product Range

Number of Serial
Primary Flash Secondary
(1) (2) Macrocells ISP Turbo
Part Number Memory Flash Memory SRAM I/O Ports
JTAG/ Mode
(8 Sectors) 4 Sectors)
Input Output ISC Port

PSD813F2 1 Mbit 256 Kbit 16 Kbit 27 24 16 yes yes

PSD813F3 1 Mbit none 16 Kbit 27 24 16 yes yes

PSD813F4 1 Mbit 256 Kbit none 27 24 16 yes yes

PSD813F5 1 Mbit none none 27 24 16 yes yes

PSD833F2 1 Mbit 256 Kbit 64 Kbit 27 24 16 yes yes

PSD834F2 2 Mbit 256 Kbit 64 Kbit 27 24 16 yes yes

PSD853F2 1 Mbit 256 Kbit 256 Kbit 27 24 16 yes yes

PSD854F2 2 Mbit 256 Kbit 256 Kbit 27 24 16 yes yes

Note: 1. All products support: JTAG serial ISP, MCU parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power Management
Unit (PMU), Automatic Power-down (APD)
2. SRAM may be backed up using an external battery.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Figure 2. PQFP52 Connections

40 CNTLO
41 RESET
43 CNTL1
42 CNTL2
46 GND
52 PB0
51 PB1
50 PB2
49 PB3
48 PB4
47 PB5

45 PB6
44 PB7
PD2 1 39 AD15
PD1 2 38 AD14
PD0 3 37 AD13
PC7 4 36 AD12
PC6 5 35 AD11
PC5 6 34 AD10
PC4 7 33 AD9
VCC 8 32 AD8
GND 9 31 VCC
PC3 10 30 AD7
PC2 11 29 AD6
PC1 12 28 AD5
PC0 13 27 AD4
PA7 14
PA6 15
PA5 16
PA4 17
PA3 18
GND 19
PA2 20
PA1 21
PA0 22
AD0 23
AD1 24
AD2 25
AD3 26

AI02858

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Figure 3. PLCC52 Connections

RESET
CNTL2

CNTL0
CNTL1
PB0
PB1
PB2
PB3
PB4
PB5
GND
PB6
PB7
4
7

3
2

52
51
50
49
48
47
6

1
PD2 8 46 AD15
PD1 9 45 AD14
PD0 10 44 AD13
PC7 11 43 AD12
PC6 12 42 AD11
PC5 13 41 AD10
PC4 14 40 AD9
VCC 15 39 AD8
GND 16 38 VCC
PC3 17 37 AD7
PC2 18 36 AD6
PC1 19 35 AD5
PC0 20 32 34 AD4
21
22
23
24
25
26
27
28
29

31

33
30
PA7
PA6
PA5
PA4
PA3

PA2
PA1
PA0

AD2
AD1

AD3
AD0
GND

AI02857

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Figure 4. TQFP64 Connections

50 RESET
52 CNTL1
51 CNTL2
56 GND
55 GND
62 PB0
61 PB1
60 PB2
59 PB3
58 PB4
57 PB5

54 PB6
53 PB7
64 NC
63 NC

49 NC
PD2 1 48 CNTL0
PD1 2 47 AD15
PD0 3 46 AD14
PC7 4 45 AD13
PC6 5 44 AD12
PC5 6 43 AD11
VCC 7 42 AD10
VCC 8 41 AD9
VCC 9 40 AD8
GND 10 39 VCC
GND 11 38 VCC
PC3 12 37 AD7
PC2 13 36 AD6
PC1 14 35 AD5
PC0 15 34 AD4
NC 16 33 AD3
NC 17
NC 18
PA7 19
PA6 20
PA5 21
PA4 22
PA3 23
GND 24
GND 25
PA2 26
PA1 27
PA0 28
AD0 29
AD1 30
ND 31
AD2 32

AI09645

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

PIN DESCRIPTION

Table 2. Pin Description (for the PLCC52 package - Note 1)

Pin Name Pin Type Description
This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect AD0-AD7 to this port.

If your MCU does not have a multiplexed address/data bus, or you are using an 80C251
ADIO0-7 30-37 I/O in page mode, connect A0-A7 to this port.

If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port.

ALE or AS latches the address. The PSD drives data out only if the READ signal is active
and one of the PSD functional blocks was selected. The addresses on this port are
passed to the PLDs.
This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect A8-A15 to this port.

If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port.

ADIO8-15 39-46 I/O If you are using an 80C251 in page mode, connect AD8-AD15 to this port.

If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this
port.

ALE or AS latches the address. The PSD drives data out only if the READ signal is active
and one of the PSD functional blocks was selected. The addresses on this port are
passed to the PLDs.
The following control signals can be connected to this port, based on your MCU:
WR – active Low Write Strobe input.

CNTL0 47 I R_W – active High READ/active Low write input.

This port is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
The following control signals can be connected to this port, based on your MCU:
RD – active Low Read Strobe input.

E – E clock input.

DS – active Low Data Strobe input.

CNTL1 50 I
PSEN – connect PSEN to this port when it is being used as an active Low READ signal.
For example, when the 80C251 outputs more than 16 address bits, PSEN is actually the
READ signal.

This port is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
This port can be used to input the PSEN (Program Select Enable) signal from any MCU
that uses this signal for code exclusively. If your MCU does not output a Program Select
CNTL2 49 I
Enable signal, this port can be used as a generic input. This port is connected to the
PLDs.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Pin Name Pin Type Description

Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low
Reset 48 I
at Power-up.
These pins make up Port A. These port pins are configurable and can have the following
functions:
MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellAB0-7) outputs.

Inputs to the PLDs.

PA0 29
PA1 28
Latched address outputs (see Table 6).
PA2 27
PA3 25
I/O Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA in
PA4 24
burst mode.
PA5 23
PA6 22
As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
PA7 21
D0/A16-D3/A19 in M37702M2 mode.

Peripheral I/O mode.

Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,
PA4-PA7 can be configured as CMOS or Open Drain Outputs.
These pins make up Port B. These port pins are configurable and can have the following
functions:
PB0 7 MCU I/O – write to or read from a standard output or input port.
PB1 6
PB2 5 CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
PB3 4
I/O
PB4 3 Inputs to the PLDs.
PB5 2
PB6 52 Latched address outputs (see Table 6).
PB7 51
Note: PB0-PB3 can only output CMOS signals with an option for high slew rate.
However, PB4-PB7 can be configured as CMOS or Open Drain Outputs.
PC0 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC0) output.

PC0 20 I/O Input to the PLDs.

TMS Input2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC1 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC1) output.

PC1 19 I/O Input to the PLDs.

TCK Input2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Pin Name Pin Type Description

PC2 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC2) output.

PC2 18 I/O
Input to the PLDs.

VSTBY – SRAM stand-by voltage input for SRAM battery backup.

This pin can be configured as a CMOS or Open Drain output.

PC3 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC3) output.

Input to the PLDs.

PC3 17 I/O
TSTAT output2 for the JTAG Serial Interface.

Ready/Busy output for parallel In-System Programming (ISP).

This pin can be configured as a CMOS or Open Drain output.

PC4 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC4) output.

Input to the PLDs.

PC4 14 I/O
TERR output2 for the JTAG Serial Interface.

Battery-on Indicator (VBATON). Goes High when power is being drawn from the external
battery.

This pin can be configured as a CMOS or Open Drain output.

PC5 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC5) output.

PC5 13 I/O Input to the PLDs.

TDI input2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC6 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC6) output.

PC6 12 I/O Input to the PLDs.

TDO output2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Pin Name Pin Type Description

PC7 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC7) output.

PC7 11 I/O
Input to the PLDs.

DBE – active Low Data Byte Enable input from 68HC912 type MCUs.

This pin can be configured as a CMOS or Open Drain output.

PD0 pin of Port D. This port pin can be configured to have the following functions:
ALE/AS input latches address output from the MCU.

MCU I/O – write or read from a standard output or input port.

PD0 10 I/O
Input to the PLDs.

CPLD output (External Chip Select).

PD1 pin of Port D. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.

Input to the PLDs.

PD1 9 I/O
CPLD output (External Chip Select).

CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and
the CPLD AND Array.
PD2 pin of Port D. This port pin can be configured to have the following functions:
MCU I/O - write to or read from a standard output or input port.

Input to the PLDs.

PD2 8 I/O
CPLD output (External Chip Select).

PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/O.
When High, the PSD memory blocks are disabled to conserve power.
VCC 15, 38 Supply Voltage

1, 16,
GND Ground pins
26
Note: 1. The pin numbers in this table are for the PLCC package only. See the package information from Table 74., page 102 onwards, for
pin numbers on other package types.
2. These functions can be multiplexed with other functions.

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14/110
ADDRESS/DATA/CONTROL BUS

PLD
INPUT
BUS 1 OR 2 MBIT PRIMARY
PAGE
REGISTER FLASH MEMORY
EMBEDDED
ALGORITHM 8 SECTORS

8
POWER
MANGMT VSTDBY
Figure 5. PSD Block Diagram

CNTL0, 256 KBIT SECONDARY UNIT (PC2)

SECTOR
CNTL1, NON-VOLATILE MEMORY
PROG. SELECTS
CNTL2 FLASH DECODE (BOOT OR DATA)
MCU BUS 4 SECTORS
INTRF. PLD (DPLD)
73
SECTOR
SELECTS

SRAM SELECT 256 KBIT BATTERY

BACKUP SRAM PROG.
PORT PA0 – PA7
PERIP I/O MODE SELECTS
CSIOP PORT
RUNTIME CONTROL A
AD0 – AD15
ADIO AND I/O REGISTERS
PORT

FLASH ISP CPLD 3 EXT CS TO PORT D

73
(CPLD)
16 OUTPUT MACROCELLS PROG.
PORT A ,B & C PORT PB0 – PB7
PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

PORT
24 INPUT MACROCELLS B
CLKIN PORT A ,B & C

PROG.
PORT PC0 – PC7

GLOBAL MACROCELL FEEDBACK OR PORT INPUT PORT

CONFIG. & C
SECURITY
CLKIN

PROG.
PORT PD0 – PD2
PLD, CONFIGURATION JTAG
CLKIN SERIAL PORT
& FLASH MEMORY
(PD1) D
LOADER CHANNEL

AI02861E
 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

PSD ARCHITECTURAL OVERVIEW

PSD devices contain several major functional The DPLD is used to decode addresses and to
blocks. Figure 5 shows the architecture of the PSD generate Sector Select signals for the PSD inter-
device family. The functions of each block are de- nal memory and registers. The DPLD has combi-
scribed briefly in the following sections. Many of natorial outputs. The CPLD has 16 Output
the blocks perform multiple functions and are user Macrocells (OMC) and 3 combinatorial outputs.
configurable. The PSD also has 24 Input Macrocells (IMC) that
Memory can be configured as inputs to the PLDs. The
PLDs receive their inputs from the PLD Input Bus
Each of the memory blocks is briefly discussed in and are differentiated by their output destinations,
the following paragraphs. A more detailed discus-
number of product terms, and macrocells.
sion can be found in the section entitled Memory
Blocks, page 19. The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
The 1 Mbit or 2 Mbit (128K x 8, or 256K x 8) Flash by the Turbo Bit in PMMR0 and other bits in the
memory is the primary memory of the PSD. It is di- PMMR2. These registers are set by the MCU at
vided into 8 equally-sized sectors that are individ-
run-time. There is a slight penalty to PLD propaga-
ually selectable.
tion time when invoking the power management
The optional 256 Kbit (32K x 8) secondary Flash features.
memory is divided into 4 equally-sized sectors. I/O Ports
Each sector is individually selectable.
The PSD has 27 individually configurable I/O pins
The optional SRAM is intended for use as a
distributed over the four ports (Port A, B, C, and
scratch-pad memory or as an extension to the
D). Each I/O pin can be individually configured for
MCU SRAM. If an external battery is connected to different functions. Ports can be configured as
Voltage Stand-by (VSTBY, PC2), data is retained in
standard MCU I/O ports, PLD I/O, or latched ad-
the event of power failure.
dress outputs for MCUs using multiplexed ad-
Each sector of memory can be located in a differ- dress/data buses.
ent address space as defined by the user. The ac- The JTAG pins can be enabled on Port C for In-
cess times for all memory types includes the System Programming (ISP).
address latching and DPLD decoding time.
Ports A and B can also be configured as a data
Page Register
port for a non-multiplexed bus.
The 8-bit Page Register expands the address
MCU Bus Interface
range of the MCU by up to 256 times. The paged
address can be used as part of the address space PSD interfaces easily with most 8-bit MCUs that
to access external memory and peripherals, or in- have either multiplexed or non-multiplexed ad-
ternal memory and I/O. The Page Register can dress/data buses. The device is configured to re-
also be used to change the address mapping of spond to the MCU’s control signals, which are also
sectors of the Flash memories into different mem- used as inputs to the PLDs. For examples, please
ory spaces for IAP. see the section entitled MCU Bus Interface
Examples, page 45.
PLDs
The device contains two PLDs, the Decode PLD
(DPLD) and the Complex PLD (CPLD), as shown Table 3. PLD I/O
in Table 3, each optimized for a different function. Product
Name Inputs Outputs
The functional partitioning of the PLDs reduces Terms
power consumption, optimizes cost/performance,
Decode PLD (DPLD) 73 17 42
and eases design entry.
Complex PLD (CPLD) 73 19 140

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

JTAG Port
In-System Programming (ISP) can be performed MCU inactivity. The APD Unit has a Power-down
through the JTAG signals on Port C. This serial in- mode that helps reduce power consumption.
terface allows complete programming of the entire The PSD also has some bits that are configured at
PSD device. A blank device can be completely run-time by the MCU to reduce power consump-
programmed. The JTAG signals (TMS, TCK, tion of the CPLD. The Turbo Bit in PMMR0 can be
TSTAT, TERR, TDI, TDO) can be multiplexed with reset to '0' and the CPLD latches its outputs and
other functions on Port C. Table 4 indicates the goes to sleep until the next transition on its inputs.
JTAG pin assignments.
Additionally, bits in PMMR2 can be set by the
In-System Programming (ISP) MCU to block signals from entering the CPLD to
Using the JTAG signals on Port C, the entire PSD reduce power consumption. Please see the sec-
device can be programmed or erased without the tion entitled POWER MANAGEMENT, page 62 for
use of the MCU. The primary Flash memory can more details.
also be programmed in-system by the MCU exe-
cuting the programming algorithms out of the sec- Table 4. JTAG SIgnals on Port C
ondary memory, or SRAM. The secondary
memory can be programmed the same way by ex- Port C Pins JTAG Signal
ecuting out of the primary Flash memory. The PLD PC0 TMS
or other PSD Configuration blocks can be pro-
grammed through the JTAG port or a device pro- PC1 TCK
grammer. Table 5 indicates which programming
methods can program different functional blocks PC3 TSTAT
of the PSD. PC4 TERR
Power Management Unit (PMU)
PC5 TDI
The Power Management Unit (PMU) gives the
user control of the power consumption on selected PC6 TDO
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during

Table 5. Methods of Programming Different Functional Blocks of the PSD

Functional Block JTAG Programming Device Programmer IAP
Primary Flash Memory Yes Yes Yes
Secondary Flash Memory Yes Yes Yes
PLD Array (DPLD and CPLD) Yes Yes No
PSD Configuration Yes Yes No

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

DEVELOPMENT SYSTEM
The PSD8XXFX family is supported by PSDsoft PSDsoft Express directly supports two low cost
Express, a Windows-based software development device programmers form ST: PSDpro and
tool. A PSD design is quickly and easily produced FlashLINK (JTAG). Both of these programmers
in a point and click environment. The designer may be purchased through your local distributor/
does not need to enter Hardware Description Lan- representative, or directly from our web site using
guage (HDL) equations, unless desired, to define a credit card. The PSD is also supported by third
PSD pin functions and memory map information. party device programmers. See our web site for
The general design flow is shown in Figure 6. PS- the current list.
Dsoft Express is available from our web site (the
address is given on the back page of this data
sheet) or other distribution channels.

Figure 6. PSDsoft Express Development Tool

PSDabel
PLD DESCRIPTION
MODIFY ABEL TEMPLATE FILE
OR GENERATE NEW FILE

PSD Configuration PSD TOOLS

CONFIGURE MCU BUS GENERATE C CODE
INTERFACE AND OTHER SPECIFIC TO PSD
PSD ATTRIBUTES FUNCTIONS

PSD Fitter
LOGIC SYNTHESIS USER'S CHOICE OF
FIRMWARE
AND FITTING MICROCONTROLLER
HEX OR S-RECORD COMPILER/LINKER
ADDRESS TRANSLATION FORMAT
AND MEMORY MAPPING

*.OBJ FILE

PSD Simulator PSD Programmer *.OBJ AND *.SVF

FILES AVAILABLE
PSDsilos III PSDPro, or FOR 3rd PARTY
DEVICE SIMULATION FlashLINK (JTAG) PROGRAMMERS
(OPTIONAL) (CONVENTIONAL or
JTAG-ISC)

AI04918

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

PSD REGISTER DESCRIPTION AND ADDRESS OFFSET

Table 6 shows the offset addresses to the PSD Table 7 provides brief descriptions of the registers
registers relative to the CSIOP base address. The in CSIOP space. The following section gives a
CSIOP space is the 256 bytes of address that is al- more detailed description.
located by the user to the internal PSD registers.

Table 6. I/O Port Latched Address Output Assignments (Note1)

Port A Port B
MCU
Port A (3:0) Port A (7:4) Port B (3:0) Port B (7:4)
8051XA (8-bit) N/A Address a7-a4 Address a11-a8 N/A
80C251 (page mode) N/A N/A Address a11-a8 Address a15-a12
All other 8-bit multiplexed Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4
8-bit non-multiplexed bus N/A N/A Address a3-a0 Address a7-a4
Note: 1. See the section entitled I/O PORTS, page 51, on how to enable the Latched Address Output function.
2. N/A = Not Applicable

Table 7. Register Address Offset

Register Name Port A Port B Port C Port D Other1 Description
Data In 00 01 10 11 Reads Port pin as input, MCU I/O input mode
Control 02 03 Selects mode between MCU I/O or Address Out
Stores data for output to Port pins, MCU I/O
Data Out 04 05 12 13
output mode
Direction 06 07 14 15 Configures Port pin as input or output
Configures Port pins as either CMOS or Open
Drive Select 08 09 16 17 Drain on some pins, while selecting high slew rate
on other pins.
Input Macrocell 0A 0B 18 Reads Input Macrocells
Reads the status of the output enable to the I/O
Enable Out 0C 0D 1A 1B
Port driver
Output Macrocells READ – reads output of macrocells AB
20 20
AB WRITE – loads macrocell flip-flops
Output Macrocells READ – reads output of macrocells BC
21 21
BC WRITE – loads macrocell flip-flops
Mask Macrocells AB 22 22 Blocks writing to the Output Macrocells AB
Mask Macrocells BC 23 23 Blocks writing to the Output Macrocells BC
Primary Flash
C0 Read only – Primary Flash Sector Protection
Protection
Secondary Flash Read only – PSD Security and Secondary Flash
C2
memory Protection memory Sector Protection
JTAG Enable C7 Enables JTAG Port
PMMR0 B0 Power Management Register 0
PMMR2 B4 Power Management Register 2
Page E0 Page Register
Places PSD memory areas in Program and/or
VM E2
Data space on an individual basis.
Note: 1. Other registers that are not part of the I/O ports.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

DETAILED OPERATION
As shown in Figure 5., page 14, the PSD consists Memory Blocks
of six major types of functional blocks: The PSD has the following memory blocks:
■ Memory Blocks – Primary Flash memory
■ PLD Blocks – Optional Secondary Flash memory
■ MCU Bus Interface – Optional SRAM
■ I/O Ports The Memory Select signals for these blocks origi-
■ Power Management Unit (PMU) nate from the Decode PLD (DPLD) and are user-
■ JTAG Interface defined in PSDsoft Express.
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.

Table 8. Memory Block Size and Organization

Primary Flash Memory Secondary Flash Memory SRAM
Sector Sector Size Sector Select Sector Size Sector Select SRAM Size SRAM Select
Number (Bytes) Signal (Bytes) Signal (Bytes) Signal
0 32K FS0 16K CSBOOT0 256K RS0
1 32K FS1 16K CSBOOT1
2 32K FS2 16K CSBOOT2
3 32K FS3 16K CSBOOT3
4 32K FS4
5 32K FS5
6 32K FS6
7 32K FS7
Total 512K 8 Sectors 64K 4 Sectors 256K

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Primary Flash Memory and Secondary Flash Memory Operation. The primary Flash memory
memory Description and secondary Flash memory are addressed
The primary Flash memory is divided evenly into through the MCU Bus Interface. The MCU can ac-
eight equal sectors. The secondary Flash memory cess these memories in one of two ways:
is divided into four equal sectors. Each sector of – The MCU can execute a typical bus WRITE or
either memory block can be separately protected READ operation just as it would if accessing a
from Program and Erase cycles. RAM or ROM device using standard bus
Flash memory may be erased on a sector-by-sec- cycles.
tor basis. Flash sector erasure may be suspended – The MCU can execute a specific instruction
while data is read from other sectors of the block that consists of several WRITE and READ
and then resumed after reading. operations. This involves writing specific data
During a Program or Erase cycle in Flash memory, patterns to special addresses within the Flash
the status can be output on Ready/Busy (PC3). memory to invoke an embedded algorithm.
This pin is set up using PSDsoft Express Configu- These instructions are summarized in Table
ration. 9., page 21.
Memory Block Select Signals Typically, the MCU can read Flash memory using
READ operations, just as it would read a ROM de-
The DPLD generates the Select signals for all the vice. However, Flash memory can only be altered
internal memory blocks (see the section entitled
using specific Erase and Program instructions. For
PLDS, page 33). Each of the eight sectors of the
example, the MCU cannot write a single byte di-
primary Flash memory has a Select signal (FS0-
rectly to Flash memory as it would write a byte to
FS7) which can contain up to three product terms. RAM. To program a byte into Flash memory, the
Each of the four sectors of the secondary Flash
MCU must execute a Program instruction, then
memory has a Select signal (CSBOOT0-
test the status of the Program cycle. This status
CSBOOT3) which can contain up to three product test is achieved by a READ operation or polling
terms. Having three product terms for each Select Ready/Busy (PC3).
signal allows a given sector to be mapped in differ-
ent areas of system memory. When using a MCU Flash memory can also be read by using special
with separate Program and Data space, these instructions to retrieve particular Flash device in-
flexible Select signals allow dynamic re-mapping formation (sector protect status and ID).
of sectors from one memory space to the other.
Ready/Busy (PC3). This signal can be used to
output the Ready/Busy status of the PSD. The out-
put on Ready/Busy (PC3) is a 0 (Busy) when Flash
memory is being written to, or when Flash memory
is being erased. The output is a 1 (Ready) when
no WRITE or Erase cycle is in progress.

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Table 9. Instructions
FS0-FS7 or
Instruction CSBOOT0- Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
CSBOOT3
“READ”
READ5 1
RD @ RA
Read Main AAh@ 55h@ 90h@ Read identifier
1
Flash ID6 X555h XAAAh X555h (A6,A1,A0 = 0,0,1)
Read Sector AAh@ 55h@ 90h@ Read identifier
1
Protection6,8,13 X555h XAAAh X555h (A6,A1,A0 = 0,1,0)
Program a AAh@ 55h@ A0h@
1 PD@ PA
Flash Byte13 X555h XAAAh X555h
Flash Sector AAh@ 55h@ 80h@ 55h@ 30h@ 30h7@
1 AAh@ X555h
Erase7,13 X555h XAAAh X555h XAAAh SA next SA
Flash Bulk AAh@ 55h@ 80h@ 55h@ 10h@
1 AAh@ X555h
Erase13 X555h XAAAh X555h XAAAh X555h
Suspend B0h@
1
Sector Erase11 XXXXh
Resume 30h@
1
Sector Erase12 XXXXh
F0h@
Reset6 1
XXXXh
AAh@ 55h@ 20h@
Unlock Bypass 1
X555h XAAAh X555h
Unlock Bypass A0h@
1 PD@ PA
Program9 XXXXh
Unlock Bypass 90h@ 00h@
1
Reset10 XXXXh XXXXh
Note: 1. All bus cycles are WRITE bus cycles, except the ones with the “READ” label
2. All values are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data read from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0).
PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be
erased, or verified, must be Active (High).
3. Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft Express.
4. Only address bits A11-A0 are used in instruction decoding.
5. No Unlock or instruction cycles are required when the device is in the READ Mode
6. The Reset instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection Sta-
tus, or if the Error Flag Bit (DQ5/DQ13) goes High.
7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0)
9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
mode.
11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status
of the primary Flash memory.

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

INSTRUCTIONS
An instruction consists of a sequence of specific for maximum security of the data contents and to
operations. Each received byte is sequentially de- remove the possibility of a byte being written on
coded by the PSD and not executed as a standard the first edge of Write Strobe (WR, CNTL0). Any
WRITE operation. The instruction is executed WRITE cycle initiation is locked when VCC is be-
when the correct number of bytes are properly re- low VLKO.
ceived and the time between two consecutive READ
bytes is shorter than the time-out period. Some in-
Under typical conditions, the MCU may read the
structions are structured to include READ opera-
tions after the initial WRITE operations. primary Flash memory or the secondary Flash
memory using READ operations just as it would a
The instruction must be followed exactly. Any in- ROM or RAM device. Alternately, the MCU may
valid combination of instruction bytes or time-out use READ operations to obtain status information
between two consecutive bytes while addressing about a Program or Erase cycle that is currently in
Flash memory resets the device logic into READ progress. Lastly, the MCU may use instructions to
Mode (Flash memory is read like a ROM device). read special data from these memory blocks. The
The PSD supports the instructions summarized in following sections describe these READ functions.
Table 9., page 21: Read Memory Contents
Flash memory: Primary Flash memory and secondary Flash
■ Erase memory by chip or sector memory are placed in the READ Mode after Pow-
■ Suspend or resume sector erase er-up, chip reset, or a Reset Flash instruction (see
Table 9., page 21). The MCU can read the memo-
■ Program a Byte
ry contents of the primary Flash memory or the
■ Reset to READ Mode secondary Flash memory by using READ opera-
■ Read primary Flash Identifier value tions any time the READ operation is not part of an
■ Read Sector Protection Status instruction.
■ Bypass (on the PSD833F2, PSD834F2, Read Primary Flash Identifier
PSD853F2 and PSD854F2) The primary Flash memory identifier is read with
These instructions are detailed in Table an instruction composed of 4 operations: 3 specific
9., page 21. For efficient decoding of the instruc- WRITE operations and a READ operation (see Ta-
tions, the first two bytes of an instruction are the ble 9., page 21). During the READ operation, ad-
coded cycles and are followed by an instruction dress bits A6, A1, and A0 must be '0,0,1,'
byte or confirmation byte. The coded cycles con- respectively, and the appropriate Sector Select
sist of writing the data AAh to address X555h dur- (FS0-FS7) must be High. The identifier for the
ing the first cycle and data 55h to address XAAAh PSD813F2/3/4/5 is E4h, and for the PSD83xF2 or
during the second cycle. Address signals A15-A12 PSD85xF2 it is E7h.
are Don’t Care during the instruction WRITE cy- Read Memory Sector Protection Status
cles. However, the appropriate Sector Select The primary Flash memory Sector Protection Sta-
(FS0-FS7 or CSBOOT0-CSBOOT3) must be se- tus is read with an instruction composed of 4 oper-
lected. ations: 3 specific WRITE operations and a READ
The primary and secondary Flash memories have operation (see Table 9., page 21). During the
the same instruction set (except for Read Primary READ operation, address Bits A6, A1, and A0
Flash Identifier). The Sector Select signals deter- must be '0,1,0,' respectively, while Sector Select
mine which Flash memory is to receive and exe- (FS0-FS7 or CSBOOT0-CSBOOT3) designates
cute the instruction. The primary Flash memory is the Flash memory sector whose protection has to
selected if any one of Sector Select (FS0-FS7) is be verified. The READ operation produces 01h if
High, and the secondary Flash memory is selected the Flash memory sector is protected, or 00h if the
if any one of Sector Select (CSBOOT0- sector is not protected.
CSBOOT3) is High. The sector protection status for all NVM blocks
Power-up Mode (primary Flash memory or secondary Flash mem-
The PSD internal logic is reset upon Power-up to ory) can also be read by the MCU accessing the
the READ Mode. Sector Select (FS0-FS7 and Flash Protection registers in PSD I/O space. See
CSBOOT0-CSBOOT3) must be held Low, and the section entitled Flash Memory Sector
Write Strobe (WR, CNTL0) High, during Power-up Protect, page 28 for register definitions.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Reading the Erase/Program Status Bits

The PSD provides several status bits to be used For Flash memory, the MCU can perform a READ
by the MCU to confirm the completion of an Erase operation to obtain these status bits while an
or Program cycle of Flash memory. These status Erase or Program instruction is being executed by
bits minimize the time that the MCU spends per- the embedded algorithm. See the section entitled
forming these tasks and are defined in Table 10. PROGRAMMING FLASH MEMORY, page 25 for
The status bits can be read as many times as details.
needed.

Table 10. Status Bit

FS0-FS7/CSBOOT0-
Functional Block DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
CSBOOT3
Erase
Data Toggle Error
Flash Memory VIH X Time- X X X
Polling Flag Flag
out
Note: 1. X = Not guaranteed value, can be read either '1' or ’0.’
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.

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Data Polling Flag (DQ7)

When erasing or programming in Flash memory, – The Toggle Flag Bit (DQ6) is effective after the
the Data Polling Flag Bit (DQ7) outputs the com- fourth WRITE pulse (for a Program instruction)
plement of the bit being entered for programming/ or after the sixth WRITE pulse (for an Erase
writing on the DQ7 Bit. Once the Program instruc- instruction).
tion or the WRITE operation is completed, the true – If the byte to be programmed belongs to a
logic value is read on the Data Polling Flag Bit protected Flash memory sector, the
(DQ7, in a READ operation). instruction is ignored.
– Data Polling is effective after the fourth WRITE – If all the Flash memory sectors selected for
pulse (for a Program instruction) or after the erasure are protected, the Toggle Flag Bit
sixth WRITE pulse (for an Erase instruction). It (DQ6) toggles to '0' for about 100µs and then
must be performed at the address being returns to the previous addressed byte.
programmed or at an address within the Flash
memory sector being erased. Error Flag (DQ5)
– During an Erase cycle, the Data Polling Flag During a normal Program or Erase cycle, the Error
Flag Bit (DQ5) is to ’0.’ This bit is set to '1' when
Bit (DQ7) outputs a ’0.’ After completion of the
there is a failure during Flash memory Byte Pro-
cycle, the Data Polling Flag Bit (DQ7) outputs
the last bit programmed (it is a '1' after gram, Sector Erase, or Bulk Erase cycle.
erasing). In the case of Flash memory programming, the Er-
ror Flag Bit (DQ5) indicates the attempt to program
– If the byte to be programmed is in a protected
a Flash memory bit from the programmed state,
Flash memory sector, the instruction is
ignored. ’0,’ to the erased state, '1,' which is not valid. The
Error Flag Bit (DQ5) may also indicate a Time-out
– If all the Flash memory sectors to be erased condition while attempting to program a byte.
are protected, the Data Polling Flag Bit (DQ7)
In case of an error in a Flash memory Sector Erase
is reset to '0' for about 100µs, and then returns
or Byte Program cycle, the Flash memory sector in
to the previous addressed byte. No erasure is
performed. which the error occurred or to which the pro-
grammed byte belongs must no longer be used.
Toggle Flag (DQ6) Other Flash memory sectors may still be used.
The PSD offers another way for determining when The Error Flag Bit (DQ5) is reset after a Reset
the Flash memory Program cycle is completed. Flash instruction.
During the internal WRITE operation and when ei- Erase Time-out Flag (DQ3)
ther the FS0-FS7 or CSBOOT0-CSBOOT3 is true,
The Erase Time-out Flag Bit (DQ3) reflects the
the Toggle Flag Bit (DQ6) toggles from '0' to '1' and
time-out period allowed between two consecutive
'1' to '0' on subsequent attempts to read any byte
of the memory. Sector Erase instructions. The Erase Time-out
Flag Bit (DQ3) is reset to '0' after a Sector Erase
When the internal cycle is complete, the toggling cycle for a time period of 100µs + 20% unless an
stops and the data read on the Data Bus D0-D7 is additional Sector Erase instruction is decoded. Af-
the addressed memory byte. The device is now ter this time period, or when the additional Sector
accessible for a new READ or WRITE operation. Erase instruction is decoded, the Erase Time-out
The cycle is finished when two successive READs Flag Bit (DQ3) is set to '1.'
yield the same output data.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

PROGRAMMING FLASH MEMORY

Flash memory must be erased prior to being pro- ming algorithm has completed, to compare the
grammed. A byte of Flash memory is erased to all byte that was written to the Flash memory with the
1s (FFh), and is programmed by setting selected byte that was intended to be written.
bits to ’0.’ The MCU may erase Flash memory all When using the Data Polling method during an
at once or by-sector, but not byte-by-byte. Howev- Erase cycle, Figure 7 still applies. However, the
er, the MCU may program Flash memory byte-by- Data Polling Flag Bit (DQ7) is '0' until the Erase cy-
byte. cle is complete. A 1 on the Error Flag Bit (DQ5) in-
The primary and secondary Flash memories re- dicates a time-out condition on the Erase cycle; a
quire the MCU to send an instruction to program a 0 indicates no error. The MCU can read any loca-
byte or to erase sectors (see Table 9., page 21). tion within the sector being erased to get the Data
Once the MCU issues a Flash memory Program or Polling Flag Bit (DQ7) and the Error Flag Bit
Erase instruction, it must check for the status bits (DQ5).
for completion. The embedded algorithms that are PSDsoft Express generates ANSI C code func-
invoked inside the PSD support several means to tions which implement these Data Polling algo-
provide status to the MCU. Status may be checked rithms.
using any of three methods: Data Polling, Data
Toggle, or Ready/Busy (PC3). Figure 7. Data Polling Flowchart
Data Polling
Polling on the Data Polling Flag Bit (DQ7) is a START
method of checking whether a Program or Erase
cycle is in progress or has completed. Figure 7
shows the Data Polling algorithm. READ DQ5 & DQ7
at VALID ADDRESS
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the byte to be pro-
DQ7 YES
grammed in Flash memory to check status. The =
Data Polling Flag Bit (DQ7) of this location be- DATA
comes the complement of b7 of the original data NO
byte to be programmed. The MCU continues to
poll this location, comparing the Data Polling Flag
NO DQ5
Bit (DQ7) and monitoring the Error Flag Bit (DQ5).
=1
When the Data Polling Flag Bit (DQ7) matches b7
of the original data, and the Error Flag Bit (DQ5) YES
remains ’0,’ the embedded algorithm is complete.
If the Error Flag Bit (DQ5) is '1,' the MCU should READ DQ7
test the Data Polling Flag Bit (DQ7) again since
the Data Polling Flag Bit (DQ7) may have changed
DQ7 YES
simultaneously with the Error Flag Bit (DQ5, see =
Figure 7). DATA

The Error Flag Bit (DQ5) is set if either an internal NO

time-out occurred while the embedded algorithm
FAIL PASS
attempted to program the byte or if the MCU at-
tempted to program a '1' to a bit that was not
erased (not erased is logic '0'). AI01369B

It is suggested (as with all Flash memories) to read

the location again after the embedded program-

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Data Toggle
Checking the Toggle Flag Bit (DQ6) is a method of The Flash memory then enters the Unlock Bypass
determining whether a Program or Erase cycle is mode. A two-cycle Unlock Bypass Program in-
in progress or has completed. Figure 8 shows the struction is all that is required to program in this
Data Toggle algorithm. mode. The first cycle in this instruction contains
When the MCU issues a Program instruction, the the Unlock Bypass Program code, A0h. The sec-
embedded algorithm within the PSD begins. The ond cycle contains the program address and data.
MCU then reads the location of the byte to be pro- Additional data is programmed in the same man-
grammed in Flash memory to check status. The ner. These instructions dispense with the initial
Toggle Flag Bit (DQ6) of this location toggles each two Unlock cycles required in the standard Pro-
time the MCU reads this location until the embed- gram instruction, resulting in faster total Flash
ded algorithm is complete. The MCU continues to memory programming.
read this location, checking the Toggle Flag Bit During the Unlock Bypass mode, only the Unlock
(DQ6) and monitoring the Error Flag Bit (DQ5). Bypass Program and Unlock Bypass Reset Flash
When the Toggle Flag Bit (DQ6) stops toggling instructions are valid.
(two consecutive reads yield the same value), and To exit the Unlock Bypass mode, the system must
the Error Flag Bit (DQ5) remains ’0,’ the embed- issue the two-cycle Unlock Bypass Reset Flash in-
ded algorithm is complete. If the Error Flag Bit struction. The first cycle must contain the data
(DQ5) is '1,' the MCU should test the Toggle Flag 90h; the second cycle the data 00h. Addresses are
Bit (DQ6) again, since the Toggle Flag Bit (DQ6) Don’t Care for both cycles. The Flash memory
may have changed simultaneously with the Error then returns to READ Mode.
Flag Bit (DQ5, see Figure 8).
The Error Flag Bit (DQ5) is set if either an internal Figure 8. Data Toggle Flowchart
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU at-
START
tempted to program a '1' to a bit that was not
erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read READ
the location again after the embedded program- DQ5 & DQ6
ming algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written. DQ6
= NO
When using the Data Toggle method after an TOGGLE
Erase cycle, Figure 8 still applies. the Toggle Flag YES
Bit (DQ6) toggles until the Erase cycle is complete.
A '1' on the Error Flag Bit (DQ5) indicates a time-
out condition on the Erase cycle; a '0' indicates no NO DQ5
error. The MCU can read any location within the =1
sector being erased to get the Toggle Flag Bit YES
(DQ6) and the Error Flag Bit (DQ5).
PSDsoft Express generates ANSI C code func- READ DQ6
tions which implement these Data Toggling algo-
rithms.
DQ6 NO
Unlock Bypass (PSD833F2x, PSD834F2x, =
TOGGLE
PSD853F2x, PSD854F2x)
YES
The Unlock Bypass instructions allow the system
to program bytes to the Flash memories faster FAIL PASS
than using the standard Program instruction. The
Unlock Bypass mode is entered by first initiating
two Unlock cycles. This is followed by a third AI01370B

WRITE cycle containing the Unlock Bypass code,

20h (as shown in Table 9., page 21).

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

ERASING FLASH MEMORY

Flash Bulk Erase
The Flash Bulk Erase instruction uses six WRITE During execution of the Erase cycle, the Flash
operations followed by a READ operation of the memory accepts only Reset and Suspend Sector
status register, as described in Table 9., page 21. Erase instructions. Erasure of one Flash memory
If any byte of the Bulk Erase instruction is wrong, sector may be suspended, in order to read data
the Bulk Erase instruction aborts and the device is from another Flash memory sector, and then re-
reset to the Read Flash memory status. sumed.
During a Bulk Erase, the memory status may be Suspend Sector Erase
checked by reading the Error Flag Bit (DQ5), the When a Sector Erase cycle is in progress, the Sus-
Toggle Flag Bit (DQ6), and the Data Polling Flag pend Sector Erase instruction can be used to sus-
Bit (DQ7), as detailed in the section entitled PRO- pend the cycle by writing 0B0h to any address
GRAMMING FLASH MEMORY, page 25. The Er- when an appropriate Sector Select (FS0-FS7 or
ror Flag Bit (DQ5) returns a '1' if there has been an CSBOOT0-CSBOOT3) is High. (See Table
Erase Failure (maximum number of Erase cycles 9., page 21). This allows reading of data from an-
have been executed). other Flash memory sector after the Erase cycle
It is not necessary to program the memory with has been suspended. Suspend Sector Erase is
00h because the PSD automatically does this be- accepted only during an Erase cycle and defaults
fore erasing to 0FFh. to READ Mode. A Suspend Sector Erase instruc-
During execution of the Bulk Erase instruction, the tion executed during an Erase time-out period, in
Flash memory does not accept any instructions. addition to suspending the Erase cycle, terminates
the time out period.
Flash Sector Erase
The Toggle Flag Bit (DQ6) stops toggling when the
The Sector Erase instruction uses six WRITE op- PSD internal logic is suspended. The status of this
erations, as described in Table 9., page 21. Addi-
bit must be monitored at an address within the
tional Flash Sector Erase codes and Flash
Flash memory sector being erased. The Toggle
memory sector addresses can be written subse- Flag Bit (DQ6) stops toggling between 0.1µs and
quently to erase other Flash memory sectors in 15µs after the Suspend Sector Erase instruction
parallel, without further coded cycles, if the addi-
has been executed. The PSD is then automatically
tional bytes are transmitted in a shorter time than
set to READ Mode.
the time-out period of about 100µs. The input of a
new Sector Erase code restarts the time-out peri- If an Suspend Sector Erase instruction was exe-
od. cuted, the following rules apply:
The status of the internal timer can be monitored – Attempting to read from a Flash memory
through the level of the Erase Time-out Flag Bit sector that was being erased outputs invalid
(DQ3). If the Erase Time-out Flag Bit (DQ3) is ’0,’ data.
the Sector Erase instruction has been received – Reading from a Flash sector that was not
and the time-out period is counting. If the Erase being erased is valid.
Time-out Flag Bit (DQ3) is '1,' the time-out period – The Flash memory cannot be programmed,
has expired and the PSD is busy erasing the Flash and only responds to Resume Sector Erase
memory sector(s). Before and during Erase time- and Reset Flash instructions (READ is an
out, any instruction other than Suspend Sector operation and is allowed).
Erase and Resume Sector Erase instructions
– If a Reset Flash instruction is received, data in
abort the cycle that is currently in progress, and re-
set the device to READ Mode. It is not necessary the Flash memory sector that was being
erased is invalid.
to program the Flash memory sector with 00h as
the PSD does this automatically before erasing Resume Sector Erase
(byte = FFh). If a Suspend Sector Erase instruction was previ-
During a Sector Erase, the memory status may be ously executed, the erase cycle may be resumed
checked by reading the Error Flag Bit (DQ5), the with this instruction. The Resume Sector Erase in-
Toggle Flag Bit (DQ6), and the Data Polling Flag struction consists of writing 030h to any address
Bit (DQ7), as detailed in the section entitled PRO- while an appropriate Sector Select (FS0-FS7 or
GRAMMING FLASH MEMORY, page 25. CSBOOT0-CSBOOT3) is High. (See Table
9., page 21.)

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SPECIFIC FEATURES
Flash Memory Sector Protect
Each primary and secondary Flash memory sector On the PSD813F2/3/4/5, the Reset Flash instruc-
can be separately protected against Program and tion puts the Flash memory back into normal
Erase cycles. Sector Protection provides addition- READ Mode. It may take the Flash memory up to
al data security because it disables all Program or a few milliseconds to complete the Reset cycle.
Erase cycles. This mode can be activated through The Reset Flash instruction is ignored when it is is-
the JTAG Port or a Device Programmer. sued during a Program or Bulk Erase cycle of the
Sector protection can be selected for each sector Flash memory. The Reset Flash instruction aborts
using the PSDsoft Express Configuration pro- any on-going Sector Erase cycle, and returns the
gram. This automatically protects selected sectors Flash memory to the normal READ Mode within a
when the device is programmed through the JTAG few milliseconds.
Port or a Device Programmer. Flash memory sec- On the PSD83xF2 or PSD85xF2, the Reset Flash
tors can be unprotected to allow updating of their instruction puts the Flash memory back into nor-
contents using the JTAG Port or a Device Pro- mal READ Mode. If an Error condition has oc-
grammer. The MCU can read (but cannot change) curred (and the device has set the Error Flag Bit
the sector protection bits. (DQ5) to '1') the Flash memory is put back into nor-
Any attempt to program or erase a protected Flash mal READ Mode within 25µs of the Reset Flash in-
memory sector is ignored by the device. The Verify struction having been issued. The Reset Flash
operation results in a READ of the protected data. instruction is ignored when it is issued during a
This allows a guarantee of the retention of the Pro- Program or Bulk Erase cycle of the Flash memory.
tection status. The Reset Flash instruction aborts any on-going
Sector Erase cycle, and returns the Flash memory
The sector protection status can be read by the
to the normal READ Mode within 25µs.
MCU through the Flash memory protection and
PSD/EE protection registers (in the CSIOP block). Reset (RESET) Signal (on the PSD83xF2 and
See Tables 11 and 12. PSD85xF2)
Reset Flash A pulse on Reset (RESET) aborts any cycle that is
in progress, and resets the Flash memory to the
The Reset Flash instruction consists of one
READ Mode. When the reset occurs during a Pro-
WRITE cycle (see Table 9., page 21). It can also
gram or Erase cycle, the Flash memory takes up
be optionally preceded by the standard two to 25µs to return to the READ Mode. It is recom-
WRITE decoding cycles (writing AAh to 555h and
mended that the Reset (RESET) pulse (except for
55h to AAAh). It must be executed after:
Power On Reset, as described on RESET TIMING
– Reading the Flash Protection Status or Flash AND DEVICE STATUS AT RESET, page 67) be
ID at least 25µs so that the Flash memory is always
– An Error condition has occurred (and the ready for the MCU to fetch the bootstrap instruc-
device has set the Error Flag Bit (DQ5) to '1') tions after the Reset cycle is complete.
during a Flash memory Program or Erase
cycle.

Table 11. Sector Protection/Security Bit Definition – Flash Protection Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Note: 1. Bit Definitions:
Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Primary Flash memory or secondary Flash memory Sector <i> is not write protected.

Table 12. Sector Protection/Security Bit Definition – PSD/EE Protection Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Security_Bit not used not used not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Note: 1. Bit Definitions:
Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

SRAM
The SRAM is enabled when SRAM Select (RS0) PC4 can be configured as an output that indicates
from the DPLD is High. SRAM Select (RS0) can when power is being drawn from the external bat-
contain up to two product terms, allowing flexible tery. Battery-on Indicator (VBATON, PC4) is High
memory mapping. with the supply voltage falls below the battery volt-
The SRAM can be backed up using an external age and the battery on Voltage Stand-by (VSTBY,
battery. The external battery should be connected PC2) is supplying power to the internal SRAM.
to Voltage Stand-by (VSTBY, PC2). If you have an SRAM Select (RS0), Voltage Stand-by (VSTBY,
external battery connected to the PSD, the con- PC2) and Battery-on Indicator (VBATON, PC4)
tents of the SRAM are retained in the event of a are all configured using PSDsoft Express Configu-
power loss. The contents of the SRAM are re- ration.
tained so long as the battery voltage remains at
2 V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.

29/110
PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

SECTOR SELECT AND SRAM SELECT

Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) This is controlled through manipulation of the VM
and SRAM Select (RS0) are all outputs of the register that resides in the CSIOP space.
DPLD. They are setup by writing equations for The VM register is set using PSDsoft Express to
them in PSDabel. The following rules apply to the have an initial value. It can subsequently be
equations for these signals: changed by the MCU so that memory mapping
1. Primary Flash memory and secondary Flash can be changed on-the-fly.
memory Sector Select signals must not be For example, you may wish to have SRAM and pri-
larger than the physical sector size. mary Flash memory in the Data space at Boot-up,
2. Any primary Flash memory sector must not be and secondary Flash memory in the Program
mapped in the same memory space as space at Boot-up, and later swap the primary and
another Flash memory sector. secondary Flash memories. This is easily done
3. A secondary Flash memory sector must not be with the VM register by using PSDsoft Express
mapped in the same memory space as Configuration to configure it for Boot-up and hav-
another secondary Flash memory sector. ing the MCU change it when desired. Table
13., page 31 describes the VM Register.
4. SRAM, I/O, and Peripheral I/O spaces must
not overlap.
5. A secondary Flash memory sector may Figure 9. Priority Level of Memory and I/O
overlap a primary Flash memory sector. In Components
case of overlap, priority is given to the
secondary Flash memory sector.
6. SRAM, I/O, and Peripheral I/O spaces may Highest Priority
overlap any other memory sector. Priority is
given to the SRAM, I/O, or Peripheral I/O.
Example Level 1
SRAM, I /O, or
FS0 is valid when the address is in the range of Peripheral I /O
8000h to BFFFh, CSBOOT0 is valid from 8000h to Level 2
9FFFh, and RS0 is valid from 8000h to 87FFh. Secondary
Non-Volatile Memory
Any address in the range of RS0 always accesses
the SRAM. Any address in the range of CSBOOT0 Level 3
greater than 87FFh (and less than 9FFFh) auto- Primary Flash Memory
matically addresses secondary Flash memory Lowest Priority AI02867D
segment 0. Any address greater than 9FFFh ac-
cesses the primary Flash memory segment 0. You
can see that half of the primary Flash memory seg-
ment 0 and one-fourth of secondary Flash memory Configuration Modes for MCUs with Separate
segment 0 cannot be accessed in this example.
Program and Data Spaces
Also note that an equation that defined FS1 to any-
where in the range of 8000h to BFFFh would not Separate Space Modes. Program space is sep-
be valid. arated from Data space. For example, Program
Select Enable (PSEN, CNTL2) is used to access
Figure 9 shows the priority levels for all memory
the program code from the primary Flash memory,
components. Any component on a higher level can
while Read Strobe (RD, CNTL1) is used to access
overlap and has priority over any component on a data from the secondary Flash memory, SRAM
lower level. Components on the same level must and I/O Port blocks. This configuration requires
not overlap. Level one has the highest priority and
the VM register to be set to 0Ch (see Figure
level 3 has the lowest.
10., page 31).
Memory Select Configuration for MCUs with
Combined Space Modes. The Program and
Separate Program and Data Spaces Data spaces are combined into one memory
The 8031 and compatible family of MCUs, which space that allows the primary Flash memory, sec-
includes the 80C51, 80C151, 80C251, and ondary Flash memory, and SRAM to be accessed
80C51XA, have separate address spaces for Pro- by either Program Select Enable (PSEN, CNTL2)
gram memory (selected using Program Select En- or Read Strobe (RD, CNTL1). For example, to
able (PSEN, CNTL2)) and Data memory (selected configure the primary Flash memory in Combined
using Read Strobe (RD, CNTL1)). Any of the space, Bits b2 and b4 of the VM register are set to
memories within the PSD can reside in either '1' (see Figure 11., page 31).
space or both spaces.

30/110
 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Figure 10. 8031 Memory Modules – Separate Space

DPLD RS0 Primary Secondary SRAM

Flash Flash
Memory Memory
CSBOOT0-3

FS0-FS7
CS CS CS
OE OE OE

PSEN

RD
AI02869C

Figure 11. 8031 Memory Modules – Combined Space

DPLD RS0 Primary Secondary SRAM

Flash Flash
Memory Memory
RD CSBOOT0-3

FS0-FS7
CS CS CS
OE OE OE

VM REG BIT 3

VM REG BIT 4

PSEN

VM REG BIT 1

VM REG BIT 2 RD

VM REG BIT 0
AI02870C

Table 13. VM Register

Bit 4 Bit 3 Bit 2 Bit 1
Bit 7 Bit 0
Bit 6 Bit 5 Primary Secondary Primary Secondary
PIO_EN SRAM_Code
FL_Data EE_Data FL_Code EE_Code
0 = RD can’t 0 = PSEN 0 = PSEN can’t
0 = RD 0 = PSEN
0 = disable not not access can’t access access
can’t access can’t access
PIO mode used used Secondary Flash Flash Secondary Flash
Flash memory SRAM
memory memory memory
1 = PSEN
1 = RD 1 = RD access 1 = PSEN access 1 = PSEN
1= enable not not access
access Flash Secondary Flash Secondary Flash access
PIO mode used used Flash
memory memory memory SRAM
memory

31/110
PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

PAGE REGISTER
The 8-bit Page Register increases the addressing If memory paging is not needed, or if not all 8 page
capability of the MCU by a factor of up to 256. The register bits are needed for memory paging, then
contents of the register can also be read by the these bits may be used in the CPLD for general
MCU. The outputs of the Page Register (PGR0- logic. See Application Note AN1154.
PGR7) are inputs to the DPLD decoder and can be Figure 12 shows the Page Register. The eight flip-
included in the Sector Select (FS0-FS7, flops in the register are connected to the internal
CSBOOT0-CSBOOT3), and SRAM Select (RS0) data bus D0-D7. The MCU can write to or read
equations. from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.

Figure 12. Page Register

RESET

PGR0 INTERNAL
D0 Q0
PGR1 SELECTS
D1 Q1 AND LOGIC
D0 - D7 PGR2
D2 Q2
PGR3 DPLD
D3 Q3 AND
PGR4 CPLD
D4 Q4
PGR5
D5 Q5
PGR6
D6 Q6
PGR7
R/W D7 Q7

PAGE PLD
REGISTER AI02871B

32/110
 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

PLDS
The PLDs bring programmable logic functionality Additionally, five bits are available in PMMR2 to
to the PSD. After specifying the logic for the PLDs block MCU control signals from entering the PLDs.
using the PSDabel tool in PSDsoft Express, the This reduces power consumption and can be used
logic is programmed into the device and available only when these MCU control signals are not used
upon Power-up. in PLD logic equations.
The PSD contains two PLDs: the Decode PLD Each of the two PLDs has unique characteristics
(DPLD), and the Complex PLD (CPLD). The PLDs suited for its applications. They are described in
are briefly discussed in the next few paragraphs, the following sections.
and in more detail in the section entitled Decode
PLD (DPLD), page 35 and the section entitled Table 14. DPLD and CPLD Inputs
Complex PLD (CPLD), page 36. Figure
13., page 34 shows the configuration of the PLDs. Number
Input Source Input Name of
The DPLD performs address decoding for Select
Signals
signals for internal components, such as memory,
registers, and I/O ports. MCU Address Bus1 A15-A0 16
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma- MCU Control Signals CNTL2-CNTL0 3
chines, and encoding and decoding logic. These Reset RST 1
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells Power-down PDN 1
(IMC), and the AND Array. The CPLD can also be Port A Input
used to generate External Chip Select (ECS0- PA7-PA0 8
Macrocells
ECS2) signals.
The AND Array is used to form product terms. Port B Input
PB7-PB0 8
Macrocells
These product terms are specified using PSDabel.
An Input Bus consisting of 73 signals is connected Port C Input
to the PLDs. The signals are shown in Table 14. PC7-PC0 8
Macrocells
The Turbo Bit in PSD Port D Inputs PD2-PD0 3
The PLDs in the PSD can minimize power con-
sumption by switching off when inputs remain un- Page Register PGR7-PGR0 8
changed for an extended time of about 70ns. Macrocell AB MCELLAB.FB7-
Resetting the Turbo Bit to '0' (Bit 3 of PMMR0) au- 8
Feedback FB0
tomatically places the PLDs into standby if no in-
puts are changing. Turning the Turbo mode off Macrocell BC MCELLBC.FB7-
8
increases propagation delays while reducing pow- Feedback FB0
er consumption. See the section entitled POWER Secondary Flash
MANAGEMENT, page 62 on how to set the Turbo memory Program Ready/Busy 1
Bit. Status Bit
Note: 1. The address inputs are A19-A4 in 80C51XA mode.

33/110
34/110
8
DATA PAGE
BUS REGISTER
Figure 13. PLD Diagram

8
DECODE PLD PRIMARY FLASH MEMORY SELECTS
73
4
SECONDARY NON-VOLATILE MEMORY SELECTS
1
SRAM SELECT
1
CSIOP SELECT
2
PERIPHERAL SELECTS
1
JTAG SELECT

16 OUTPUT MACROCELL FEEDBACK DIRECT MACROCELL ACCESS FROM MCU DATA BUS

PLD INPUT BUS

CPLD 16 OUTPUT MCELLAB
PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

MACROCELL TO PORT A OR B 8
MACROCELL
PT ALLOC.
73 ALLOC. MCELLBC
TO PORT B OR C 8
24 INPUT MACROCELL
(PORT A,B,C)
3
I/O PORTS

EXTERNAL CHIP SELECTS

TO PORT D

DIRECT MACROCELL INPUT TO MCU DATA BUS

24 INPUT MACROCELL & INPUT PORTS

3 PORT D INPUTS

AI02872C
 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Decode PLD (DPLD)

The DPLD, shown in Figure 14, is used for decod- ■ 1 internal SRAM Select (RS0) signal (two
ing the address for internal and external compo- product terms)
nents. The DPLD can be used to generate the ■ 1 internal CSIOP Select (PSD Configuration
following decode signals: Register) signal
■ 8 Sector Select (FS0-FS7) signals for the ■ 1 JTAG Select signal (enables JTAG on Port
primary Flash memory (three product terms C)
each)
■ 2 internal Peripheral Select signals
■ 4 Sector Select (CSBOOT0-CSBOOT3) (Peripheral I/O mode).
signals for the secondary Flash memory (three
product terms each)

Figure 14. DPLD Logic Array

3 CSBOOT 0

3 CSBOOT 1

3 CSBOOT 2

3 CSBOOT 3

(INPUTS) 3
FS0
I /O PORTS (PORT A,B,C) (24)
3
FS1
MCELLAB.FB [7:0] (FEEDBACKS) (8)
3
FS2
MCELLBC.FB [7:0] (FEEDBACKS) (8)
3
FS3 8 PRIMARY FLASH
PGR0 - PGR7 (8)
3 MEMORY SECTOR SELECTS
FS4
A[15:0] * (16)
3
FS5
PD[2:0] (ALE,CLKIN,CSI) (3)
3
FS6
PDN (APD OUTPUT) (1)
3
FS7
CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) (3)

RESET (1)
2 RS0
SRAM SELECT
RD_BSY (1)
1 CSIOP I/O DECODER
SELECT
1 PSEL0
PERIPHERAL I/O MODE
1 PSEL1 SELECT

1 JTAGSEL

AI02873D

35/110
PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Complex PLD (CPLD)

The CPLD can be used to implement system logic ■ Product Term Allocator
functions, such as loadable counters and shift reg- ■ AND Array capable of generating up to 137
isters, system mailboxes, handshaking protocols, product terms
state machines, and random logic. The CPLD can
also be used to generate three External Chip Se- ■ Four I/O Ports.
lect (ECS0-ECS2), routed to Port D. Each of the blocks are described in the sections
that follow.
Although External Chip Select (ECS0-ECS2) can
be produced by any Output Macrocell (OMC), The Input Macrocells (IMC) and Output Macrocells
these three External Chip Select (ECS0-ECS2) on (OMC) are connected to the PSD internal data bus
Port D do not consume any Output Macrocells and can be directly accessed by the MCU. This
(OMC). enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
As shown in Figure 13., page 34, the CPLD has
the following blocks: the Input and Output Macrocells (IMC and OMC).
■ 24 Input Macrocells (IMC) This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
■ 16 Output Macrocells (OMC) data bus to the AND Array as required in most
■ Macrocell Allocator standard PLD macrocell architectures.

Figure 15. Macrocell and I/O Port

PRODUCT TERMS MCU ADDRESS / DATA BUS
PLD INPUT BUS

FROM OTHER
MACROCELLS
TO OTHER I/O PORTS

CPLD MACROCELLS I/O PORTS

DATA
LOAD LATCHED
PT PRESET CONTROL
MCU DATA IN ADDRESS OUT
PRODUCT TERM
ALLOCATOR I/O PIN
MCU LOAD DATA
D Q
MUX
WR
UP TO 10
AND ARRAY

PRODUCT TERMS
MACROCELL CPLD OUTPUT
OUT TO
MCU
POLARITY
MUX

SELECT
PR DI LD
D/T Q SELECT
PT
CLOCK CPLD PDR
D/T/JK FF COMB. OUTPUT INPUT
SELECT /REG
MUX

GLOBAL
PLD INPUT BUS

CLOCK SELECT
CK MACROCELL
TO
CL I/O PORT
CLOCK ALLOC. D Q
SELECT DIR
WR REG.
PT CLEAR

PT OUTPUT ENABLE (OE)

MACROCELL FEEDBACK INPUT MACROCELLS

I/O PORT INPUT
MUX

Q D

PT INPUT LATCH GATE/CLOCK

Q D
MUX

ALE/AS G

AI02874

36/110
 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Output Macrocell (OMC)

Eight of the Output Macrocells (OMC) are con- trolled by the XOR gate. The Output Macrocell
nected to Ports A and B pins and are named as (OMC) can implement either sequential logic, us-
McellAB0-McellAB7. The other eight macrocells ing the flip-flop element, or combinatorial logic.
are connected to Ports B and C pins and are The multiplexer selects between the sequential or
named as McellBC0-McellBC7. If an McellAB out- combinatorial logic outputs. The multiplexer output
put is not assigned to a specific pin in PSDabel, can drive a port pin and has a feedback path to the
the Macrocell Allocator block assigns it to either AND Array inputs.
Port A or B. The same is true for a McellBC output The flip-flop in the Output Macrocell (OMC) block
on Port B or C. Table 15 shows the macrocells and can be configured as a D, T, JK, or SR type in the
port assignment. PSDabel program. The flip-flop’s clock, preset,
The Output Macrocell (OMC) architecture is and clear inputs may be driven from a product
shown in Figure 16., page 39. As shown in the fig- term of the AND Array. Alternatively, CLKIN (PD1)
ure, there are native product terms available from can be used for the clock input to the flip-flop. The
the AND Array, and borrowed product terms avail- flip-flop is clocked on the rising edge of CLKIN
able (if unused) from other Output Macrocells (PD1). The preset and clear are active High inputs.
(OMC). The polarity of the product term is con- Each clear input can use up to two product terms.

Table 15. Output Macrocell Port and Data Bit Assignments

Output Port Maximum Borrowed Data Bit for Loading or
Native Product Terms
Macrocell Assignment Product Terms Reading
McellAB0 Port A0, B0 3 6 D0
McellAB1 Port A1, B1 3 6 D1
McellAB2 Port A2, B2 3 6 D2
McellAB3 Port A3, B3 3 6 D3
McellAB4 Port A4, B4 3 6 D4
McellAB5 Port A5, B5 3 6 D5
McellAB6 Port A6, B6 3 6 D6
McellAB7 Port A7, B7 3 6 D7
McellBC0 Port B0, C0 4 5 D0
McellBC1 Port B1, C1 4 5 D1
McellBC2 Port B2, C2 4 5 D2
McellBC3 Port B3, C3 4 5 D3
McellBC4 Port B4, C4 4 6 D4
McellBC5 Port B5, C5 4 6 D5
McellBC6 Port B6, C6 4 6 D6
McellBC7 Port B7, C7 4 6 D7

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Product Term Allocator

The CPLD has a Product Term Allocator. The PS- Data can be loaded to the Output Macrocells
Dabel compiler uses the Product Term Allocator to (OMC) on the trailing edge of Write Strobe (WR,
borrow and place product terms from one macro- CNTL0) (edge loading) or during the time that
cell to another. The following list summarizes how Write Strobe (WR, CNTL0) is active (level load-
product terms are allocated: ing). The method of loading is specified in PSDsoft
■ McellAB0-McellAB7 all have three native Express Configuration.
product terms and may borrow up to six more The OMC Mask Register
■ McellBC0-McellBC3 all have four native There is one Mask Register for each of the two
product terms and may borrow up to five more groups of eight Output Macrocells (OMC). The
■ McellBC4-McellBC7 all have four native Mask Registers can be used to block the loading
product terms and may borrow up to six more. of data to individual Output Macrocells (OMC).
The default value for the Mask Registers is 00h,
Each macrocell may only borrow product terms which allows loading of the Output Macrocells
from certain other macrocells. Product terms al- (OMC). When a given bit in a Mask Register is set
ready in use by one macrocell are not available for
to a 1, the MCU is blocked from writing to the as-
another macrocell.
sociated Output Macrocells (OMC). For example,
If an equation requires more product terms than suppose McellAB0-McellAB3 are being used for a
are available to it, then “external” product terms state machine. You would not want a MCU write to
are required, which consume other Output Macro- McellAB to overwrite the state machine registers.
cells (OMC). If external product terms are used, Therefore, you would want to load the Mask Reg-
extra delay is added for the equation that required ister for McellAB (Mask Macrocell AB) with the val-
the extra product terms. ue 0Fh.
This is called product term expansion. PSDsoft The Output Enable of the OMC
Express performs this expansion as needed.
The Output Macrocells (OMC) block can be con-
Loading and Reading the Output Macrocells nected to an I/O port pin as a PLD output. The out-
(OMC) put enable of each port pin driver is controlled by
The Output Macrocells (OMC) block occupies a a single product term from the AND Array, ORed
memory location in the MCU address space, as with the Direction Register output. The pin is en-
defined by the CSIOP block (see the section enti- abled upon Power-up if no output enable equation
tled I/O PORTS, page 51). The flip-flops in each of is defined and if the pin is declared as a PLD out-
the 16 Output Macrocells (OMC) can be loaded put in PSDsoft Express.
from the data bus by a MCU. Loading the Output If the Output Macrocell (OMC) output is declared
Macrocells (OMC) with data from the MCU takes as an internal node and not as a port pin output in
priority over internal functions. As such, the preset, the PSDabel file, the port pin can be used for other
clear, and clock inputs to the flip-flop can be over- I/O functions. The internal node feedback can be
ridden by the MCU. The ability to load the flip-flops routed as an input to the AND Array.
and read them back is useful in such applications
as loadable counters and shift registers, mailbox-
es, and handshaking protocols.

38/110
 MASK
REG.

MACROCELL CS INTERNAL DATA BUS D [ 7:0]

RD

WR
PT DIRECTION
ALLOCATOR REGISTER
Figure 16. CPLD Output Macrocell

ENABLE (.OE)

PRESET(.PR) COMB/REG
SELECT
PT

PT
DIN PR

AND ARRAY
MUX I/O PIN
LD MACROCELL
PT Q ALLOCATOR
POLARITY
SELECT IN
PORT
DRIVER
CLR

PLD INPUT BUS

CLEAR (.RE)
PROGRAMMABLE
FF (D/T/JK /SR)
PT CLK

CLKIN MUX

FEEDBACK (.FB)

PORT INPUT INPUT

MACROCELL

AI02875B
PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

39/110
PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Input Macrocells (IMC)

The CPLD has 24 Input Macrocells (IMC), one for Input Macrocells (IMC) can use Address Strobe
each pin on Ports A, B, and C. The architecture of (ALE/AS, PD0) to latch address bits higher than
the Input Macrocells (IMC) is shown in Figure A15. Any latched addresses are routed to the
17., page 41. The Input Macrocells (IMC) are indi- PLDs as inputs.
vidually configurable, and can be used as a latch, Input Macrocells (IMC) are particularly useful with
register, or to pass incoming Port signals prior to handshaking communication applications where
driving them onto the PLD input bus. The outputs two processors pass data back and forth through
of the Input Macrocells (IMC) can be read by the a common mailbox. Figure 18., page 42 shows a
MCU through the internal data bus. typical configuration where the Master MCU writes
The enable for the latch and clock for the register to the Port A Data Out Register. This, in turn, can
are driven by a multiplexer whose inputs are a be read by the Slave MCU via the activation of the
product term from the CPLD AND Array or the “Slave-Read” output enable product term.
MCU Address Strobe (ALE/AS). Each product The Slave can also write to the Port A Input Mac-
term output is used to latch or clock four Input rocells (IMC) and the Master can then read the In-
Macrocells (IMC). Port inputs 3-0 can be con- put Macrocells (IMC) directly.
trolled by one product term and 7-4 by another.
Note that the “Slave-Read” and “Slave-Wr” signals
Configurations for the Input Macrocells (IMC) are are product terms that are derived from the Slave
specified by equations written in PSDabel (see Ap- MCU inputs Read Strobe (RD, CNTL1), Write
plication Note AN1171). Outputs of the Input Mac- Strobe (WR, CNTL0), and Slave_CS.
rocells (IMC) can be read by the MCU via the IMC
buffer. See the section entitled I/O
PORTS, page 51.

40/110
 INTERNAL DATA BUS D [ 7:0]
Figure 17. Input Macrocell

INPUT MACROCELL _ RD DIRECTION

REGISTER
ENABLE ( .OE )

OUTPUT
PT MACROCELLS BC
AND
MACROCELL AB

I/O PIN

AND ARRAY
PT
PORT
DRIVER

PLD INPUT BUS

MUX Q D PT

MUX ALE/AS
D FF

FEEDBACK Q D

G
LATCH
INPUT MACROCELL

AI02876B
PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

41/110
42/110
PSD
SLAVE– CS
RD
WR

SLAVE–READ

PORT A
DATA OUT SLAVE
REGISTER MCU
CPLD D [ 7:0]
MCU- RD D Q
PORT A
MCU-WR
MCU- WR
MASTER
MCU
SLAVE–WR
PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

D [ 7:0]
PORT A
INPUT
MACROCELL
Figure 18. Handshaking Communication Using Input Macrocells

Q D

MCU-RD

AI02877C
 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

MCU BUS INTERFACE

The “no-glue logic” MCU Bus Interface block can bus types and control signals, are shown in Table
be directly connected to most popular MCUs and 16. The interface type is specified using the PSD-
their control signals. Key 8-bit MCUs, with their soft Express Configuration.

Table 16. MCUs and their Control Signals

Data Bus
MCU
Width
CNTL0 CNTL1 CNTL2 PC7 PD02 ADIO0 PA3-PA0 PA7-PA3

8031 8 WR RD PSEN (Note 1) ALE A0 (Note 1) (Note 1)

80C51XA 8 WR RD PSEN (Note 1) ALE A4 A3-A0 (Note 1)

80C251 8 WR PSEN (Note 1) (Note 1) ALE A0 (Note 1) (Note 1)

80C251 8 WR RD PSEN (Note 1) ALE A0 (Note 1) (Note 1)

80198 8 WR RD (Note 1) (Note 1) ALE A0 (Note 1) (Note 1)

68HC11 8 R/W E (Note 1) (Note 1) AS A0 (Note 1) (Note 1)

68HC912 8 R/W E (Note 1) DBE AS A0 (Note 1) (Note 1)

Z80 8 WR RD (Note 1) (Note 1) (Note 1) A0 D3-D0 D7-D4

Z8 8 R/W DS (Note 1) (Note 1) AS A0 (Note 1) (Note 1)

68330 8 R/W DS (Note 1) (Note 1) AS A0 (Note 1) (Note 1)

M37702M2 8 R/W E (Note 1) (Note 1) ALE A0 D3-D0 D7-D4

Note: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be configured for other I/O func-
tions.
2. ALE/AS input is optional for MCUs with a non-multiplexed bus

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

PSD Interface to a Multiplexed 8-Bit Bus

Figure 19 shows an example of a system using a B. The PSD drives the ADIO data bus only when
MCU with an 8-bit multiplexed bus and a PSD. The one of its internal resources is accessed and Read
ADIO port on the PSD is connected directly to the Strobe (RD, CNTL1) is active. Should the system
MCU address/data bus. Address Strobe (ALE/AS, address bus exceed sixteen bits, Ports A, B, C, or
PD0) latches the address signals internally. D may be used as additional address inputs.
Latched addresses can be brought out to Port A or

Figure 19. An Example of a Typical 8-bit Multiplexed Bus Interface

MCU PSD
AD [ 7:0] A [ 7: 0]
PORT
A (OPTIONAL)
ADIO
PORT
A[ 15:8]
PORT A [ 15: 8]
B (OPTIONAL)
WR WR (CNTRL0)
RD RD (CNTRL1)
BHE BHE (CNTRL2) PORT
C
RST

ALE ALE (PD0)

PORT D

RESET
AI02878C

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

PSD Interface to a Non-Multiplexed 8-Bit Bus MCU Bus Interface Examples

Figure 20 shows an example of a system using a Figure 21 through 25 show examples of the basic
MCU with an 8-bit non-multiplexed bus and a connections between the PSD and some popular
PSD. The address bus is connected to the ADIO MCUs. The PSD Control input pins are labeled as
Port, and the data bus is connected to Port A. Port to the MCU function for which they are configured.
A is in tri-state mode when the PSD is not access- The MCU bus interface is specified using the PS-
ed by the MCU. Should the system address bus Dsoft Express Configuration.
exceed sixteen bits, Ports B, C, or D may be used
for additional address inputs. Table 17. Eight-Bit Data Bus
Data Byte Enable Reference
BHE A0 D7-D0
MCUs have different data byte orientations. Table
17 shows how the PSD interprets byte/word oper- X 0 Even Byte
ations in different bus WRITE configurations.
X 1 Odd Byte
Even-byte refers to locations with address A0
equal to '0' and odd byte as locations with A0 equal
to ’1.’

Figure 20. An Example of a Typical 8-bit Non-Multiplexed Bus Interface

MCU PSD

D [ 7:0] D [ 7:0]
PORT
ADIO A
PORT
A [ 15:0]
PORT A[ 23:16]
B
(OPTIONAL)
WR WR (CNTRL0)
RD RD (CNTRL1)
BHE BHE (CNTRL2) PORT
RST C

ALE ALE (PD0)

PORT D

RESET

AI02879C

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

80C31
Figure 21 shows the bus interface for the 80C31, CNTL1), and Write Strobe (WR, CNTL0) may be
which has an 8-bit multiplexed address/data bus. used for accessing the internal memory and I/O
The lower address byte is multiplexed with the Ports blocks. Address Strobe (ALE/AS, PD0)
data bus. The MCU control signals Program Se- latches the address.
lect Enable (PSEN, CNTL2), Read Strobe (RD,

Figure 21. Interfacing the PSD with an 80C31

AD7-AD0
AD[ 7:0 ]

80C31 PSD
AD0 30 29
31 31 ADIO0 PA0
39 AD0 AD1 28
EA/VP P0.0 ADIO1 PA1
38 AD1 AD2 32 27
19 P0.1 ADIO2 PA2
X1 37 AD2 AD3 33 25
P0.2 34 ADIO3 PA3
36 AD3 AD4 24
18 P0.3 ADIO4 PA4
X2 35 AD4 AD5 35 23
P0.4 ADIO5 PA5
34 AD5 AD6 36 22
P0.5 ADIO6 PA6
9 33 AD6 AD7 37 21
RESET RESET P0.6 ADIO7 PA7
32 AD7
P0.7
12
INT0 21 A8 39 7
13 P2.0 ADIO8 PB0
INT1 22 A9 40 6
14 P2.1 ADIO9 PB1
T0 23 A10 41 5
15 P2.2 ADIO10 PB2
T1 24 A11 42
P2.3 ADIO11 4
25 A12 43 PB3
P2.4 ADIO12 3
1 26 A13 44 PB4
P1.0 P2.5 ADIO13 2
2 27 A14 45 PB5
P1.1 P2.6 ADIO14 52
3 28 A15 46 PB6
P1.2 P2.7 ADIO15 51
4 PB7
P1.3 17 RD
5 RD
P1.4
6 16 WR 47 20
P1.5 WR CNTL0 (WR) PC0
7 29 PSEN 50 19
P1.6 PSEN CNTL1(RD) PC1
8 18
P1.7 30 ALE PC2
ALE/P 49 17
11 CNTL2 (PSEN) PC3
TXD 14
PC4
10 10 13
RXD PD0-ALE PC5
12
9 PC6
PD1 11
8 PC7
PD2

RESET 48
RESET RESET

AI02880C

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

80C251
The Intel 80C251 MCU features a user-config- The 80C251 has two major operating modes:
urable bus interface with four possible bus config- Page mode and Non-page mode. In Non-page
urations, as shown in Table 18., page 48. mode, the data is multiplexed with the lower ad-
The first configuration is 80C31-compatible, and dress byte, and Address Strobe (ALE/AS, PD0) is
the bus interface to the PSD is identical to that active in every bus cycle. In Page mode, data (D7-
shown in Figure 21., page 46. The second and D0) is multiplexed with address (A15-A8). In a bus
third configurations have the same bus connection cycle where there is a Page hit, Address Strobe
as shown in Figure 22. There is only one Read (ALE/AS, PD0) is not active and only addresses
Strobe (PSEN) connected to CNTL1 on the PSD. (A7-A0) are changing. The PSD supports both
The A16 connection to PA0 allows for a larger ad- modes. In Page Mode, the PSD bus timing is iden-
dress input to the PSD. The fourth configuration is tical to Non-Page Mode except the address hold
shown in Figure 23., page 48. Read Strobe (RD) is time and setup time with respect to Address
connected to CNTL1 and Program Select Enable Strobe (ALE/AS, PD0) is not required. The PSD
(PSEN) is connected to CNTL2. access time is measured from address (A7-A0)
valid to data in valid.

Figure 22. Interfacing the PSD with the 80C251, with One READ Input

80C251SB PSD
2 43 A0 A0 30
P1.0 P0.0 ADIO0 A161
3 42 A1 A1 31 29
P1.1 P0.1 ADIO1 PA0
4 41 A2 A2 32 28
P1.2 P0.2 ADIO2 PA1
5 P0.3
40 A3 A3 33
ADIO3
27 A171
P1.3 A4
PA2
6 39 A4 34 25
P1.4 P0.4 ADIO4 PA3
7 38 A5 A5 35 24
P1.5 P0.5 ADIO5 PA4
8 37 A6 A6 36 23
P1.6 P0.6 ADIO6 PA5
9 36 A7 A7 37 22
P1.7 P0.7 ADIO7 PA6
21
24 AD8
PA7
21 P2.0
X1 25 AD9 AD8 39
P2.1 ADIO8 7
20 26 AD10 AD9 40
X2 P2.2 ADIO9 PB0 6
27 AD11 AD10 41
P2.3 ADIO10 PB1 5
11 28 AD12 AD11 42
P3.0/RXD P2.4 ADIO11 PB2 4
13 29 AD13 AD12 43 PB3
P3.1/TXD P2.5 ADIO12 3
14 30 AD14 AD13 44 PB4
P3.2/INT0 P2.6 ADIO13 2
15 31 AD15 AD14 45 PB5
P2.7 ADIO14 52
P3.3/INT1 AD15 46 PB6
16 ADIO15
P3.4/T0 51
17 PB7
P3.5/T1 33 ALE 47
ALE CNTL0 ( WR)
10 32 RD 50
RESET RST PSEN CNTL1( RD) 20
18 WR PC0
WR 19
35 19 A16 49 PC1
EA RD/A16 CNTL 2(PSEN) 18
PC2
17
PC3
10 14
PD0-ALE PC4
13
9 PC5
PD1 12
8 PC6
PD2 11
PC7
RESET 48
RESET RESET
AI02881C

Note: 1. The A16 and A17 connections are optional.

2. In non-Page-Mode, AD7-AD0 connects to ADIO7-ADIO0.

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Figure 23. Interfacing the PSD with the 80C251, with RD and PSEN Inputs

80C251SB PSD
2 43 A0 A0 30
P1.0 P0.0 ADIO0
3 42 A1 A1 31 29
P1.1 P0.1 ADIO1 PA0
4 41 A2 A2 32 28
P1.2 P0.2 ADIO2 PA1
5 40 A3 A3 33 27
P1.3 P0.3 ADIO3 PA2
6 39 A4 A4 34 25
P1.4 P0.4 ADIO4 PA3
7 38 A5 A5 35 24
P1.5 P0.5 ADIO5 PA4
8 37 A6 A6 36 23
P1.6 P0.6 ADIO6 PA5
9 36 A7 A7 37 22
P1.7 P0.7 ADIO7 PA6
21
24 AD8
PA7
21 P2.0
X1 25 AD9 AD8 39
P2.1 ADIO8 7
20 26 AD10 AD9 40
X2 P2.2 ADIO9 PB0 6
27 AD11 AD10 41
P2.3 ADIO10 PB1 5
11 28 AD12 AD11 42
P3.0/RXD P2.4 ADIO11 PB2 4
13 29 AD13 AD12 43 PB3
P3.1/TXD P2.5 ADIO12 3
14 30 AD14 AD13 44 PB4
P3.2/INT0 P2.6 ADIO13 2
15 31 AD15 AD14 45 PB5
P3.3/INT1 P2.7 ADIO14 52
16 AD15 46 PB6
P3.4/T0 ADIO15 51
17 PB7
P3.5/T1 33 ALE 47
ALE CNTL0 ( WR)
10 32 RD 50
RESET RST PSEN CNTL1( RD) 20
18 WR PC0
WR 19
35 19 PSEN 49 PC1
EA RD/A16 CNTL 2(PSEN) 18
PC2
17
PC3
10 14
PD0-ALE PC4
13
9 PC5
PD1 12
8 PC6
PD2 11
PC7
RESET 48
RESET RESET

AI02882C

Table 18. 80C251 Configurations

80C251 READ/WRITE
Configuration Connecting to PSD Pins Page Mode
Pins
WR CNTL0
Non-Page Mode, 80C31 compatible A7-
1 RD CNTL1
A0 multiplex with D7-D0
PSEN CNTL2
WR CNTL0 Non-Page Mode
2
PSEN only CNTL1 A7-A0 multiplex with D7-D0
WR CNTL0 Page Mode
3
PSEN only CNTL1 A15-A8 multiplex with D7-D0
WR CNTL0
Page Mode
4 RD CNTL1
A15-A8 multiplex with D7-D0
PSEN CNTL2

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

80C51XA
The Philips 80C51XA MCU family supports an 8- es. In Burst Mode, address A19-A4 are latched
or 16-bit multiplexed bus that can have burst cy- internally by the PSD, while the 80C51XA changes
cles. Address bits (A3-A0) are not multiplexed, the A3-A0 signals to fetch up to 16 bytes of code.
while (A19-A4) are multiplexed with data bits The PSD access time is then measured from ad-
(D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4) dress A3-A0 valid to data in valid. The PSD bus
are multiplexed with data bits (D7-D0). timing requirement in Burst Mode is identical to the
The 80C51XA can be configured to operate in normal bus cycle, except the address setup and
eight-bit data mode (as shown in Figure 24). hold time with respect to Address Strobe (ALE/AS,
PD0) does not apply.
The 80C51XA improves bus throughput and per-
formance by executing burst cycles for code fetch-

Figure 24. Interfacing the PSD with the 80C51X, 8-bit Data Bus

80C51XA PSD
21 2 A0 A4D0 30
XTAL1 A0/WRH ADIO0
20 3 A1 A5D1 31 29 A0
XTAL2 A1 ADIO1 PA0
4 A2 A6D2 32 28 A1
A2 ADIO2 PA1
5 A3 A7D3 33 27 A2
A3 ADIO3 PA2
43 A4D0 A8D4 34 25 A3
11 A4D0 AD104 PA3
RXD0 42 A5D1 A9D5 35 AD105 24
13 A5D1 PA4
TXD0 41 A6D2 A10D6 36 23
6 A6D2 ADIO6 PA5
RXD1 40 A7D3 A11D7 37 22
7 A7D3 ADIO7 PA6
TXD1 39 A8D4 21
A8D4 PA7
38 A9D5
A9D5
37 A10D6 A12 39
9 A10D6 ADIO8 7
T2EX 36 A11D7 A13 40 PB0
8 A11D7 ADIO9 6
T2 24 A12 A14 41 PB1
16 A12D8 ADIO10 5
T0 25 A13 A15 42 PB2
A13D9 ADIO11 4
26 A14 A16 43 PB3
A14D10 AD1012 3
27 A15 A17 44 PB4
A15D11 AD1013 2
10 28 A16 A18 45 PB5
RESET RST A16D12 ADIO14 52
14 29 A17 A19 46 PB6
INT0 A17D13 ADIO15 51
30 A18 PB7
15 A18D14
INT1 31 A19
A19D15
47 CNTL0 (WR) 20
50 PC0
CNTL1(RD) 19
PC1
18
PC2
35 32 PSEN 49 17
EA/WAIT PSEN CNTL 2(PSEN) PC3
19 14
17 RD 10 PC4
BUSW RD 13
18 WR 8 PD0-ALE PC5
WRL PD1 12
33 ALE 9 PC6
ALE PD2 11
PC7

48
RESET

RESET
AI02883C

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

68HC11
Figure 25 shows a bus interface to a 68HC11 used to generate the READ and WR signals for
where the PSD is configured in 8-bit multiplexed external devices.
mode with E and R/W settings. The DPLD can be

Figure 25. Interfacing the PSD with a 68HC11

AD7-AD0
AD7-AD0

PSD
AD0 30 29
ADIO0 PA0
AD1 31 28
68HC11 ADIO1 PA1
27
AD2 32 PA2
ADIO2
31 AD3 33 25
8 PA3 ADIO3 PA3
XT 30 AD4 34 24
PA4 AD104 PA4
7 29 AD5 35 23
EX PA5 AD105 PA5
28 AD6 36 22
PA6 ADIO6 PA6
17 27 AD7 37 21
RESET PA7 ADIO7 PA7
RESET
19
IRQ
18
XIRQ 42 A8 39 7
PB0 ADIO8 PB0
41 A9 40 6
2 PB1 ADIO9 PB1
MODB 40 A10 41 5
PB2 ADIO10 PB2
39 A11 42 4
34 PB3 ADIO11 PB3
38 A12 43 3
PA0 PB4 AD1012 PB4
33 37 A13 44 2
PA1 PB5 AD1013 PB5
32 36 A14 45 52
PA2 PB6 ADIO14 PB6
35 A15 46 51
PB7 ADIO15 PB7
9 AD0
43 PC0 20
PE0 10 AD1 PC0
44 PC1 47 19
PE1 11 AD2 CNTL0 (R _W) PC1
45 PC2 50 18
PE2 12 AD3 CNTL1(E) PC2
46 PC3 17
PE3 13 AD4 PC3
47 PC4 49 14
PE4 14 AD5 CNTL 2 PC4
48 PC5 13
PE5 15 AD6 PC5
49 PC6 10 12
PE6 16 AD7 PD0 – AS PC6
50 PC7 9 11
PE7 8 PD1 PC7
20 PD2
52 PD0
VRH 21
51 PD1 48
VRL 22 RESET
PD2
23
PD3
24
PD4
25
PD5

3
MODA
5 E
E
4 AS
AS
6 R/W
R/W

RESET
AI02884C

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

I/O PORTS
There are four programmable I/O ports: Ports A, B, The Port pin’s tri-state output driver enable is con-
C, and D. Each of the ports is eight bits except Port trolled by a two input OR gate whose inputs come
D, which is 3 bits. Each port pin is individually user from the CPLD AND Array enable product term
configurable, thus allowing multiple functions per and the Direction Register. If the enable product
port. The ports are configured using PSDsoft Ex- term of any of the Array outputs are not defined
press Configuration or by the MCU writing to on- and that port pin is not defined as a CPLD output
chip registers in the CSIOP space. in the PSDabel file, then the Direction Register has
The topics discussed in this section are: sole control of the buffer that drives the port pin.
■ General Port architecture The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
■ Port operating modes
path allows the MCU to check the contents of the
■ Port Configuration Registers (PCR) registers.
■ Port Data Registers Ports A, B, and C have embedded Input Macro-
■ Individual Port functionality. cells (IMC). The Input Macrocells (IMC) can be
General Port Architecture configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
The general architecture of the I/O Port block is by Address Strobe (ALE/AS, PD0) or a product
shown in Figure 26., page 52. Individual Port ar- term from the PLD AND Array. The outputs from
chitectures are shown in Figure 28., page 58 to the Input Macrocells (IMC) drive the PLD input bus
Figure 31., page 61. In general, once the purpose and can be read by the MCU. See the section en-
for a port pin has been defined, that pin is no long- titled Input Macrocell, page 41.
er available for other purposes. Exceptions are
noted. Port Operating Modes
As shown in Figure 26., page 52, the ports contain The I/O Ports have several modes of operation.
an output multiplexer whose select signals are Some modes can be defined using PSDabel,
driven by the configuration bits in the Control Reg- some by the MCU writing to the Control Registers
isters (Ports A and B only) and PSDsoft Express in CSIOP space, and some by both. The modes
Configuration. Inputs to the multiplexer include the that can only be defined using PSDsoft Express
following: must be programmed into the device and cannot
be changed unless the device is reprogrammed.
■ Output data from the Data Out register The modes that can be changed by the MCU can
■ Latched address outputs be done so dynamically at run-time. The PLD I/O,
■ CPLD macrocell output Data Port, Address Input, and Peripheral I/O
■ External Chip Select (ECS0-ECS2) from the modes are the only modes that must be defined
CPLD. before programming the device. All other modes
can be changed by the MCU at run-time. See Ap-
The Port Data Buffer (PDB) is a tri-state buffer that plication Note AN1171 for more detail.
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal Table 19., page 53 summarizes which modes are
Data Bus for feedback and can be read by the available on each port. Table 22., page 56 shows
MCU. The Data Out and macrocell outputs, Direc- how and where the different modes are config-
tion and Control Registers, and port pin input are ured. Each of the port operating modes are de-
all connected to the Port Data Buffer (PDB). scribed in the following sections.

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Figure 26. General I/O Port Architecture

DATA OUT
REG.
DATA OUT
D Q
WR

ADDRESS ADDRESS
D Q PORT PIN
ALE OUTPUT
G MUX
MACROCELL OUTPUTS
EXT CS
READ MUX
INTERNAL DATA BUS

P OUTPUT
SELECT
D
DATA IN
B

CONTROL REG.
ENABLE OUT
D Q
WR

DIR REG.
D Q
WR

ENABLE PRODUCT TERM (.OE)

INPUT
MACROCELL

CPLD- INPUT

AI02885

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

MCU I/O Mode

In the MCU I/O mode, the MCU uses the I/O Ports corresponding bit in the Direction Register to ’0.’
block to expand its own I/O ports. By setting up the The corresponding bit in the Direction Register
CSIOP space, the ports on the PSD are mapped must not be set to '1' if the pin is defined for a PLD
into the MCU address space. The addresses of input signal in PSDabel. The PLD I/O mode is
the ports are listed in Table 7., page 18. specified in PSDabel by declaring the port pins,
A port pin can be put into MCU I/O mode by writing and then writing an equation assigning the PLD I/
a 0 to the corresponding bit in the Control Regis- O to a port.
ter. The MCU I/O direction may be changed by Address Out Mode
writing to the corresponding bit in the Direction For MCUs with a multiplexed address/data bus,
Register, or by the output enable product term. Address Out Mode can be used to drive latched
See the section entitled Peripheral I/O addresses on to the port pins. These port pins can,
Mode, page 55. When the pin is configured as an in turn, drive external devices. Either the output
output, the content of the Data Out Register drives enable or the corresponding bits of both the Direc-
the pin. When configured as an input, the MCU tion Register and Control Register must be set to
can read the port input through the Data In buffer. a 1 for pins to use Address Out Mode. This must
See Figure 26., page 52. be done by the MCU at run-time. See Table 21 for
Ports C and D do not have Control Registers, and the address output pin assignments on Ports A
are in MCU I/O mode by default. They can be used and B for various MCUs.
for PLD I/O if equations are written for them in PS- For non-multiplexed 8-bit bus mode, address sig-
Dabel. nals (A7-A0) are available to Port B in Address Out
PLD I/O Mode Mode.
The PLD I/O Mode uses a port as an input to the Note: Do not drive address signals with Address
CPLD’s Input Macrocells (IMC), and/or as an out- Out Mode to an external memory device if it is in-
put from the CPLD’s Output Macrocells (OMC). tended for the MCU to Boot from the external de-
The output can be tri-stated with a control signal. vice. The MCU must first Boot from PSD memory
This output enable control signal can be defined so the Direction and Control register bits can be
by a product term from the PLD, or by resetting the set.

Table 19. Port Operating Modes

Port Mode Port A Port B Port C Port D
MCU I/O Yes Yes Yes Yes
PLD I/O
McellAB Outputs Yes Yes No No
McellBC Outputs No Yes Yes No
Additional Ext. CS Outputs No No No Yes
PLD Inputs Yes Yes Yes Yes
Yes (A7 – 0)
Address Out Yes (A7 – 0) No No
or (A15 – 8)
Address In Yes Yes Yes Yes
Data Port Yes (D7 – 0) No No No
Peripheral I/O Yes No No No

JTAG ISP No No Yes1 No

Note: 1. Can be multiplexed with other I/O functions.

53/110
PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 20. Port Operating Mode Settings

Control Direction VM
Defined in Defined in PSD
Mode Register Register Register JTAG Enable
PSDabel Configuration
Setting Setting Setting
1 = output,
MCU I/O Declare pins only N/A1 0 0 = input N/A N/A
(Note 2)

PLD I/O Logic equations N/A N/A (Note 2) N/A N/A

Data Port (Port A) N/A Specify bus type N/A N/A N/A N/A
Address Out
(Port A,B)
Declare pins only N/A 1 1 (Note 2) N/A N/A

Address In Logic for equation

N/A N/A N/A N/A N/A
(Port A,B,C,D) Input Macrocells
Peripheral I/O Logic equations
N/A N/A N/A PIO bit = 1 N/A
(Port A) (PSEL0 & 1)
JTAG
JTAG ISP (Note 3) JTAGSEL
Configuration
N/A N/A N/A JTAG_Enable

Note: 1. N/A = Not Applicable

2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
3. Any of these three methods enables the JTAG pins on Port C.

Table 21. I/O Port Latched Address Output Assignments

MCU Port A (PA3-PA0) Port A (PA7-PA4) Port B (PB3-PB0) Port B (PB7-PB4)

8051XA (8-Bit) N/A1 Address a7-a4 Address a11-a8 N/A

80C251
N/A N/A Address a11-a8 Address a15-a12
(Page Mode)
All Other
Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4
8-Bit Multiplexed
8-Bit
N/A N/A Address a3-a0 Address a7-a4
Non-Multiplexed Bus
Note: 1. N/A = Not Applicable.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Address In Mode Peripheral I/O Mode

For MCUs that have more than 16 address sig- Peripheral I/O mode can be used to interface with
nals, the higher addresses can be connected to external peripherals. In this mode, all of Port A
Port A, B, C, and D. The address input can be serves as a tri-state, bi-directional data buffer for
latched in the Input Macrocell (IMC) by Address the MCU. Peripheral I/O Mode is enabled by set-
Strobe (ALE/AS, PD0). Any input that is included ting Bit 7 of the VM Register to a ’1.’ Figure 27
in the DPLD equations for the SRAM, or primary or shows how Port A acts as a bi-directional buffer for
secondary Flash memory is considered to be an the MCU data bus if Peripheral I/O Mode is en-
address input. abled. An equation for PSEL0 and/or PSEL1 must
Data Port Mode be written in PSDabel. The buffer is tri-stated
when PSEL0 or PSEL1 is not active.
Port A can be used as a data bus port for a MCU
with a non-multiplexed address/data bus. The
Data Port is connected to the data bus of the MCU.
The general I/O functions are disabled in Port A if
the port is configured as a Data Port.

Figure 27. Peripheral I/O Mode

RD

PSEL0

PSEL

PSEL1

D0 - D7
VM REGISTER BIT 7 PA0 - PA7
DATA BUS

WR
AI02886

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JTAG In-System Programming (ISP) Drive Select Register

Port C is JTAG compliant, and can be used for In- The Drive Select Register configures the pin driver
System Programming (ISP). You can multiplex as Open Drain or CMOS for some port pins, and
JTAG operations with other functions on Port C controls the slew rate for the other port pins. An
because In-System Programming (ISP) is not per- external pull-up resistor should be used for pins
formed in normal Operating mode. For more infor- configured as Open Drain.
mation on the JTAG Port, see the section entitled A pin can be configured as Open Drain if its corre-
PROGRAMMING IN-CIRCUIT USING THE JTAG sponding bit in the Drive Select Register is set to a
SERIAL INTERFACE, page 69. ’1.’ The default pin drive is CMOS.
Port Configuration Registers (PCR) Note that the slew rate is a measurement of the
Each Port has a set of Port Configuration Regis- rise and fall times of an output. A higher slew rate
ters (PCR) used for configuration. The contents of means a faster output response and may create
the registers can be accessed by the MCU through more electrical noise. A pin operates in a high slew
normal READ/WRITE bus cycles at the addresses rate when the corresponding bit in the Drive Reg-
given in Table 7., page 18. The addresses in Ta- ister is set to ’1.’ The default rate is slow slew.
ble 7 are the offsets in hexadecimal from the base Table 26., page 57 shows the Drive Register for
of the CSIOP register. Ports A, B, C, and D. It summarizes which pins can
The pins of a port are individually configurable and be configured as Open Drain outputs and which
each bit in the register controls its respective pin. pins the slew rate can be set for.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers Table 22. Port Configuration Registers (PCR)
(PCR), shown in Table 22, are used for setting the
Port configurations. The default Power-up state for Register Name Port MCU Access
each register in Table 22 is 00h. Control A,B WRITE/READ
Control Register
Direction A,B,C,D WRITE/READ
Any bit reset to '0' in the Control Register sets the
corresponding port pin to MCU I/O Mode, and a '1' Drive Select1 A,B,C,D WRITE/READ
sets it to Address Out Mode. The default mode is
MCU I/O. Only Ports A and B have an associated Note: 1. See Table 26., page 57 for Drive Register bit definition.
Control Register.
Direction Register Table 23. Port Pin Direction Control, Output
The Direction Register, in conjunction with the out- Enable P.T. Not Defined
put enable (except for Port D), controls the direc- Direction Register Bit Port Pin Mode
tion of data flow in the I/O Ports. Any bit set to '1'
in the Direction Register causes the correspond- 0 Input
ing pin to be an output, and any bit set to '0' causes 1 Output
it to be an input. The default mode for all port pins
is input.
Figure 28., page 58 and Figure 29., page 59 show Table 24. Port Pin Direction Control, Output
the Port Architecture diagrams for Ports A/B and Enable P.T. Defined
C, respectively. The direction of data flow for Ports Direction Output Enable
Port Pin Mode
A, B, and C are controlled not only by the direction Register Bit P.T.
register, but also by the output enable product
term from the PLD AND Array. If the output enable 0 0 Input
product term is not active, the Direction Register 0 1 Output
has sole control of a given pin’s direction.
1 0 Output
An example of a configuration for a Port with the
three least significant bits set to output and the re- 1 1 Output
mainder set to input is shown in Table 25. Since
Port D only contains three pins (shown in Figure
31., page 61), the Direction Register for Port D Table 25. Port Direction Assignment Example
has only the three least significant bits active. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 0 1 1 1

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Table 26. Drive Register Pin Assignment

Drive
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
Open Open Open Open Slew Slew Slew Slew
Port A
Drain Drain Drain Drain Rate Rate Rate Rate
Open Open Open Open Slew Slew Slew Slew
Port B
Drain Drain Drain Drain Rate Rate Rate Rate
Open Open Open Open Open Open Open Open
Port C
Drain Drain Drain Drain Drain Drain Drain Drain
Slew Slew Slew
Port D NA1 NA1 NA1 NA1 NA1 Rate Rate Rate
Note: 1. NA = Not Applicable.

Port Data Registers Output Macrocells (OMC). The CPLD Output

The Port Data Registers, shown in Table 27, are Macrocells (OMC) occupy a location in the MCU’s
used by the MCU to write data to or read data from address space. The MCU can read the output of
the ports. Table 27 shows the register name, the the Output Macrocells (OMC). If the OMC Mask
ports having each register type, and MCU access Register bits are not set, writing to the macrocell
for each register type. The registers are described loads data to the macrocell flip-flops. See the sec-
below. tion entitled PLDS, page 33.
Data In OMC Mask Register
Port pins are connected directly to the Data In buff- Each OMC Mask Register bit corresponds to an
er. In MCU I/O input mode, the pin input is read Output Macrocell (OMC) flip-flop. When the OMC
through the Data In buffer. Mask Register bit is set to a 1, loading data into the
Output Macrocell (OMC) flip-flop is blocked. The
Data Out Register
default value is 0 or unblocked.
Stores output data written by the MCU in the MCU
I/O output mode. The contents of the Register are
driven out to the pins if the Direction Register or
the output enable product term is set to ’1.’ The
contents of the register can also be read back by
the MCU.

Table 27. Port Data Registers

Register Name Port MCU Access
Data In A,B,C,D READ – input on pin
Data Out A,B,C,D WRITE/READ
READ – outputs of macrocells
Output Macrocell A,B,C
WRITE – loading macrocells flip-flop
WRITE/READ – prevents loading into a given
Mask Macrocell A,B,C
macrocell
Input Macrocell A,B,C READ – outputs of the Input Macrocells
Enable Out A,B,C READ – the output enable control of the port driver

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Input Macrocells (IMC) Ports A and B – Functionality and Structure

The Input Macrocells (IMC) can be used to latch or Ports A and B have similar functionality and struc-
store external inputs. The outputs of the Input ture, as shown in Figure 28. The two ports can be
Macrocells (IMC) are routed to the PLD input bus, configured to perform one or more of the following
and can be read by the MCU. See the section en- functions:
titled PLDS, page 33. ■ MCU I/O Mode
Enable Out ■ CPLD Output – Macrocells McellAB7-
The Enable Out register can be read by the MCU. McellAB0 can be connected to Port A or Port
It contains the output enable values for a given B. McellBC7-McellBC0 can be connected to
port. A 1 indicates the driver is in output mode. A Port B or Port C.
0 indicates the driver is in tri-state and the pin is in ■ CPLD Input – Via the Input Macrocells (IMC).
input mode.
■ Latched Address output – Provide latched
address output as per Table 21., page 54.
■ Address In – Additional high address inputs
using the Input Macrocells (IMC).
■ Open Drain/Slew Rate – pins PA3-PA0 and
PB3-PB0 can be configured to fast slew rate,
pins PA7-PA4 and PB7-PB4 can be
configured to Open Drain Mode.
■ Data Port – Port A to D7-D0 for 8 bit non-
multiplexed bus
■ Multiplexed Address/Data port for certain
types of MCU bus interfaces.
■ Peripheral Mode – Port A only

Figure 28. Port A and Port B Structure

DATA OUT
REG.
DATA OUT
D Q
WR

ADDRESS PORT
ADDRESS A OR B PIN
D Q
ALE A[ 7:0] OR A[15:8] OUTPUT
G MUX

MACROCELL OUTPUTS

READ MUX
INTERNAL DATA BUS

P OUTPUT
SELECT
D DATA IN
B

CONTROL REG.
ENABLE OUT
D Q
WR

DIR REG.
D Q
WR

ENABLE PRODUCT TERM (.OE)

INPUT
MACROCELL

CPLD - INPUT

AI02887

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Port C – Functionality and Structure

Port C can be configured to perform one or more ■ Open Drain – Port C pins can be configured in
of the following functions (see Figure 29): Open Drain Mode
■ MCU I/O Mode ■ Battery Backup features – PC2 can be
■ CPLD Output – McellBC7-McellBC0 outputs configured for a battery input supply, Voltage
can be connected to Port B or Port C. Stand-by (VSTBY).
■ CPLD Input – via the Input Macrocells (IMC) PC4 can be configured as a Battery-on Indicator
(VBATON), indicating when VCC is less than
■ Address In – Additional high address inputs
VBAT.
using the Input Macrocells (IMC).
Port C does not support Address Out mode, and
■ In-System Programming (ISP) – JTAG port therefore no Control Register is required.
can be enabled for programming/erase of the
PSD device. (See the section entitled Pin PC7 may be configured as the DBE input in
PROGRAMMING IN-CIRCUIT USING THE certain MCU bus interfaces.
JTAG SERIAL INTERFACE, page 69 for
more information on JTAG programming.)

Figure 29. Port C Structure

DATA OUT
REG.
DATA OUT
D Q
WR

1 PORT C PIN
SPECIAL FUNCTION OUTPUT
MUX

MCELLBC[ 7:0]

READ MUX
INTERNAL DATA BUS

P OUTPUT
SELECT
D
DATA IN
B

ENABLE OUT

DIR REG.

D Q
WR

ENABLE PRODUCT TERM (.OE)

INPUT
MACROCELL

1
CPLD - INPUT SPECIAL FUNCTION CONFIGURATION
BIT AI02888B

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Port D – Functionality and Structure

Port D has three I/O pins. See Figure 30 and Fig- ■ Slew rate – pins can be set up for fast slew
ure 31., page 61. This port does not support Ad- rate
dress Out mode, and therefore no Control Port D pins can be configured in PSDsoft Express
Register is required. Port D can be configured to as input pins for other dedicated functions:
perform one or more of the following functions:
■ Address Strobe (ALE/AS, PD0)
■ MCU I/O Mode
■ CLKIN (PD1) as input to the macrocells flip-
■ CPLD Output – External Chip Select (ECS0- flops and APD counter
ECS2)
■ PSD Chip Select Input (CSI, PD2). Driving this
■ CPLD Input – direct input to the CPLD, no signal High disables the Flash memory, SRAM
Input Macrocells (IMC) and CSIOP.

Figure 30. Port D Structure

DATA OUT
REG.
DATA OUT
D Q
WR

PORT D PIN
OUTPUT
MUX

ECS[ 2:0]

READ MUX
INTERNAL DATA BUS

P OUTPUT
SELECT
D

B DATA IN

ENABLE PRODUCT
DIR REG. TERM (.OE)

D Q
WR
CPLD-INPUT AI02889

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External Chip Select

The CPLD also provides three External Chip Se- term that can be configured active High or Low.
lect (ECS0-ECS2) outputs on Port D pins that can The output enable of the pin is controlled by either
be used to select external devices. Each External the output enable product term or the Direction
Chip Select (ECS0-ECS2) consists of one product Register. (See Figure 31.)

Figure 31. Port D External Chip Select Signals

ENABLE (.OE) DIRECTION

REGISTER

PT0 PD0 PIN

ECS0

POLARITY
CPLD AND ARRAY

BIT
PLD INPUT BUS

ENABLE (.OE) DIRECTION

REGISTER

PT1 PD1 PIN

ECS1

POLARITY
BIT
ENABLE (.OE) DIRECTION
REGISTER

PT2 PD2 PIN

ECS2

POLARITY
BIT AI02890

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POWER MANAGEMENT
All PSD devices offer configurable power saving remain in standby mode even if the address/
options. These options may be used individually or data signals are changing state externally
in combinations, as follows: (noise, other devices on the MCU bus, etc.).
■ All memory blocks in a PSD (primary and Keep in mind that any unblocked PLD input
secondary Flash memory, and SRAM) are signals that are changing states keeps the PLD
built with power management technology. In out of Stand-by mode, but not the memories.
addition to using special silicon design ■ PSD Chip Select Input (CSI, PD2) can be
methodology, power management technology used to disable the internal memories, placing
puts the memories into standby mode when them in standby mode even if inputs are
address/data inputs are not changing (zero changing. This feature does not block any
DC current). As soon as a transition occurs on internal signals or disable the PLDs. This is a
an input, the affected memory “wakes up”, good alternative to using the APD Unit. There
changes and latches its outputs, then goes is a slight penalty in memory access time
back to standby. The designer does not have when PSD Chip Select Input (CSI, PD2)
to do anything special to achieve memory makes its initial transition from deselected to
standby mode when no inputs are changing— selected.
it happens automatically. ■ The PMMRs can be written by the MCU at run-
The PLD sections can also achieve Stand-by time to manage power. All PSD supports
mode when its inputs are not changing, as “blocking bits” in these registers that are set to
described in the sections on the Power block designated signals from reaching both
Management Mode Registers (PMMR). PLDs. Current consumption of the PLDs is
■ As with the Power Management mode, the directly related to the composite frequency of
Automatic Power Down (APD) block allows the changes on their inputs (see Figure 35 and
the PSD to reduce to stand-by current Figure 36., page 72). Significant power
automatically. The APD Unit can also block savings can be achieved by blocking signals
MCU address/data signals from reaching the that are not used in DPLD or CPLD logic
memories and PLDs. This feature is available equations.
on all the devices of the PSD family. The APD PSD devices have a Turbo Bit in PMMR0. This
Unit is described in more detail in the sections bit can be set to turn the Turbo mode off (the
entitled Automatic Power-down (APD) Unit default is with Turbo mode turned on). While
and Power-down Mode, page 63. Turbo mode is off, the PLDs can achieve
Built in logic monitors the Address Strobe of the standby current when no PLD inputs are
MCU for activity. If there is no activity for a changing (zero DC current). Even when inputs
certain time period (MCU is asleep), the APD do change, significant power can be saved at
Unit initiates Power-down mode (if enabled). lower frequencies (AC current), compared to
Once in Power-down mode, all address/data when Turbo mode is on. When the Turbo mode
signals are blocked from reaching PSD memory is on, there is a significant DC current
and PLDs, and the memories are deselected component and the AC component is higher.
internally. This allows the memory and PLDs to

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Automatic Power-down (APD) Unit and Power-down Mode

The APD Unit, shown in Figure 32, puts the PSD registers. The blocked signals include MCU
into Power-down mode by monitoring the activity control signals and the common CLKIN (PD1).
of Address Strobe (ALE/AS, PD0). If the APD Unit Note that blocking CLKIN (PD1) from the
is enabled, as soon as activity on Address Strobe PLDs does not block CLKIN (PD1) from the
(ALE/AS, PD0) stops, a four bit counter starts APD Unit.
counting. If Address Strobe (ALE/AS, PD0) re- – All PSD memories enter Standby mode and
mains inactive for fifteen clock periods of CLKIN are drawing standby current. However, the
(PD1), Power-down (PDN) goes High, and the PLD and I/O ports blocks do not go into
PSD enters Power-down mode, as discussed Standby Mode because you don’t want to
next. have to wait for the logic and I/O to “wake-up”
Power-down Mode. By default, if you enable the before their outputs can change. See Table 28
APD Unit, Power-down mode is automatically en- for Power-down mode effects on PSD ports.
abled. The device enters Power-down mode if Ad- – Typical standby current is of the order of
dress Strobe (ALE/AS, PD0) remains inactive for microamperes. These standby current values
fifteen periods of CLKIN (PD1). assume that there are no transitions on any
The following should be kept in mind when the PLD input.
PSD is in Power-down mode:
– If Address Strobe (ALE/AS, PD0) starts Table 28. Power-down Mode’s Effect on Ports
pulsing again, the PSD returns to normal
Port Function Pin Level
Operating mode. The PSD also returns to
normal Operating mode if either PSD Chip MCU I/O No Change
Select Input (CSI, PD2) is Low or the Reset
(RESET) input is High. PLD Out No Change
– The MCU address/data bus is blocked from all Address Out Undefined
memory and PLDs.
Data Port Tri-State
– Various signals can be blocked (prior to
Power-down mode) from entering the PLDs by Peripheral I/O Tri-State
setting the appropriate bits in the PMMR

Figure 32. APD Unit

APD EN
PMMR0 BIT 1=1
TRANSITION
DETECTION DISABLE BUS
INTERFACE
ALE
CLR PD

APD EEPROM SELECT

COUNTER
RESET FLASH SELECT
EDGE PD
CSI DETECT PLD SRAM SELECT

CLKIN POWER DOWN

(PDN) SELECT

DISABLE
FLASH/EEPROM/SRAM AI02891

Table 29. PSD Timing and Stand-by Current during Power-down Mode
PLD Propagation Memory Access Recovery Time Typical Stand-by Current
Mode
Delay Access Time to Normal Access 5V VCC 3V VCC

Power-down Normal tPD (Note 1) No Access tLVDV 75µA (Note 2) 25µA (Note 2)
Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit.
2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is ’0.’

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For Users of the HC11 (or compatible) PLD Power Management

The HC11 turns off its E clock when it sleeps. The power and speed of the PLDs are controlled
Therefore, if you are using an HC11 (or compati- by the Turbo Bit (Bit 3) in PMMR0. By setting the
ble) in your design, and you wish to use the Pow- bit to '1,' the Turbo mode is off and the PLDs con-
er-down mode, you must not connect the E clock sume the specified stand-by current when the in-
to CLKIN (PD1). You should instead connect a puts are not switching for an extended time of
crystal oscillator to CLKIN (PD1). The crystal oscil- 70ns. The propagation delay time is increased by
lator frequency must be less than 15 times the fre- 10ns after the Turbo Bit is set to '1' (turned off)
quency of AS. The reason for this is that if the when the inputs change at a composite frequency
frequency is greater than 15 times the frequency of less than 15 MHz. When the Turbo Bit is reset
of AS, the PSD keeps going into Power-down to '0' (turned on), the PLDs run at full power and
mode. speed. The Turbo Bit affects the PLD’s DC power,
Other Power Saving Options AC power, and propagation delay.
The PSD offers other reduced power saving op- Blocking MCU control signals with the bits of
tions that are independent of the Power-down PMMR2 can further reduce PLD AC power con-
mode. Except for the SRAM Stand-by and PSD sumption.
Chip Select Input (CSI, PD2) features, they are en- SRAM Standby Mode (Battery Backup). The
abled by setting bits in PMMR0 and PMMR2. PSD supports a battery backup mode in which the
contents of the SRAM are retained in the event of
Figure 33. Enable Power-down Flow Chart a power loss. The SRAM has Voltage Stand-by
(VSTBY, PC2) that can be connected to an external
RESET battery. When VCC becomes lower than VSTBY
then the PSD automatically connects to Voltage
Stand-by (VSTBY, PC2) as a power source to the
Enable APD
Set PMMR0 Bit 1 = 1 SRAM. The SRAM Standby Current (ISTBY) is typ-
ically 0.5µA. The SRAM data retention voltage is
2V minimum. The Battery-on Indicator (VBATON)
can be routed to PC4. This signal indicates when
OPTIONAL the VCC has dropped below VSTBY.
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.

No ALE/AS idle
for 15 CLKIN
clocks?

Yes

PSD in Power
Down Mode
AI02892

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 30. Power Management Mode Registers PMMR0 (Note 1)

Bit 0 X 0 Not used, and should be set to zero.
0 = off Automatic Power-down (APD) is disabled.
Bit 1 APD Enable
1 = on Automatic Power-down (APD) is enabled.
Bit 2 X 0 Not used, and should be set to zero.
0 = on PLD Turbo mode is on
Bit 3 PLD Turbo
1 = off PLD Turbo mode is off, saving power.
CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN
0 = on
Bit 4 PLD Array clk (PD1) Powers-up the PLD when Turbo Bit is ’0.’
1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power.
0 = on CLKIN (PD1) input to the PLD macrocells is connected.
Bit 5 PLD MCell clk
1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.
Bit 6 X 0 Not used, and should be set to zero.
Bit 7 X 0 Not used, and should be set to zero.
Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.

Table 31. Power Management Mode Registers PMMR2 (Note 1)

Bit 0 X 0 Not used, and should be set to zero.
Bit 1 X 0 Not used, and should be set to zero.

PLD Array 0 = on Cntl0 input to the PLD AND Array is connected.

Bit 2
CNTL0 1 = off Cntl0 input to PLD AND Array is disconnected, saving power.

PLD Array 0 = on Cntl1 input to the PLD AND Array is connected.

Bit 3
CNTL1 1 = off Cntl1 input to PLD AND Array is disconnected, saving power.

PLD Array 0 = on Cntl2 input to the PLD AND Array is connected.

Bit 4
CNTL2 1 = off Cntl2 input to PLD AND Array is disconnected, saving power.

PLD Array 0 = on ALE input to the PLD AND Array is connected.

Bit 5
ALE 1 = off ALE input to PLD AND Array is disconnected, saving power.

PLD Array 0 = on DBE input to the PLD AND Array is connected.

Bit 6
DBE 1 = off DBE input to PLD AND Array is disconnected, saving power.
Bit 7 X 0 Not used, and should be set to zero.
Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.

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PSD Chip Select Input (CSI, PD2) Input Clock

PD2 of Port D can be configured in PSDsoft Ex- The PSD provides the option to turn off CLKIN
press as PSD Chip Select Input (CSI). When Low, (PD1) to the PLD to save AC power consumption.
the signal selects and enables the internal Flash CLKIN (PD1) is an input to the PLD AND Array and
memory, EEPROM, SRAM, and I/O blocks for the Output Macrocells (OMC).
READ or WRITE operations involving the PSD. A During Power-down mode, or, if CLKIN (PD1) is
High on PSD Chip Select Input (CSI, PD2) dis- not being used as part of the PLD logic equation,
ables the Flash memory, EEPROM, and SRAM, the clock should be disabled to save AC power.
and reduces the PSD power consumption. How- CLKIN (PD1) is disconnected from the PLD AND
ever, the PLD and I/O signals remain operational Array or the Macrocells block by setting Bits 4 or 5
when PSD Chip Select Input (CSI, PD2) is High. to a 1 in PMMR0.
There may be a timing penalty when using PSD Input Control Signals
Chip Select Input (CSI, PD2) depending on the
speed grade of the PSD that you are using. See The PSD provides the option to turn off the input
control signals (CNTL0, CNTL1, CNTL2, Address
the timing parameter tSLQV in Table 61., page 94
Strobe (ALE/AS, PD0) and DBE) to the PLD to
or Table 62., page 95.
save AC power consumption. These control sig-
nals are inputs to the PLD AND Array. During
Power-down mode, or, if any of them are not being
used as part of the PLD logic equation, these con-
trol signals should be disabled to save AC power.
They are disconnected from the PLD AND Array
by setting Bits 2, 3, 4, 5, and 6 to a 1 in PMMR2.

Table 32. APD Counter Operation

APD Enable Bit ALE PD Polarity ALE Level APD Counter
0 X X Not Counting
1 X Pulsing Not Counting
1 1 1 Counting (Generates PDN after 15 Clocks)
1 0 0 Counting (Generates PDN after 15 Clocks)

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

RESET TIMING AND DEVICE STATUS AT RESET

Power-Up Reset
Upon Power-up, the PSD requires a Reset (RE- The same tOPR period is needed before the device
SET) pulse of duration tNLNH-PO after VCC is is operational after warm reset. Figure 34 shows
steady. During this period, the device loads inter- the timing of the Power-up and warm reset.
nal configurations, clears some of the registers I/O Pin, Register and PLD Status at Reset
and sets the Flash memory into Operating mode.
Table 33., page 68 shows the I/O pin, register and
After the rising edge of Reset (RESET), the PSD
PLD status during Power On Reset, warm reset
remains in the Reset mode for an additional peri-
and Power-down mode. PLD outputs are always
od, tOPR, before the first memory access is al-
lowed. valid during warm reset, and they are valid in Pow-
er On Reset once the internal PSD Configuration
The Flash memory is reset to the READ Mode bits are loaded. This loading of PSD is completed
upon Power-up. Sector Select (FS0-FS7 and typically long before the VCC ramps up to operat-
CSBOOT0-CSBOOT3) must all be Low, Write ing level. Once the PLD is active, the state of the
Strobe (WR, CNTL0) High, during Power On Re- outputs are determined by the PSDabel equa-
set for maximum security of the data contents and tions.
to remove the possibility of a byte being written on
Reset of Flash Memory Erase and Program
the first edge of Write Strobe (WR, CNTL0). Any
Flash memory WRITE cycle initiation is prevented Cycles (on the PSD834Fx)
automatically when VCC is below VLKO. A Reset (RESET) also resets the internal Flash
memory state machine. During a Flash memory
Warm Reset
Program or Erase cycle, Reset (RESET) termi-
Once the device is up and running, the device can nates the cycle and returns the Flash memory to
be reset with a pulse of a much shorter duration, the Read Mode within a period of tNLNH-A.
tNLNH.

Figure 34. Reset (RESET) Timing

VCC VCC(min)

tNLNH
tNLNH-PO tOPR tNLNH-A tOPR
Power-On Reset Warm Reset

RESET

AI02866b

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode
Port Configuration Power-On Reset Warm Reset Power-down Mode
MCU I/O Input mode Input mode Unchanged
Valid after internal PSD Depends on inputs to PLD
PLD Output configuration bits are Valid (addresses are blocked in
loaded PD mode)
Address Out Tri-stated Tri-stated Not defined
Data Port Tri-stated Tri-stated Tri-stated
Peripheral I/O Tri-stated Tri-stated Tri-stated

Register Power-On Reset Warm Reset Power-down Mode

PMMR0 and PMMR2 Cleared to '0' Unchanged Unchanged
Cleared to '0' by internal Depends on .re and .pr Depends on .re and .pr
Macrocells flip-flop status
Power-On Reset equations equations
Initialized, based on the Initialized, based on the
VM Register1 selection in PSDsoft selection in PSDsoft Unchanged
Configuration menu Configuration menu
All other registers Cleared to '0' Cleared to '0' Unchanged
Note: 1. The SR_cod and PeriphMode bits in the VM Register are always cleared to '0' on Power-On Reset or Warm Reset.

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PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE

The JTAG Serial Interface block can be enabled This dedicates the pins for JTAG at all
on Port C (see Table 34., page 70). All memory times (compliant with IEEE 1149.1 */
blocks (primary and secondary Flash memory), Microcontroller_enabled +
PLD logic, and PSD Configuration Register bits /* The microcontroller can set a bit at
may be programmed through the JTAG Serial In- run-time by writing to the PSD
terface block. A blank device can be mounted on register, JTAG Enable. This register is
a printed circuit board and programmed using located at address CSIOP + offset C7h.
JTAG. Setting the JTAG_ENABLE bit in this
The standard JTAG signals (IEEE 1149.1) are register will enable the pins for JTAG
TMS, TCK, TDI, and TDO. Two additional signals, use. This bit is cleared by a PSD reset
TSTAT and TERR, are optional JTAG extensions or the microcontroller. See Table
used to speed up Program and Erase cycles. 35., page 71 for bit definition. */
PSD_product_term_enabled;
By default, on a blank PSD (as shipped from the
/* A dedicated product term (PT) inside
factory or after erasure), four pins on Port C are
the PSD can be used to enable the JTAG
enabled for the basic JTAG signals TMS, TCK, pins. This PT has the reserved name
TDI, and TDO. JTAGSEL. Once defined as a node in
See Application Note AN1153 for more details on PSDabel, the designer can write an
JTAG In-System Programming (ISP). equation for JTAGSEL. This method is
Standard JTAG Signals used when the Port C JTAG pins are
The standard JTAG signals (TMS, TCK, TDI, and multiplexed with other I/O signals. It
TDO) can be enabled by any of three different con- is recommended to logically tie the
ditions that are logically ORed. When enabled, node JTAGSEL to the JEN\ signal on the
TDI, TDO, TCK, and TMS are inputs, waiting for a Flashlink cable when multiplexing JTAG
JTAG serial command from an external JTAG con- signals. See Application Note 1153 for
troller device (such as FlashLINK or Automated details. */
Test Equipment). When the enabling command is The state of the PSD Reset (RESET) signal does
received, TDO becomes an output and the JTAG not interrupt (or prevent) JTAG operations if the
channel is fully functional inside the PSD. The JTAG pins are dedicated by an NVM configuration
same command that enables the JTAG channel bit (via PSDsoft Express). However, Reset (RE-
may optionally enable the two additional JTAG sig- SET) will prevent or interrupt JTAG operations if
nals, TSTAT and TERR. the JTAG enable register is used to enable the
The following symbolic logic equation specifies the JTAG pins.
conditions enabling the four basic JTAG signals The PSD supports JTAG In-System-Configuration
(TMS, TCK, TDI, and TDO) on their respective (ISC) commands, but not Boundary Scan. The PS-
Port C pins. For purposes of discussion, the logic Dsoft Express software tool and FlashLINK JTAG
label JTAG_ON is used. When JTAG_ON is true, programming cable implement the JTAG In-Sys-
the four pins are enabled for JTAG. When tem-Configuration (ISC) commands. A definition
JTAG_ON is false, the four pins can be used for of these JTAG In-System-Configuration (ISC)
general PSD I/O. commands and sequences is defined in a supple-
JTAG_ON = PSDsoft_enabled + mental document available from ST. This docu-
/* An NVM configuration bit inside the ment is needed only as a reference for designers
PSD is set by the designer in the who use a FlashLINK to program their PSD.
PSDsoft Express Configuration utility.

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

JTAG Extensions Security and Flash memory Protection

TSTAT and TERR are two JTAG extension signals When the security bit is set, the device cannot be
enabled by an “ISC_ENABLE” command received read on a Device Programmer or through the
over the four standard JTAG signals (TMS, TCK, JTAG Port. When using the JTAG Port, only a Full
TDI, and TDO). They are used to speed Program Chip Erase command is allowed.
and Erase cycles by indicating status on PSD sig- All other Program, Erase and Verify commands
nals instead of having to scan the status out seri- are blocked. Full Chip Erase returns the part to a
ally using the standard JTAG channel. See non-secured blank state. The Security Bit can be
Application Note AN1153. set in PSDsoft Express Configuration.
TERR indicates if an error has occurred when All primary and secondary Flash memory sectors
erasing a sector or programming a byte in Flash can individually be sector protected against era-
memory. This signal goes Low (active) when an sures. The sector protect bits can be set in PSD-
Error condition occurs, and stays Low until an soft Express Configuration.
“ISC_CLEAR” command is executed or a chip Re-
set (RESET) pulse is received after an
“ISC_DISABLE” command. Table 34. JTAG Port Signals
TSTAT behaves the same as Ready/Busy de- Port C Pin JTAG Signals Description
scribed in the section entitled Ready/Busy PC0 TMS Mode Select
(PC3), page 20. TSTAT is High when the PSD de-
vice is in READ Mode (primary and secondary PC1 TCK Clock
Flash memory contents can be read). TSTAT is
Low when Flash memory Program or Erase cycles PC3 TSTAT Status
are in progress, and also when data is being writ- PC4 TERR Error Flag
ten to the secondary Flash memory.
PC5 TDI Serial Data In
TSTAT and TERR can be configured as open-
drain type signals during an “ISC_ENABLE” com- PC6 TDO Serial Data Out
mand. This facilitates a wired-OR connection of
TSTAT signals from multiple PSD devices and a
wired-OR connection of TERR signals from those
same devices. This is useful when several PSD
devices are “chained” together in a JTAG environ-
ment.

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INITIAL DELIVERY STATE

When delivered from ST, the PSD device has all programming procedure. Information for program-
bits in the memory and PLDs set to ’1.’ The PSD ming the device is available directly from ST.
Configuration Register bits are set to ’0.’ The code, Please contact your local sales representative.
configuration, and PLD logic are loaded using the

Table 35. JTAG Enable Register

0 = off JTAG port is disabled.
Bit 0 JTAG_Enable
1 = on JTAG port is enabled.
Bit 1 X 0 Not used, and should be set to zero.
Bit 2 X 0 Not used, and should be set to zero.
Bit 3 X 0 Not used, and should be set to zero.
Bit 4 X 0 Not used, and should be set to zero.
Bit 5 X 0 Not used, and should be set to zero.
Bit 6 X 0 Not used, and should be set to zero.
Bit 7 X 0 Not used, and should be set to zero.
Note: 1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Config-
uration bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is
used to enable the JTAG signals.

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AC/DC PARAMETERS
These tables describe the AD and DC parameters – Power-down and Reset Timing
of the PSD: The following are issues concerning the parame-
❏ DC Electrical Specification ters presented:
❏ AC Timing Specification – In the DC specification the supply current is
■ PLD Timing given for different modes of operation. Before
calculating the total power consumption,
– Combinatorial Timing determine the percentage of time that the PSD
– Synchronous Clock Mode is in each mode. Also, the supply power is
– Asynchronous Clock Mode considerably different if the Turbo Bit is ’0.’
– Input Macrocell Timing – The AC power component gives the PLD,
■ MCU Timing Flash memory, and SRAM mA/MHz
specification. Figures 35 and 36 show the PLD
– READ Timing mA/MHz as a function of the number of
– WRITE Timing Product Terms (PT) used.
– Peripheral Mode Timing – In the PLD timing parameters, add the
required delay when Turbo Bit is ’0.’

Figure 35. PLD ICC /Frequency Consumption (5V range)

110

100 VCC = 5V
)
00%
90
ON (1
BO
80 TUR

70
ICC – (mA)

)
(25%
FF

60
O ON
URB
O

T
O

50
RB
TU

40

30
F
20 OF PT 100%
O
RB PT 25%
TU
10

0
0 5 10 15 20 25

HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) AI02894

Figure 36. PLD ICC /Frequency Consumption (3V range)

60
VCC = 3V )
100%
50 O ON (
T URB

40
ICC – (mA)

30
FF

%)
O

(25
O ON
O

TU R B
RB

20
TU

PT 100%
10 F
OF PT 25%
O
RB
TU
0
0 5 10 15 20 25

HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) AI03100

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Table 36. Example of PSD Typical Power Calculation at VCC = 5.0V (Turbo Mode On)
Conditions
Highest Composite PLD input frequency
(Freq PLD) = 8 MHz
MCU ALE frequency (Freq ALE) = 4 MHz
% Flash memory Access = 80%
% SRAM access = 15%
% I/O access = 5% (no additional power above base)
Operational Modes
% Normal = 10%
% Power-down Mode = 90%
Number of product terms used
(from fitter report) = 45 PT
% of total product terms = 45/182 = 24.7%
Turbo Mode = ON
Calculation (using typical values)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))

= Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE

+ %SRAM x 1.5mA/MHz x Freq ALE
+ % PLD x 2mA/MHz x Freq PLD
+ #PT x 400µA/PT)
= 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz
+ 0.15 x 1.5mA/MHz x 4 MHz
+ 2mA/MHz x 8 MHz
+ 45 x 0.4mA/PT)
= 45µA + 0.1 x (8 + 0.9 + 16 + 18mA)
= 45µA + 0.1 x 42.9
= 45µA + 4.29mA
= 4.34mA
This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based
on IOUT = 0mA.

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Table 37. Example of PSD Typical Power Calculation at VCC = 5.0V (Turbo Mode Off)
Conditions
Highest Composite PLD input frequency
(Freq PLD) = 8 MHz
MCU ALE frequency (Freq ALE) = 4 MHz
% Flash memory Access = 80%
% SRAM access = 15%
% I/O access = 5% (no additional power above base)
Operational Modes
% Normal = 10%
% Power-down Mode = 90%
Number of product terms used
(from fitter report) = 45 PT
% of total product terms = 45/182 = 24.7%
Turbo Mode = Off
Calculation (using typical values)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))

= Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE

+ %SRAM x 1.5mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz
+ 0.15 x 1.5mA/MHz x 4 MHz
+ 24mA)
= 45µA + 0.1 x (8 + 0.9 + 24)
= 45µA + 0.1 x 32.9
= 45µA + 3.29mA
= 3.34mA
This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based
on IOUT = 0mA.

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MAXIMUM RATING
Stressing the device above the rating listed in the plied. Exposure to Absolute Maximum Rating con-
Absolute Maximum Ratings” table may cause per- ditions for extended periods may affect device
manent damage to the device. These are stress reliability. Refer also to the STMicroelectronics
ratings only and operation of the device at these or SURE Program and other relevant quality docu-
any other conditions above those indicated in the ments.
Operating sections of this specification is not im-

Table 38. Absolute Maximum Ratings

Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 125 °C

TLEAD Lead Temperature during Soldering (20 seconds max.)1 235 °C

VIO Input and Output Voltage (Q = VOH or Hi-Z) –0.6 7.0 V

VCC Supply Voltage –0.6 7.0 V
VPP Device Programmer Supply Voltage –0.6 14.0 V

VESD Electrostatic Discharge Voltage (Human Body model) 2 –2000 2000 V

Note: 1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

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DC AND AC PARAMETERS
This section summarizes the operating and mea- ment Conditions summarized in the relevant
surement conditions, and the DC and AC charac- tables. Designers should check that the operating
teristics of the device. The parameters in the DC conditions in their circuit match the measurement
and AC Characteristic tables that follow are de- conditions when relying on the quoted parame-
rived from tests performed under the Measure- ters.

Table 39. Operating Conditions (5V devices)

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 4.5 5.5 V

Ambient Operating Temperature (industrial) –40 85 °C

TA
Ambient Operating Temperature (commercial) 0 70 °C

Table 40. Operating Conditions (3V devices)

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 3.0 3.6 V

Ambient Operating Temperature (industrial) –40 85 °C

TA
Ambient Operating Temperature (commercial) 0 70 °C

Table 41. AC Signal Letters for PLD Timing Table 42. AC Signal Behavior Symbols for PLD
A Address Input
Timing
t Time
C CEout Output
L Logic Level Low or ALE
D Input Data
H Logic Level High
E E Input
V Valid
G Internal WDOG_ON signal
X No Longer a Valid Logic Level
I Interrupt Input
Z Float
L ALE Input
PW Pulse Width
N RESET Input or Output
Note: Example: tAVLX = Time from Address Valid to ALE Invalid.
P Port Signal Output
Q Output Data
R WR, UDS, LDS, DS, IORD, PSEN Inputs
S Chip Select Input
T R/W Input
W Internal PDN Signal

B VSTBY Output

M Output Macrocell
Note: Example: tAVLX = Time from Address Valid to ALE Invalid.

Table 43. AC Measurement Conditions

Symbol Parameter Min. Max. Unit

CL Load Capacitance 30 pF
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 44. Capacitance

Symbol Parameter Test Condition Typ.2 Max. Unit
CIN Input Capacitance (for input pins) VIN = 0V 4 6 pF
Output Capacitance (for input/ pF
COUT VOUT = 0V 8 12
output pins)
CVPP Capacitance (for CNTL2/VPP) VPP = 0V 18 25 pF
Note: 1. Sampled only, not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.

Figure 37. AC Measurement I/O Waveform Figure 38. AC Measurement Load Circuit

2.01 V

3.0V 195 Ω
Test Point 1.5V
Device
Under Test
0V CL = 30 pF
AI03103b (Including Scope and
Jig Capacitance)
AI03104b

Figure 39. Switching Waveforms – Key

WAVEFORMS INPUTS OUTPUTS

STEADY INPUT STEADY OUTPUT

MAY CHANGE FROM WILL BE CHANGING

HI TO LO FROM HI TO LO

MAY CHANGE FROM WILL BE CHANGING

LO TO HI LO TO HI

DON'T CARE CHANGING, STATE

UNKNOWN

OUTPUTS ONLY CENTER LINE IS

TRI-STATE

AI03102

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 45. DC Characteristics (5V devices)

Test Condition
Symbol Parameter (in addition to those in Min. Typ. Max. Unit
Table 39., page 76)
VIH Input High Voltage 4.5 V < VCC < 5.5 V 2 VCC +0.5 V
VIL Input Low Voltage 4.5 V < VCC < 5.5 V –0.5 0.8 V

VIH1 Reset High Level Input Voltage (Note 1) 0.8VCC VCC +0.5 V

VIL1 Reset Low Level Input Voltage (Note 1) –0.5 0.2VCC –0.1 V

VHYS Reset Pin Hysteresis 0.3 V

VCC (min) for Flash Erase and

VLKO 2.5 4.2 V
Program
IOL = 20µA, VCC = 4.5 V 0.01 0.1 V
VOL Output Low Voltage
IOL = 8mA, VCC = 4.5 V 0.25 0.45 V

Output High Voltage Except IOH = –20µA, VCC = 4.5 V 4.4 4.49 V
VOH
VSTBY On IOH = –2mA, VCC = 4.5 V 2.4 3.9 V

VOH1 Output High Voltage VSTBY On IOH1 = 1µA VSTBY – 0.8 V

VSTBY SRAM Stand-by Voltage 2.0 VCC V

ISTBY SRAM Stand-by Current VCC = 0 V 0.5 1 µA
IIDLE Idle Current (VSTBY input) VCC > VSTBY –0.1 0.1 µA
VDF SRAM Data Retention Voltage Only on VSTBY 2 V
Stand-by Supply Current
ISB
for Power-down Mode CSI >VCC –0.3 V (Notes 2,3) 50 200 µA

ILI Input Leakage Current VSS < VIN < VCC –1 ±0.1 1 µA
ILO Output Leakage Current 0.45 < VOUT < VCC –10 ±5 10 µA
PLD_TURBO = Off,
0 µA/PT
f = 0 MHz (Note 5)
PLD Only
PLD_TURBO = On,
400 700 µA/PT
ICC (DC) Operating f = 0 MHz
Supply
(Note 5) Current During Flash memory
15 30 mA
Flash memory WRITE/Erase Only
Read only, f = 0 MHz 0 0 mA
SRAM f = 0 MHz 0 0 mA

PLD AC Adder note 4

ICC (AC) mA/

Flash memory AC Adder 2.5 3.5
MHz
(Note 5)
mA/
SRAM AC Adder 1.5 3.0
MHz
Note: 1. Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.
2. CSI deselected or internal Power-down mode is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. Please see Figure 35., page 72 for the PLD current calculation.
5. IOUT = 0mA

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 46. DC Characteristics (3V devices)

Symbol Parameter Conditions Min. Typ. Max. Unit
VIH High Level Input Voltage 3.0 V < VCC < 3.6 V 0.7VCC VCC +0.5 V
VIL Low Level Input Voltage 3.0 V < VCC < 3.6 V –0.5 0.8 V

VIH1 Reset High Level Input Voltage (Note 1) 0.8VCC VCC +0.5 V

VIL1 Reset Low Level Input Voltage (Note 1) –0.5 0.2VCC –0.1 V

VHYS Reset Pin Hysteresis 0.3 V

VCC (min) for Flash Erase and

VLKO 1.5 2.2 V
Program
IOL = 20µA, VCC = 3.0 V 0.01 0.1 V
VOL Output Low Voltage
IOL = 4mA, VCC = 3.0 V 0.15 0.45 V

Output High Voltage Except IOH = –20µA, VCC = 3.0 V 2.9 2.99 V
VOH
VSTBY On IOH = –1mA, VCC = 3.0 V 2.7 2.8 V
VOH1 Output High Voltage VSTBY On IOH1 = 1µA VSTBY – 0.8 V

VSTBY SRAM Stand-by Voltage 2.0 VCC V

ISTBY SRAM Stand-by Current VCC = 0V 0.5 1 µA
IIDLE Idle Current (VSTBY input) VCC > VSTBY –0.1 0.1 µA
VDF SRAM Data Retention Voltage Only on VSTBY 2 V

Stand-by Supply Current

ISB
for Power-down Mode CSI >VCC –0.3 V (Notes 2,3) 25 100 µA

ILI Input Leakage Current VSS < VIN < VCC –1 ±0.1 1 µA
ILO Output Leakage Current 0.45 < VIN < VCC –10 ±5 10 µA
PLD_TURBO = Off,
0 µA/PT
f = 0 MHz (Note 3)
PLD Only
PLD_TURBO = On,
200 400 µA/PT
Operating f = 0 MHz
ICC (DC)
Supply
(Note 5) Current During Flash memory
10 25 mA
Flash memory WRITE/Erase Only
Read only, f = 0 MHz 0 0 mA
SRAM f = 0 MHz 0 0 mA

PLD AC Adder note 4

ICC (AC) mA/

Flash memory AC Adder 1.5 2.0
MHz
(Note 5)
mA/
SRAM AC Adder 0.8 1.5
MHz
Note: 1. Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.
2. CSI deselected or internal PD is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. Please see Figure 36., page 72 for the PLD current calculation.
5. IOUT = 0mA

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Figure 40. Input to Output Disable / Enable

INPUT

tER tEA

INPUT TO
OUTPUT
ENABLE/DISABLE

AI02863

Table 47. CPLD Combinatorial Timing (5V devices)

-70 -90 -15 Fast
Turbo Slew
Symbol Parameter Conditions PT Unit
Min Max Min Max Min Max Aloc
Off rate1

CPLD Input Pin/

tPD Feedback to CPLD 20 25 32 +2 + 10 –2 ns
Combinatorial Output
CPLD Input to CPLD
tEA 21 26 32 + 10 –2 ns
Output Enable
CPLD Input to CPLD
tER 21 26 32 + 10 –2 ns
Output Disable
CPLD Register Clear
tARP 21 26 33 + 10 –2 ns
or Preset Delay
CPLD Register Clear
tARPW 10 20 29 + 10 ns
or Preset Pulse Width
Any
tARD CPLD Array Delay 11 16 22 +2 ns
macrocell
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

Table 48. CPLD Combinatorial Timing (3V devices)

-12 -15 -20 PT Turbo Slew
Symbol Parameter Conditions Unit
Min Max Min Max Min Max Aloc Off rate1

CPLD Input Pin/

tPD Feedback to CPLD 40 45 50 +4 + 20 –6 ns
Combinatorial Output
CPLD Input to CPLD
tEA 43 45 50 + 20 –6 ns
Output Enable
CPLD Input to CPLD
tER 43 45 50 + 20 –6 ns
Output Disable
CPLD Register Clear
tARP or 40 43 48 + 20 –6 ns
Preset Delay
CPLD Register Clear
tARPW or 25 30 35 + 20 ns
Preset Pulse Width
Any
tARD CPLD Array Delay 25 29 33 +4 ns
macrocell
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Figure 41. Synchronous Clock Mode Timing – PLD

tCH tCL

CLKIN

tS tH

INPUT

tCO

REGISTERED
OUTPUT

AI02860

Table 49. CPLD Macrocell Synchronous Clock Mode Timing (5V devices)
-70 -90 -15 Fast
Turbo Slew
Symbol Parameter Conditions PT Unit
Min Max Min Max Min Max Aloc
Off rate1

Maximum
Frequency
1/(tS+tCO) 40.0 30.30 25.00 MHz
External
Feedback
Maximum
Frequency
fMAX
Internal 1/(tS+tCO–10) 66.6 43.48 31.25 MHz
Feedback
(fCNT)

Maximum
Frequency 1/(tCH+tCL) 83.3 50.00 35.71 MHz
Pipelined Data
Input Setup
tS 12 15 20 +2 + 10 ns
Time
tH Input Hold Time 0 0 0 ns
tCH Clock High Time Clock Input 6 10 15 ns
tCL Clock Low Time Clock Input 6 10 15 ns
Clock to Output
tCO Clock Input 13 18 22 –2 ns
Delay
CPLD Array
tARD Any macrocell 11 16 22 +2 ns
Delay
Minimum Clock
tMIN tCH+tCL 12 20 30 ns
Period 2
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL.

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Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices)
-12 -15 -20 PT Turbo Slew
Symbol Parameter Conditions Unit
Min Max Min Max Min Max Aloc Off rate1

Maximum
Frequency 1/(tS+tCO) 22.2 18.8 15.8 MHz
External Feedback
Maximum
Frequency
fMAX 1/(tS+tCO–10) 28.5 23.2 18.8 MHz
Internal Feedback
(fCNT)

Maximum
Frequency 1/(tCH+tCL) 40.0 33.3 31.2 MHz
Pipelined Data
tS Input Setup Time 20 25 30 +4 + 20 ns
tH Input Hold Time 0 0 0 ns
tCH Clock High Time Clock Input 15 15 16 ns
tCL Clock Low Time Clock Input 10 15 16 ns

Clock to Output
tCO Clock Input 25 28 33 –6 ns
Delay
tARD CPLD Array Delay Any macrocell 25 29 33 +4 ns

Minimum Clock
tMIN tCH+tCL 25 29 32 ns
Period2
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Figure 42. Asynchronous Reset / Preset

tARPW

RESET/PRESET
INPUT

tARP

REGISTER
OUTPUT

AI02864

Figure 43. Asynchronous Clock Mode Timing (product term clock)

tCHA tCLA

CLOCK

tSA tHA

INPUT

tCOA

REGISTERED
OUTPUT

AI02859

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices)
-70 -90 -15 PT Turbo Slew
Symbol Parameter Conditions Unit
Min Max Min Max Min Max Aloc Off Rate

Maximum
Frequency
1/(tSA+tCOA) 38.4 26.32 21.27 MHz
External
Feedback
Maximum
Frequency
fMAXA Internal 1/(tSA+tCOA–10) 62.5 35.71 27.78 MHz
Feedback
(fCNTA)

Maximum
Frequency
1/(tCHA+tCLA) 71.4 41.67 35.71 MHz
Pipelined
Data
Input Setup
tSA 7 8 12 +2 + 10 ns
Time
Input Hold
tHA 8 12 14 ns
Time
Clock Input
tCHA 9 12 15 + 10 ns
High Time
Clock Input
tCLA 9 12 15 + 10 ns
Low Time
Clock to
tCOA 21 30 37 + 10 –2 ns
Output Delay
CPLD Array
tARDA Any macrocell 11 16 22 +2 ns
Delay
Minimum
tMINA 1/fCNTA 16 28 39 ns
Clock Period

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Table 52. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices)
-12 -15 -20 PT Turbo Slew
Symbol Parameter Conditions Unit
Min Max Min Max Min Max Aloc Off Rate

Maximum
Frequency
1/(tSA+tCOA) 21.7 19.2 16.9 MHz
External
Feedback
Maximum
Frequency
fMAXA
Internal 1/(tSA+tCOA–10) 27.8 23.8 20.4 MHz
Feedback
(fCNTA)

Maximum
Frequency 1/(tCHA+tCLA) 33.3 27 24.4 MHz
Pipelined Data
Input Setup
tSA 10 12 13 +4 + 20 ns
Time
tHA Input Hold Time 12 15 17 ns
tCHA Clock High Time 17 22 25 + 20 ns
tCLA Clock Low Time 13 15 16 + 20 ns
Clock to Output
tCOA 36 40 46 + 20 –6 ns
Delay
CPLD Array
tARD Any macrocell 25 29 33 +4 ns
Delay
Minimum Clock
tMINA 1/fCNTA 36 42 49 ns
Period

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Figure 44. Input Macrocell Timing (product term clock)

t INH t INL

PT CLOCK

t IS t IH

INPUT

OUTPUT

t INO
AI03101

Table 53. Input Macrocell Timing (5V devices)

-70 -90 -15 PT Turbo
Symbol Parameter Conditions Unit
Min Max Min Max Min Max Aloc Off

tIS Input Setup Time (Note 1) 0 0 0 ns

tIH Input Hold Time (Note 1) 15 20 26 + 10 ns

tINH NIB Input High Time (Note 1) 9 12 18 ns

tINL NIB Input Low Time (Note 1) 9 12 18 ns

NIB Input to Combinatorial

tINO
Delay (Note 1) 34 46 59 +2 + 10 ns

Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX.

Table 54. Input Macrocell Timing (3V devices)

-12 -15 -20 PT Turbo
Symbol Parameter Conditions Unit
Min Max Min Max Min Max Aloc Off

tIS Input Setup Time (Note 1) 0 0 0 ns

tIH Input Hold Time (Note 1) 25 25 30 + 20 ns

tINH NIB Input High Time (Note 1) 12 13 15 ns

tINL NIB Input Low Time (Note 1) 12 13 15 ns

NIB Input to Combinatorial

tINO
Delay (Note 1) 46 62 70 +4 + 20 ns

Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX.

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Figure 45. READ Timing

tAVLX tLXAX
1

ALE /AS

tLVLX

A /D ADDRESS DATA
MULTIPLEXED VALID VALID
BUS tAVQV

ADDRESS
ADDRESS
NON-MULTIPLEXED
VALID
BUS

DATA DATA
NON-MULTIPLEXED VALID
BUS
tSLQV

CSI

tRLQV
tRHQX
tRLRH
RD
(PSEN, DS) tRHQZ

tEHEL
E
tTHEH tELTL

R/W

tAVPV

ADDRESS OUT
AI02895

Note: 1. tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 55. READ Timing (5V devices)

-70 -90 -15 Turbo
Symbol Parameter Conditions Unit
Min Max Min Max Min Max Off

tLVLX ALE or AS Pulse Width 15 20 28 ns

tAVLX Address Setup Time (Note 3) 4 6 10 ns

tLXAX Address Hold Time (Note 3) 7 8 11 ns

tAVQV Address Valid to Data Valid (Note 3) 70 90 150 + 10 ns

tSLQV CS Valid to Data Valid 75 100 150 ns

RD to Data Valid 8-Bit Bus (Note 5) 24 32 40 ns

tRLQV
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251 (Note 2) 31 38 45 ns

tRHQX RD Data Hold Time (Note 1) 0 0 0 ns

tRLRH RD Pulse Width (Note 1) 27 32 38 ns

tRHQZ RD to Data High-Z (Note 1) 20 25 30 ns

tEHEL E Pulse Width 27 32 38 ns

tTHEH R/W Setup Time to Enable 6 10 18 ns
tELTL R/W Hold Time After Enable 0 0 0 ns

Address Input Valid to

tAVPV
Address Output Delay (Note 4) 20 25 30 ns

Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing.
3. Any input used to select an internal PSD function.
4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 56. READ Timing (3V devices)

-12 -15 -20 Turbo
Symbol Parameter Conditions Unit
Min Max Min Max Min Max Off

tLVLX ALE or AS Pulse Width 26 26 30 ns

tAVLX Address Setup Time (Note 3) 9 10 12 ns

tLXAX Address Hold Time (Note 3) 9 12 14 ns

tAVQV Address Valid to Data Valid (Note 3) 120 150 200 + 20 ns

tSLQV CS Valid to Data Valid 120 150 200 ns

RD to Data Valid 8-Bit Bus (Note 5) 35 35 40 ns

tRLQV
RD or PSEN to Data Valid 8-Bit Bus,
8031, 80251 (Note 2) 45 50 55 ns

tRHQX RD Data Hold Time (Note 1) 0 0 0 ns

tRLRH RD Pulse Width 38 40 45 ns

tRHQZ RD to Data High-Z (Note 1) 38 40 45 ns

tEHEL E Pulse Width 40 45 52 ns

tTHEH R/W Setup Time to Enable 15 18 20 ns
tELTL R/W Hold Time After Enable 0 0 0 ns
Address Input Valid to
tAVPV
Address Output Delay (Note 4) 33 35 40 ns

Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing for 8031.
3. Any input used to select an internal PSD function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Figure 46. WRITE Timing

tAVLX t LXAX

ALE/AS

t LVLX
A/D ADDRESS DATA
MULTIPLEXED VALID VALID
BUS
tAVWL

ADDRESS
ADDRESS
NON-MULTIPLEXED
VALID
BUS

DATA DATA
NON-MULTIPLEXED VALID
BUS
tSLWL

CSI

tDVWH t WHDX
WR t WLWH
(DS) t WHAX

t EHEL
E
t THEH t ELTL

R/ W

t WLMV

tAVPV t WHPV

STANDARD
ADDRESS OUT MCU I/O OUT

AI02896

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 57. WRITE Timing (5V devices)

-70 -90 -15
Symbol Parameter Conditions Unit
Min Max Min Max Min Max
tLVLX ALE or AS Pulse Width 15 20 28 ns

tAVLX Address Setup Time (Note 1) 4 6 10 ns

tLXAX Address Hold Time (Note 1) 7 8 11 ns

Address Valid to Leading

tAVWL
Edge of WR (Notes 1,3) 8 15 20 ns

tSLWL CS Valid to Leading Edge of WR (Note 3) 12 15 20 ns

tDVWH WR Data Setup Time (Note 3) 25 35 45 ns

tWHDX WR Data Hold Time (Note 3) 4 5 5 ns

tWLWH WR Pulse Width (Note 3) 31 35 45 ns

tWHAX1 Trailing Edge of WR to Address Invalid (Note 3) 6 8 10 ns

Trailing Edge of WR to DPLD Address

tWHAX2
Invalid (Note 3,6) 0 0 0 ns

Trailing Edge of WR to Port Output

tWHPV
Valid Using I/O Port Data Register (Note 3) 27 30 38 ns

Data Valid to Port Output Valid

tDVMV Using Macrocell Register (Notes 3,5) 42 55 65 ns
Preset/Clear
Address Input Valid to Address
tAVPV
Output Delay (Note 2) 20 25 30 ns

WR Valid to Port Output Valid Using

tWLMV
Macrocell Register Preset/Clear (Notes 3,4) 48 55 65 ns

Note: 1. Any input used to select an internal PSD function.

2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.

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Table 58. WRITE Timing (3V devices)

-12 -15 -20
Symbol Parameter Conditions Unit
Min Max Min Max Min Max
tLVLX ALE or AS Pulse Width 26 26 30

tAVLX Address Setup Time (Note 1) 9 10 12 ns

tLXAX Address Hold Time (Note 1) 9 12 14 ns

Address Valid to Leading

tAVWL
Edge of WR (Notes 1,3) 17 20 25 ns

tSLWL CS Valid to Leading Edge of WR (Note 3) 17 20 25 ns

tDVWH WR Data Setup Time (Note 3) 45 45 50 ns

tWHDX WR Data Hold Time (Note 3) 7 8 10 ns

tWLWH WR Pulse Width (Note 3) 46 48 53 ns

tWHAX1 Trailing Edge of WR to Address Invalid (Note 3) 10 12 17 ns

Trailing Edge of WR to DPLD Address

tWHAX2
Invalid (Note 3,6) 0 0 0 ns

Trailing Edge of WR to Port Output

tWHPV
Valid Using I/O Port Data Register (Note 3) 33 35 40 ns

Data Valid to Port Output Valid

tDVMV
Using Macrocell Register Preset/Clear (Notes 3,5) 70 70 80 ns

Address Input Valid to Address

tAVPV
Output Delay (Note 2) 33 35 40 ns

WR Valid to Port Output Valid Using

tWLMV
Macrocell Register Preset/Clear (Notes 3,4) 70 70 80 ns

Note: 1. Any input used to select an internal PSD function.

2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.

Table 59. Program, WRITE and Erase Times (5V devices)

Symbol Parameter Min. Typ. Max. Unit
Flash Program 8.5 s
1 3 30 s
Flash Bulk Erase (pre-programmed)
Flash Bulk Erase (not pre-programmed) 5 s
tWHQV3 Sector Erase (pre-programmed) 1 30 s
tWHQV2 Sector Erase (not pre-programmed) 2.2 s
tWHQV1 Byte Program 14 1200 µs
Program / Erase Cycles (per Sector) 100,000 cycles
tWHWLO Sector Erase Time-Out 100 µs
tQ7VQV DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)2 30 ns
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 60. Program, WRITE and Erase Times (3V devices)

Symbol Parameter Min. Typ. Max. Unit
Flash Program 8.5 s

Flash Bulk Erase1 (pre-programmed) 3 30 s

Flash Bulk Erase (not pre-programmed) 5 s
tWHQV3 Sector Erase (pre-programmed) 1 30 s
tWHQV2 Sector Erase (not pre-programmed) 2.2 s
tWHQV1 Byte Program 14 1200 µs
Program / Erase Cycles (per Sector) 100,000 cycles
tWHWLO Sector Erase Time-Out 100 µs
tQ7VQV 2 30 ns
DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Figure 47. Peripheral I/O READ Timing

ALE/AS

A/D BUS ADDRESS DATA VALID

tAVQV (PA)

tSLQV (PA)

CSI

tRLQV (PA) tQXRH (PA)

tRHQZ (PA)
RD tRLRH (PA)

tDVQV (PA)

DATA ON PORT A

AI02897

Table 61. Port A Peripheral Data Mode READ Timing (5V devices)
-70 -90 -15 Turbo
Symbol Parameter Conditions Unit
Min Max Min Max Min Max Off

Address Valid to Data

tAVQV–PA
Valid (Note 3) 37 39 45 + 10 ns

tSLQV–PA CSI Valid to Data Valid 27 35 45 + 10 ns

RD to Data Valid (Notes 1,4) 21 32 40 ns

tRLQV–PA
RD to Data Valid 8031 Mode 32 38 45 ns
tDVQV–PA Data In to Data Out Valid 22 30 38 ns
tQXRH–PA RD Data Hold Time 0 0 0 ns

tRLRH–PA RD Pulse Width (Note 1) 27 32 38 ns

tRHQZ–PA RD to Data High-Z (Note 1) 23 25 30 ns

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Table 62. Port A Peripheral Data Mode READ Timing (3V devices)
-12 -15 -20 Turbo
Symbol Parameter Conditions Unit
Min Max Min Max Min Max Off

tAVQV–PA Address Valid to Data Valid (Note 3) 50 50 50 + 20 ns

tSLQV–PA CSI Valid to Data Valid 37 45 50 + 20 ns

RD to Data Valid (Notes 1,4) 37 40 45 ns

tRLQV–PA
RD to Data Valid 8031 Mode 45 45 50 ns
tDVQV–PA Data In to Data Out Valid 38 40 45 ns
tQXRH–PA RD Data Hold Time 0 0 0 ns

tRLRH–PA RD Pulse Width (Note 1) 36 36 46 ns

tRHQZ–PA RD to Data High-Z (Note 1) 36 40 45 ns

Figure 48. Peripheral I/O WRITE Timing

ALE/AS

A / D BUS ADDRESS DATA OUT

tWLQV (PA) tWHQZ (PA)

WR

tDVQV (PA)

PORT A
DATA OUT

AI02898

Table 63. Port A Peripheral Data Mode WRITE Timing (5V devices)
-70 -90 -15
Symbol Parameter Conditions Unit
Min Max Min Max Min Max

tWLQV–PA WR to Data Propagation Delay (Note 2) 25 35 40 ns

tDVQV–PA Data to Port A Data Propagation Delay (Note 5) 22 30 38 ns

tWHQZ–PA WR Invalid to Port A Tri-state (Note 2) 20 25 33 ns

Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.

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Table 64. Port A Peripheral Data Mode WRITE Timing (3V devices)
-12 -15 -20
Symbol Parameter Conditions Unit
Min Max Min Max Min Max

tWLQV–PA WR to Data Propagation Delay (Note 2) 42 45 55 ns

tDVQV–PA Data to Port A Data Propagation Delay (Note 5) 38 40 45 ns

tWHQZ–PA WR Invalid to Port A Tri-state (Note 2) 33 33 35 ns

Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.

Figure 49. Reset (RESET) Timing

VCC VCC(min)

tNLNH
tNLNH-PO tOPR tNLNH-A tOPR
Power-On Reset Warm Reset

RESET

AI02866b

Table 65. Reset (RESET) Timing (5V devices)

Symbol Parameter Conditions Min Max Unit

tNLNH RESET Active Low Time 1 150 ns

tNLNH–PO Power On Reset Active Low Time 1 ms

tNLNH–A Warm Reset (on the PSD834Fx) 2 25 µs

tOPR RESET High to Operational Device 120 ns

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

Table 66. Reset (RESET) Timing (3V devices)

Symbol Parameter Conditions Min Max Unit

tNLNH RESET Active Low Time 1 300 ns

tNLNH–PO Power On Reset Active Low Time 1 ms

tNLNH–A Warm Reset (on the PSD834Fx) 2 25 µs

tOPR RESET High to Operational Device 300 ns

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 67. VSTBYON Timing (5V devices)

Symbol Parameter Conditions Min Typ Max Unit

tBVBH VSTBY Detection to VSTBYON Output High (Note 1) 20 µs

VSTBY Off Detection to VSTBYON Output

tBXBL
Low (Note 1) 20 µs

Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.

Table 68. VSTBYON Timing (3V devices)

Symbol Parameter Conditions Min Typ Max Unit

tBVBH VSTBY Detection to VSTBYON Output High (Note 1) 20 µs

VSTBY Off Detection to VSTBYON Output

tBXBL
Low (Note 1) 20 µs

Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.

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Figure 50. ISC Timing

t ISCCH

TCK

t ISCCL

t ISCPSU t ISCPH

TDI/TMS

t ISCPZV
t ISCPCO

ISC OUTPUTS/TDO

t ISCPVZ

ISC OUTPUTS/TDO

AI02865

Table 69. ISC Timing (5V devices)

-70 -90 -15
Symbol Parameter Conditions Unit
Min Max Min Max Min Max
Clock (TCK, PC1) Frequency (except for
tISCCF
PLD) (Note 1) 20 18 14 MHz

Clock (TCK, PC1) High Time (except for

tISCCH
PLD) (Note 1) 23 26 31 ns

Clock (TCK, PC1) Low Time (except for

tISCCL
PLD) (Note 1) 23 26 31 ns

tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2) 2 2 2 MHz

tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2) 240 240 240 ns

tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2) 240 240 240 ns

tISCPSU ISC Port Set Up Time 7 8 10 ns

tISCPH ISC Port Hold Up Time 5 5 5 ns
tISCPCO ISC Port Clock to Output 21 23 25 ns
tISCPZV ISC Port High-Impedance to Valid Output 21 23 25 ns
ISC Port Valid Output to
tISCPVZ 21 23 25 ns
High-Impedance
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 70. ISC Timing (3V devices)

-12 -15 -20
Symbol Parameter Conditions Unit
Min Max Min Max Min Max
Clock (TCK, PC1) Frequency (except for
tISCCF
PLD) (Note 1) 12 10 9 MHz

Clock (TCK, PC1) High Time (except for

tISCCH
PLD) (Note 1) 40 45 51 ns

Clock (TCK, PC1) Low Time (except for

tISCCL
PLD) (Note 1) 40 45 51 ns

tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2) 2 2 2 MHz

tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2) 240 240 240 ns

tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2) 240 240 240 ns

tISCPSU ISC Port Set Up Time 12 13 15 ns

tISCPH ISC Port Hold Up Time 5 5 5 ns
tISCPCO ISC Port Clock to Output 30 36 40 ns
tISCPZV ISC Port High-Impedance to Valid Output 30 36 40 ns

ISC Port Valid Output to

tISCPVZ 30 36 40 ns
High-Impedance
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.

Table 71. Power-down Timing (5V devices)

-70 -90 -15
Symbol Parameter Conditions Unit
Min Max Min Max Min Max
tLVDV ALE Access Time from Power-down 80 90 150 ns
Maximum Delay from
Using CLKIN
tCLWH APD Enable to Internal PDN Valid
(PD1) 15 * tCLCL1 µs
Signal
Note: 1. tCLCL is the period of CLKIN (PD1).

Table 72. Power-down Timing (3V devices)

-12 -15 -20
Symbol Parameter Conditions Unit
Min Max Min Max Min Max
tLVDV ALE Access Time from Power-down 145 150 200 ns
Maximum Delay from APD Enable to Using CLKIN
tCLWH
Internal PDN Valid Signal (PD1) 15 * tCLCL1 µs

Note: 1. tCLCL is the period of CLKIN (PD1).

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PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

PACKAGE MECHANICAL

Figure 51. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing
D

D1

D2 A2

Ne E2 E1 E

b
N
1

Nd A
CP
L1

c
QFP-A A1 α L

Note: Drawing is not to scale.

100/110
 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 73. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 2.35 0.093
A1 0.25 0.010
A2 2.00 1.80 2.10 0.079 0.077 0.083
b 0.22 0.38 0.009 0.015
c 0.11 0.23 0.004 0.009
D 13.20 13.15 13.25 0.520 0.518 0.522
D1 10.00 9.95 10.05 0.394 0.392 0.396
D2 7.80 – – 0.307 – –
E 13.20 13.15 13.25 0.520 0.518 0.522
E1 10.00 9.95 10.05 0.394 0.392 0.396
E2 7.80 – – 0.307 – –
e 0.65 – – 0.026
L 0.88 0.73 1.03 0.035 0.029 0.041
L1 1.60 – – 0.063
α 0° 7° 0° 7°
N 52 52
Nd 13 13
Ne 13 13
CP 0.10 0.004

101/110
PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Figure 52. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing
D A1
D1 A2 M1
M
1 N
b1

E1 E D2/E2 D3/E3 e
b

L1
L

C
A

CP
PLCC-B

Note: Drawing is not to scale.

Table 74. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions
mm inches
Symbol
Typ. Min. Max. Typ. Min. Max.
A 4.19 4.57 0.165 0.180
A1 2.54 2.79 0.100 0.110
A2 – 0.91 – 0.036
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
C 0.246 0.261 0.0097 0.0103
D 19.94 20.19 0.785 0.795
D1 19.05 19.15 0.750 0.754
D2 17.53 18.54 0.690 0.730
E 19.94 20.19 0.785 0.795
E1 19.05 19.15 0.750 0.754
E2 17.53 18.54 0.690 0.730
e 1.27 – – 0.050 – –
R 0.89 – – 0.035 – –
N 52 52
Nd 13 13
Ne 13 13

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Figure 53. TQFP64 - 64-lead Thin Quad Flatpack, Package Outline

D1

D2 A2

Ne E2 E1 E

b
N
1

Nd A
CP
L1

c
QFP-A A1 α L

Note: Drawing is not to scale.

103/110
PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

Table 75. TQFP64 - 64-lead Thin Quad Flatpack, Package Mechanical Data
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 1.42 1.54 0.056 0.061
A1 0.10 0.07 0.14 0.004 0.003 0.005
A2 1.40 1.36 1.44 0.055 0.054 0.057
α 3.5° 0.0° 7.0° 3.5° 0.0° 7.0°
b 0.35 0.33 0.38 0.014 0.013 0.015
c 0.17 0.006
D 16.00 15.90 16.10 0.630 0.626 0.634
D1 14.00 13.98 14.03 0.551 0.550 0.552
D2 12.00 11.95 12.05 0.472 0.470 0.474
E 16.00 15.90 16.10 0.630 0.626 0.634
E1 14.00 13.98 14.03 0.551 0.550 0.552
E2 12.00 11.95 12.05 0.472 0.470 0.474
e 0.80 0.75 0.85 0.031 0.030 0.033
L 0.60 0.45 0.75 0.024 0.018 0.030
L1 1.00 0.94 1.06 0.039 0.037 0.042
CP 0.10 0.004
N 64 64
Nd 16 16
Ne 16 16

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 PSD813F2V, PSD833F2V, PSD853F2V, PSD854F2V

PART NUMBERING

Table 76. Ordering Information Scheme

Example: PSD8 1 3 F 2 V – 15 J 1 T

Device Type
PSD8 = 8-bit PSD with Register Logic
PSD9 = 8-bit PSD with Combinatorial Logic

SRAM Capacity
1 = 16 Kbit
3 = 64 Kbit
5 = 256 Kbit

Flash Memory Capacity

3 = 1 Mbit (128K x 8)
4 = 2 Mbit (256K x 8)

2nd Flash Memory

2 = 256 Kbit Flash memory + SRAM
3 = SRAM but no Flash memory
4 = 256 Kbit Flash memory but no SRAM
5 = no Flash memory + no SRAM

Operating Voltage
blank = VCC = 4.5 to 5.5V
V = VCC = 3.0 to 3.6V

Speed
70 = 70ns
90 = 90ns
12 = 120ns
15 = 150ns
20 = 200ns

Package
J = PLCC52
M = PQFP52
U = TQFP64

Temperature Range
blank = 0 to 70°C (commercial)
I = –40 to 85°C (industrial)

Option
T = Tape & Reel Packing

For a list of available options (e.g., speed, package) or for further information on any aspect of this device,
please contact your nearest ST Sales Office.

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APPENDIX A. PQFP52 PIN ASSIGNMENTS

Table 77. PQFP52 Connections (Figure 2)

Pin Number Pin Assignments Pin Number Pin Assignments
1 PD2 27 AD4
2 PD1 28 AD5
3 PD0 29 AD6
4 PC7 30 AD7
5 PC6 31 VCC
6 PC5 32 AD8
7 PC4 33 AD9
8 VCC 34 AD10
9 GND 35 AD11
10 PC3 36 AD12
11 PC2 37 AD13
12 PC1 38 AD14
13 PC0 39 AD15
14 PA7 40 CNTL0
15 PA6 41 RESET
16 PA5 42 CNTL2
17 PA4 43 CNTL1
18 PA3 44 PB7
19 GND 45 PB6
20 PA2 46 GND
21 PA1 47 PB5
22 PA0 48 PB4
23 AD0 49 PB3
24 AD1 50 PB2
25 AD2 51 PB1
26 AD3 52 PB0

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APPENDIX B. PLCC52 PIN ASSIGNMENTS

Table 78. PLCC52 Connections (Figure 3)

Pin Number Pin Assignments Pin Number Pin Assignments
1 GND 27 PA2
2 PB5 28 PA1
3 PB4 29 PA0
4 PB3 30 AD0
5 PB2 31 AD1
6 PB1 32 AD2
7 PB0 33 AD3
8 PD2 34 AD4
9 PD1 35 AD5
10 PD0 36 AD6
11 PC7 37 AD7
12 PC6 38 VCC
13 PC5 39 AD8
14 PC4 40 AD9
15 VCC 41 AD10
16 GND 42 AD11
17 PC3 43 AD12

18 PC2 (VSTBY) 44 AD13

19 PC1 45 AD14

20 PC0 46 AD15

21 PA7 47 CNTL0

22 PA6 48 RESET

23 PA5 49 CNTL2

24 PA4 50 CNTL1

25 PA3 51 PB7

26 GND 52 PB6

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APPENDIX C. TQFP64 PIN ASSIGNMENTS

Table 79. TQFP64 Connections (Figure 4)

Pin Number Pin Assignments Pin Number Pin Assignments
1 PD2 33 AD3
2 PD1 34 AD4
3 PD0 35 AD5
4 PC7 36 AD6
5 PC6 37 AD7
6 PC5 38 VCC
7 VCC 39 VCC

8 VCC 40 AD8
9 VCC 41 AD9

10 GND 42 AD10

11 GND 43 AD11

12 PC3 44 AD12

13 PC2 45 AD13
14 PC1 46 AD14
15 PC0 47 AD15
16 NC 48 CNTL0
17 NC 49 NC
18 NC 50 RESET
19 PA7 51 CNTL2
20 PA6 52 CNTL1
21 PA5 53 PB7
22 PA4 54 PB6
23 PA3 55 GND
24 GND 56 GND
25 GND 57 PB5
26 PA2 58 PB4
27 PA1 59 PB3
28 PA0 60 PB2
29 AD0 61 PB1
30 AD1 62 PB0
31 N/D 63 NC
32 AD2 64 NC

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REVISION HISTORY

Table 80. Document Revision History

Date Version Description of Revision
04-Jun-04 1.0 First Edition (3V split from original)

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