電子學（二）/ (Microelectronics II)

Chapter 8: Differential and Multistage Amplifiers

Instructor: Prof. Che-Wei LIN (林哲偉)

November 2023
 Introduction

IN THIS CHAPTER YOU WILL LEARN:

The essence of the operation of the MOS and the bipolar differential amplifiers: how they reject
common-mode noise or interference and amplify differential signals.

The analysis and design of MOS and BJT differential amplifiers.

Differential amplifier circuits of varying complexity; utilizing passive resistive loads, current-source
loads, and cascodes - the building blocks studied in previous chapter.

An ingenious and highly popular differential-amplifier circuit that utilizes a current-mirror load.

The structure, analysis, and design of amplifiers composed of two or more stages in cascade.

Two practical examples are studied in detail: a two-stage CMOS op-amp and four-stage bipolar op-
amp.

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 Introduction

The differential-pair of differential-amplifier configuration is widely used in IC circuit design.

One example is input stage of OP-amp.

Another example is emitter-coupled logic (ECL).

Technology was invented in 1940’s for use in vacuum tubes – the basic differential-amplifier
configuration was later implemented with discrete bipolar transistors.

However, the configuration became most useful with invention of modern transistor / MOS
technologies.

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 8.1. The MOS Differential Pair

Figure 8.1: MOS differential-pair configuration.

Two matched transistors (Q1 and Q2) joined and biased by a constant current source I.

FET’s should not enter triode region of operation.

Figure 8.1 The basic MOS differential-pair configuration.

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 8.1.1. Operation with a Common-Mode Input Voltage

Consider case when two gate terminals are joined together.

Connected to a common-mode voltage (VCM).

𝑣𝐺1 = 𝑣𝐺2 = 𝑉𝐶𝑀

Q1 and Q2 are matched.

Current I will divide equally between the two transistors.

𝐼𝐷1 = 𝐼𝐷2 = 𝐼 Τ2 , 𝑉𝑆 = 𝑉𝐶𝑀 − 𝑉𝐺𝑆 (8.1)

where VGS is the gate-to-source voltage.

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 8.1.1. Operation with a Common-Mode Input Voltage

𝐼 1 ′𝑊 2
(8.2) = 𝑘 𝑉 − 𝑉𝑡
2 2 𝑛 𝐿 𝐺𝑆
Equations (8.2) through (8.8) describe this system,
(8.3) 𝑉𝑂𝑉 = 𝑉𝐺𝑆 − 𝑉𝑡
if channel-length modulation is neglected.
𝐼 1 ′𝑊 2
(8.4) = 𝑘 𝑉
Note specification of input common-mode 2 2 𝑛 𝐿 𝑂𝑉

range (VCM).
𝐼 𝑊
(8.5) 𝑉𝑂𝑉 =
𝑘𝑛′ 𝐿

𝐼
(8.6) 𝑣𝐷1 = 𝑣𝐷2 = 𝑉𝐷𝐷 − 𝑅𝐷
2
𝐼
8.7 𝑉𝐶𝑀𝑚𝑎𝑥 = 𝑉𝑡 + 𝑉𝐷𝐷 − 𝑅𝐷
2
(8.8)𝑉𝐶𝑀𝑚𝑖𝑛 = −𝑉𝑆𝑆 + 𝑉𝐶𝑆 + 𝑉𝑡 + 𝑉OV
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8.1.1. Operation with a Common-Mode Input Voltage

Figure 8.2 The MOS differential pair with a common-mode input voltage VCM.

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 8.1.2. Operation with a Differential Input Voltage

If vid is applied to Q1 and Q2 is grounded, following conditions apply:

vid = vGS1 – vGS2 > 0

iD1 > iD2

The opposite applies if Q2 is grounded etc.

The differential pair responds to a difference-mode or differential input signals.

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 8.1.2. Operation with a Differential Input Voltage
1 𝑊
(8.9) 𝐼 = 2 𝑘𝑛′ 𝐿
𝑣𝐺𝑆1 − 𝑉𝑡 2

2𝐼
as 𝑣𝐺𝑆1 = 𝑉𝑡 + ′ 𝑊
𝑘𝑛
𝐿

= 𝑉𝑡 + 2𝑉𝑂𝑉
(8.10) 𝑣𝑖𝑑max = VGS + 𝑣𝑠 = 2𝑂𝑉

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 8.1.2. Operation with a Differential Input Voltage

Two input terminals connected to a suitable dc voltage VCM.

Bias current I of a “perfectly” symmetrical differential pair divides equally.

Zero voltage differential between the two drains (collectors).

To steer the current completely to one side of the pair, a difference input
voltage vid of at least 2VOV (4VT for bipolar) is needed.

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 8.1.3. Large-Signal Operation

Objective is to derive expressions for drain current iD1 and iD2 in terms of
differential signal vid = vG1 – vG2.

Assumptions:
Perfectly Matched

Channel-length Modulation is Neglected

Load Independence

Saturation Region

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 8.1.3. Large-Signal Operation
1 ′𝑊 2
(8.11) 𝑖𝐷1 = 𝑘 𝑣 − 𝑉𝑡
2 𝑛 𝐿 𝐺𝑆1
step #1: Expression drain currents 1 𝑊
(8.12) 𝑖𝐷2 = 𝑘𝑛′ 𝑣 − 𝑉𝑡 2
for Q1 and Q2. 2 𝐿 𝐺𝑆2
−−−−−−−−−−−−−−−− −
step #2: Take the square roots of 1 ′𝑊
(8.13) 𝑖𝐷1 = 𝑘 𝑣 − 𝑉𝑡
both sides of both (8.11) and (8.12) 2 𝑛 𝐿 𝐺𝑆1
step #3: Subtract (8.14) from (8.15) 1 ′𝑊
(8.14) 𝑖𝐷2 = 𝑘 𝑣 − 𝑉𝑡
and perform appropriate 2 𝑛 𝐿 𝐺𝑆2

substitution. −−−−−−−−−−−−−−−− −
(8.15) 𝑣𝐺𝑆1 − 𝑣𝐺𝑆2 = 𝑣𝐺1 − 𝑣𝐺2 = 𝑣𝑖𝑑
step #4: Note the constant-current 1 ′𝑊
(8.16) 𝑖𝐷1 − 𝑖𝐷2 = 𝑘 𝑣
bias constraint. 2 𝑛 𝐿 𝑖𝑑

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 8.1.3. Large-Signal Operation

step #5: Simplify (8.15). (8.17) 𝑖𝐷1 + 𝑖𝐷2 = 𝐼

−−−−−−−−−−−−−−−−−−−−−− −
step #6: Incorporate the constant- 1 𝑊 2
(8.17) 2 𝑖𝐷1 𝑖𝐷2 = 𝐼 − 𝑘𝑛′ 𝑣
current bias. 2 𝐿 𝑖𝑑
−−−−−−−−−−−−−−−−−−−−−− −
step #7: Solve (8.16) and (8.17) 𝐼 𝐼 𝑣𝑖𝑑 𝑣𝑖𝑑 /2
2
(8.23) 𝑖𝐷1 = + 1−
for the two unknowns – iD1 and iD2. 2 𝑉𝑂𝑉 2 𝑉𝑂𝑉
Refer to (8.23) and (8.24). 2
𝐼 𝐼 𝑣𝑖𝑑 𝑣𝑖𝑑 /2
(8.24) 𝑖𝐷2 = − 1−
2 𝑉𝑂𝑉 2 𝑉𝑂𝑉

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8.1.3. Large-Signal Operation

Figure 8.6 Normalized plots of the currents in a

MOSFET differential pair. Note that VOV is the
overdrive voltage at which Q1 and Q2 operate
when conducting drain currents equal to I/2, the
equilibrium situation. Note that these graphs are
universal and apply to any MOS differential pair.

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 8.1.3. Large-Signal Operation

Transfer characteristics of (8.23)

Small signal approximation
and (8.24) are nonlinear.
𝐼 𝐼 𝑣𝑖𝑑
(8.25) 𝑖𝐷1 ≅ 2 +
Linear amplification is desirable 𝑉𝑜𝑣 2

and vid will be as small as possible. 𝐼 𝐼 𝑣𝑖𝑑

(8.26) 𝑖𝐷1 ≅ 2 − 𝑉𝑜𝑣 2
For a given value of VOV, the only
𝐼 𝑣𝑖𝑑
(8.27) 𝑖𝑑 =
option is to keep vid/2 much smaller 𝑉𝑜𝑣 2

than VOV.

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8.1.3. Large-Signal Operation

Figure 8.7 The linear range of operation of the MOS differential pair can
be extended by operating the transistor at a higher value of VOV.

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 8.1.4. Small-Signal Operation

Figure 8.8 Small-signal analysis of the MOS differential amplifier. (a) The circuit with a common-mode voltage applied to
set the dc bias voltage at the gates and with vid applied in a complementary (or balanced) manner. (b) The circuit prepared
for small-signal analysis. (c) An alternative way of looking at the smallsignal operation of the circuit.

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 8.1.4. Small-Signal Operation
Differential Gain
1
Two reasons single-ended (8.28) 𝑣𝐺1 = 𝑉𝐶𝑀 + 𝑣𝑖𝑑
2
amplifiers are preferable: 1
(8.29) 𝑣𝐺2 = 𝑉𝐶𝑀 − 𝑣𝑖𝑑
2
Insensitive to interference. −−−−−−−−−−−−−−−− −
2𝐼𝐷 2(𝐼/2) 𝐼
(8.30) 𝑔𝑚 = = =
Do not need bypass coupling 𝑉𝑂𝑉 𝑉𝑂𝑉 𝑉𝑂𝑉
−−−−−−−−−−−−−−−− −
capacitors. 𝑣𝑖𝑑
(8.31) 𝑣𝑜1 = −𝑔𝑚 𝑅
2 𝐷
𝑣𝑖𝑑
(8.32) 𝑣𝑜2 = +𝑔𝑚 𝑅
2 𝐷
−−−−−−−−−−−−−−−− −
𝑣𝑜𝑑
(8.35) 𝐴𝑑 ≡ = 𝑔𝑚 𝑅𝐷
𝑣𝑖𝑑

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 8.1.4. Small-Signal Operation
Differential Gain
1
For MOS pair, each device operates with (8.28) 𝑣𝐺1 = 𝑉𝐶𝑀 + 𝑣𝑖𝑑
2
drain current I/2 and corresponding 1
(8.29) 𝑣𝐺2 = 𝑉𝐶𝑀 − 𝑣𝑖𝑑
2
overdrive voltage (VOV). −−−−−−−−−−−−−−−− −
2𝐼𝐷 2(𝐼/2) 𝐼
(8.30) 𝑔𝑚 = = =
a=1 𝑉𝑂𝑉 𝑉𝑂𝑉 𝑉𝑂𝑉
−−−−−−−−−−−−−−−− −
MOS: gm = I/VOV 𝑣𝑖𝑑
(8.31) 𝑣𝑜1 = −𝑔𝑚 𝑅
2 𝐷
BJT: gm = aI/2VT (8.32) 𝑣𝑜2 = +𝑔𝑚
𝑣𝑖𝑑
𝑅
2 𝐷
MOS: ro = |VA|/(I/2). −−−−−−−−−−−−−−−− −
𝑣𝑜𝑑
(8.35) 𝐴𝑑 ≡ = 𝑔𝑚 𝑅𝐷
𝑣𝑖𝑑

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 8.1.4. Small-Signal Operation
Differential Gain
vi1 = VCM + vid/2 and vi2 = VCM – vid/2 causes a virtual signal ground to
appear on the common-source (common-emitter) connection

Current in Q1 increases by gmvid/2 and the current in Q2 decreases by

gmvid/2.

Voltage signals of gm(RD||ro)vid/2 develop at the two drains (collectors,

with RD replaced by RC).

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 8.1.4. Small-Signal Operation
The Differential Half-Circuit

Figure 8.9 An alternative view of the small-signal differential operation of the MOS differential
pair: (a) analysis done directly on the circuit; (b) analysis using equivalent-circuit models.

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 8.1.4. Small-Signal Operation
The Differential Half-Circuit
Figure 8.10 (right): The equivalent
differential half-circuit of the differential
amplifier of Figure 8.8.

Here Q1 is biased at I/2 and is operating

at VOV.

This circuit may be used to determine the

differential voltage gain of the differential
amplifier Ad = vod/vid.

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 8.1.5. The Differential Amplifier with
Current-Source Loads
To obtain higher gain, the passive resistances (RD) can be replaced with current
sources.

Ad = gm1(ro1||ro3)

Figure 8.12 (a) Differential amplifier with

current-source loads formed by Q3 and Q4. (b)
Differential half-circuit of the amplifier in (a).

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 8.1.6. Cascode Differential Amplifier

Gain can be increased via

cascode configuration –
discussed in Section 7.5.

𝑣𝑜𝑑
(8.38) 𝐴𝑑 ≡ = 𝑔𝑚1 (𝑅𝑜𝑛 ቛ𝑅𝑜𝑝 )
𝑣𝑖𝑑
(8.39) 𝑅𝑜𝑛 = (𝑔𝑚3 𝑟𝑜3 )𝑟𝑜1
(8.40) 𝑅𝑜𝑝 = (𝑔𝑚5 𝑟𝑜5 )𝑟𝑜7
Figure 8.13 (a) Cascode differential amplifier; and
(b) its differential half-circuit.
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 8.2. The BJT Differential Pair

Figure 8.14 shows the basic BJT

differential-pair configuration.

It is similar to the MOSFET

circuit – composed of two
matched transistors biased by a
constant-current source – and
is modeled by many similar
Figure 8.14 The basic BJT differential-
expressions. pair configuration.

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 8.2.1. Basic Operation

To see how the BJT differential pair

works, consider the first case of the two
bases joined together and connected to
a common-mode voltage VCM.

Since Q1 and Q2 are matched, and

assuming an ideal bias current I with
infinite output resistance, this current
Figure 8.15: Different modes of operation of the BJT differential pair: (a)
will flow equally through both transistors. the differential pair with a common-mode input voltage VCM; (b) the
differential pair with a “large” differential input signal; (c) the differential
pair with a large differential input signal of polarity opposite to that in (b);
(d) the differential pair with a small differential input signal vi. Note that
we have assumed the bias current source I to be ideal.

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Figure 8.15: Different modes of operation of the BJT
differential pair:
(a) the differential pair with a common-mode input
voltage VCM;
(b) the differential pair with a “large” differential input
signal;
(c) the differential pair with a large differential input
signal of polarity opposite to that in (b);
(d) the differential pair with a small differential input
signal vi. Note that we have assumed the bias current
source I to be ideal.

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 8.2.2. Input Common-Mode Range

Refer to the circuit in Figure 8.15(a).

The allowable range of VCM is determined at the upper end by Q1 and Q2 leaving
the active mode and entering saturation.

Equations (8.41) and (8.45) define the minimum and maximum common-mode
input voltages.

𝐼
(8.41) 𝑉𝐶𝑀 max ≅ 𝑉𝐶 + 0.4 = 𝑉𝐶𝐶 − 𝛼 2 𝑅𝐶 + 0.4

(8.42) 𝑉𝐶𝑀 min ≅ −𝑉𝐸𝐸 + 𝑉𝐶𝑆 + 𝑉𝐵𝐸

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8.2.3 Large-Signal Operation
𝐼𝑆 (𝑣 −𝑣 )/𝑉
(8.43)𝑖𝐸1 = 𝑒 𝐵1 𝐸 𝑇 (8.47) 𝑖𝐸1 + 𝑖𝐸2 = 𝐼
𝛼
1
𝐼𝑆 (𝑣 −𝑣 )/𝑉 (8.48) 𝑖𝐸1 =
(8.44)𝑖𝐸2 = 𝑒 𝐵2 𝐸 𝑇 1 + 𝑒 −𝑣𝑖𝑑/𝑣𝑇
𝛼
1
𝑖𝐸1 (8.49) 𝑖𝐸2 =
= 𝑒 (𝑣𝐵1 −𝑣𝐵2 )/𝑉𝑇 1 + 𝑒 𝑣𝑖𝑑/𝑣𝑇
𝑖𝐸2

𝑖𝐸1 1
(8.45) =
𝑖𝐸1 + 𝑖𝐸2 1 + 𝑒 (𝑣𝐵2 −𝑣𝐸)/𝑉𝑇

𝑖𝐸2 1
(8.46) =
𝑖𝐸1 + 𝑖𝐸2 1 + 𝑒 (𝑣𝐵1 −𝑣𝐸)/𝑉𝑇

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8.2.3 Large-Signal Operation

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8.2.3 Large-Signal Operation

Figure 8.17 The transfer characteristics of the BJT differential pair (a) can be linearized (b) (i.e., the
linear range of operation can be extended) by including resistances in the emitters.

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8.2.4 Small-Signal Operation

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8.2.4 Small-Signal Operation
The Collector Currents When vid is Applied
𝛼𝐼 𝛼𝐼 𝛼𝐼 𝑣𝑖𝑑
8.50 𝑖𝐶1 = (8.53) 𝑖𝐶2 = −
1 + 𝑒 −𝑣𝑖𝑑 /𝑉𝑇 2 2𝑉𝑇 2

𝛼𝐼 𝛼𝐼 𝑣𝑖𝑑
(8.51) 𝑖𝐶2 = (8.54) 𝑖𝑐 =
1 + 𝑒 𝑣𝑖𝑑 /𝑉𝑇 2𝑉𝑇 2

𝛼𝐼𝑒 𝑣𝑑 /2𝑉𝑇 𝑣𝑖𝑑

𝑖𝐶1 = 𝑣 /2𝑉 𝑣𝐵𝐸 |𝑄1 = 𝑉𝐵𝐸 +
𝑒 𝑖𝑑 𝑇 + 𝑒 −𝑣𝑖𝑑 /2𝑉𝑇 2
𝑣𝑖𝑑
𝛼𝐼(1 + 𝑣𝑑 /2𝑉𝑇 ) 𝑣𝐵𝐸 |𝑄2 = 𝑉𝐵𝐸 −
𝑖𝐶1 ≃ 2
1 + 𝑣𝑑 /2𝑉𝑇 + 1 − 𝑣𝑑 /2𝑉𝑇
𝐼𝐶 𝛼𝐼/2
𝛼𝐼 𝛼𝐼 𝑣𝑖𝑑 (8.55) 𝑔𝑚 = =
(8.52) 𝑖𝐶1 = + 𝑉𝑇 𝑉𝑇
2 2𝑉𝑇 2

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8.2.4 Small-Signal Operation

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 8.2.4 Small-Signal Operation
An Alternative Viewpoint
𝑣𝑖𝑑
(8.57) 𝑖𝑒 =
2𝑟𝑒
𝛼𝑣𝑖𝑑 𝑣𝑖𝑑
(8.58) 𝑖𝑐 = 𝛼𝑖𝑒 = = 𝑔𝑚
2𝑟𝑒 2
𝑣𝑖𝑑
(8.59) 𝑖𝑒 =
2𝑟𝑒 + 2𝑅𝑒
𝑖𝑒 𝑣𝑑 /2𝑟𝑒
(8.60) 𝑖𝑏 = =
𝛽+1 𝛽+1

𝑣𝑖𝑑
(8.61) 𝑅𝑖𝑑 ≡ = (𝛽 + 1)2𝑟𝑒 = 2𝑟𝜋
Figure 8.20 A differential amplifier with emitter resistances. 𝑖𝑏
Only signal quantities are shown (in color).
(8.62) 𝑅𝑖𝑑 = (𝛽 + 1)(2𝑟𝑒 + 2𝑅𝑒 )
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 8.2.4 Small-Signal Operation
Differential Voltage Gain
𝑣𝑖𝑑 𝑣𝑜𝑑
(8.63) 𝑖𝐶1 = 𝐼𝐶 + 𝑔𝑚 (8.68) 𝐴𝑑 = = 𝑔𝑚 𝑅𝐶
2 𝑣𝑖𝑑

𝑣𝑖𝑑 𝛼(2𝑅𝐶 ) 𝑅𝐶
(8.64) 𝑖𝐶1 = 𝐼𝐶 − 𝑔𝑚 (8.69) 𝐴𝑑 = ≃
2 2𝑟𝑒 + 2𝑅𝑒 𝑟𝑒 + 𝑅

𝛼𝐼
(8.65) 𝐼𝐶 =
2
𝑣𝑖𝑑
(8.66) 𝑣𝐶1 = (𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 ) − 𝑔𝑚 𝑅𝐶
2
𝑣𝑖𝑑
(8.67) 𝑣𝐶1 = (𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 ) + 𝑔𝑚 𝑅𝐶
2
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8.2.4 Small-Signal Operation
The Differential Half-Circuit

Figure 8.21 Equivalence of the BJT differential amplifier in (a) to the two common-emitter amplifiers
in (b). This equivalence applies only for differential input signals. Either of the two common-emitter
amplifiers in (b) can be used to find the differential gain, differential input resistance, frequency
response, and so on, of the differential amplifier.

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8.2.4 Small-Signal Operation
The Differential Half-Circuit

Figure 8.22 The differential amplifier fed in a single-ended fashion.

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8.2.4 Small-Signal Operation
The Differential Half-Circuit

(8.70) 𝐴𝑑 = 𝑔𝑚 (𝑅𝐶 ฮ𝑟𝑜 )

Figure 8.23 Equivalent-circuit model of the differential half-circuit formed by Q1 in Fig. 8.22(b).

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 8.3. Common-Mode Rejection
8.3.1 The MOS Case
𝑖
Equation (8.73) describes effect of (8.71) 𝑣𝑖𝑐𝑚 = + 2𝑖𝑅𝑆𝑆
𝑔𝑚
common-mode signal (vicm) on vo1 and vo2. −−−−−−−−−−−−−−−−−− −
𝑣𝑖𝑐𝑚
(8.72) 𝑖 =
1/𝑔𝑚 + 2𝑅𝑆𝑆
−−−−−−−−−−−−−−−−−− −
𝑅𝐷
(8.73) 𝑣𝑜1 = 𝑣𝑜2 = − 𝑣
1/𝑔𝑚 + 2𝑅𝑆𝑆 𝑖𝑐𝑚
−−−−−−−−−−−−−−−−−− −
𝑣𝑜1 𝑣𝑜2 𝑅𝐷
(8.74) = ≃−
𝑣𝑖𝑐𝑚 𝑣𝑖𝑐𝑚 2𝑅𝑆𝑆
−−−−−−−−−−−−−−−−−− −
(8.75) 𝑣𝑜𝑑 = 𝑣𝑜2 − 𝑣𝑜1 = 0

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40/84
 8.3.1 The MOS Case
Effect of RD Mismatch 8.76 𝑣𝑜1 ≃ −
𝑅𝐷
𝑣
2𝑅𝑆𝑆 𝑖𝑐𝑚
When the output is taken single-ended,
RD′s are
magnitude of common-mode gain is mismatched
𝑅𝐷 + Δ𝑅𝐷
(8.77) 𝑣𝑜2 ≃ − 𝑣𝑖𝑐𝑚
defined in (8.76) and (8.77). 2𝑅𝑆𝑆
−−−−−−−−−−−−−−−−−−−−− −
Taking the output differentially results −Δ𝑅𝐷
(8.78) 𝑣𝑜𝑑 = 𝑣𝑜2 − 𝑣𝑜1 = 𝑣
2𝑅𝑆𝑆 𝑖𝑐𝑚
in the perfectly matched case, in zero −−−−−−−−−−−−−−−−−−−−− −
Acm (infinite CMRR). 𝑣𝑜𝑑 −Δ𝑅𝐷
(8.79) 𝐴𝑐𝑚 ≡ =
𝑣𝑖𝑐𝑚 2𝑅𝑆𝑆
−−−−−−−−−−−−−−−−−−−−− −
−𝑅𝐷 Δ𝑅𝐷
(8.80) 𝐴𝑐𝑚 = −
2𝑅𝑆𝑆 𝑅𝐷

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 8.3.1 The MOS Case
Effect of RD Mismatch 8.76 𝑣𝑜1 ≃ −
𝑅𝐷
𝑣
2𝑅𝑆𝑆 𝑖𝑐𝑚
Mismatches between the two sides of
RD′s are
the pair make Acm finite even when the mismatched
𝑅𝐷 + Δ𝑅𝐷
(8.77) 𝑣𝑜2 ≃ − 𝑣𝑖𝑐𝑚
output is taken differentially. 2𝑅𝑆𝑆
−−−−−−−−−−−−−−−−−−−−− −
This is illustrated in (8.79). −Δ𝑅𝐷
(8.78) 𝑣𝑜𝑑 = 𝑣𝑜2 − 𝑣𝑜1 = 𝑣
2𝑅𝑆𝑆 𝑖𝑐𝑚
Corresponding expressions apply for the −−−−−−−−−−−−−−−−−−−−− −
𝑣𝑜𝑑 −Δ𝑅𝐷
bipolar pair. (8.79) 𝐴𝑐𝑚 ≡ =
𝑣𝑖𝑐𝑚 2𝑅𝑆𝑆
−−−−−−−−−−−−−−−−−−−−− −
−𝑅𝐷 Δ𝑅𝐷
(8.80) 𝐴𝑐𝑚 = −
2𝑅𝑆𝑆 𝑅𝐷

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8.3.1 The MOS Case
Effect of RD and gm Mismatch
𝐴𝑑 1
(8.81) CMRR ≡ (8.84) 𝑔𝑚1 = 𝑔𝑚 + Δ𝑔𝑚
𝐴𝑐𝑚 2
1
𝐴𝑑 (8.85) 𝑔𝑚2 = 𝑔𝑚 − Δ𝑔𝑚
(8.82) CMRR = 20log 2
𝐴𝑐𝑚
(8.86) 𝑔𝑚1 − 𝑔𝑚2 = Δ𝑔𝑚

(2𝑔𝑚 𝑅𝑆𝑆 ) 𝑅𝐷 Δ𝑔𝑚

(8.83) CMRR = (8.87) 𝐴𝑐𝑚 ≃
Δ𝑅𝐷 2𝑅𝑆𝑆 𝑔𝑚
𝑅𝐷
𝑣𝑜𝑑
(8.35) 𝐴𝑑 ≡ = 𝑔𝑚 𝑅𝐷 (2𝑔𝑚 𝑅𝑆𝑆 )
𝑣𝑖𝑑 (8.88) CMRR =
Δ𝑔𝑚
𝑣𝑜𝑑 −Δ𝑅𝐷 𝑔𝑚
(8.79) 𝐴𝑐𝑚 ≡ =
𝑣𝑖𝑐𝑚 2𝑅𝑆𝑆

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8.3.1 The MOS Case
Effect of RD and gm Mismatch
1
(8.84) 𝑔𝑚1 = 𝑔𝑚 + Δ𝑔𝑚
2
1
(8.85) 𝑔𝑚2 = 𝑔𝑚 − Δ𝑔𝑚
2
(8.86) 𝑔𝑚1 − 𝑔𝑚2 = Δ𝑔𝑚

𝑅𝐷 Δ𝑔𝑚
(8.87) 𝐴𝑐𝑚 ≃
2𝑅𝑆𝑆 𝑔𝑚

(2𝑔𝑚 𝑅𝑆𝑆 )
(8.88) CMRR =
Δ𝑔𝑚
𝑔𝑚

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8.3.1 The MOS Case
Effect of RD and gm Mismatch
𝑣𝑜1 = −𝑅𝐷 𝑖1
𝑣𝑜2 = −𝑅𝐷 𝑖2
𝑣𝑜1 − 𝑣𝑜2 = −𝑅𝐷 𝑖1 − 𝑖2 = −𝑅𝐷 𝑣𝑔𝑠 ∆𝑔𝑚
𝑖1 = 𝑣𝑔𝑠 𝑔𝑚 + ∆𝑔𝑚 /2
𝑖2 = 𝑣𝑔𝑠 𝑔𝑚 − ∆𝑔𝑚 /2

𝑣𝑔𝑠 = 𝑣𝑖𝑐𝑚 − 𝑖1 + 𝑖2 2R SS = 𝑣𝑖𝑐𝑚 − 𝑣𝑔𝑠 𝑔𝑚 2R SS

𝑣𝑖𝑐𝑚 = 𝑣𝑔𝑠 (1+𝑔𝑚 2R SS)

𝑣𝑖𝑐𝑚
𝑣𝑜 = 𝑣𝑜1 − 𝑣𝑜2 = −𝑅𝐷 ∆𝑔
2𝑔𝑚 R SS 𝑚
𝑣𝑜 𝑅𝐷 ∆𝑔𝑚
=−
𝑣𝑖𝑐𝑚 2R SS 𝑔𝑚

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8.3.2 The BJT Case

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8.3.2 The BJT Case
𝛼𝑅𝐶
(8.91) 𝑣𝑜1 = − 𝑣
𝑟𝑒 + 2𝑅𝐸𝐸 𝑖𝑐𝑚

𝛼𝑅𝐶
(8.92) 𝑣𝑜2 = − 𝑣
𝑟𝑒 + 2𝑅𝐸𝐸 𝑖𝑐𝑚
(8.93) 𝑣𝑜𝑑 = 𝑣𝑜2 − 𝑣𝑜1 = 0

𝑣𝑜𝑑 𝛼Δ𝑅𝐶
(8.94) 𝐴𝑐𝑚 ≡ =−
𝑣𝑖𝑐𝑚 2𝑅𝐸𝐸 + 𝑟𝑒

𝐴𝑑
CMRR =
𝐴𝑐𝑚

Δ𝑅𝐶
(8.95) CMRR = (2𝑔𝑚 𝑅𝐸𝐸 )/
𝑅𝐶

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8.3.2 The BJT Case
Common-Mode Input Resistance
1 + 𝑅𝐶 Τ𝛽𝑟𝑜
(8.96) 𝑅𝑖𝑐𝑚 ≅ 𝛽𝑅𝐸𝐸
𝑅 + 2𝑅𝐸𝐸
1+ 𝐶
𝑟𝑜

Figure 8.27 (a) Definition of the input common-mode resistance Ricm.

Figure 8.27 (b) The equivalent common-mode half-circuit.

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 8.4 DC Offset
8.4.1 Input Offset Voltage of The MOS Differential Amplifier

Figure 8.28 (a) The MOS differential pair with both inputs grounded. Owing to device and resistor mismatches, a finite dc
output voltage VO results. (b) Application of a voltage equal to the input offset voltage VOS to the input terminals with opposite
polarity reduces VO to zero.

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 8.4.1 Input Offset Voltage of The MOS
Differential Amplifier
𝑊 𝑊 1 𝑊
Δ𝑅𝐷 𝐼 (8.102) = + Δ
(8.98) 𝑅𝐷1 = 𝑅𝐷 + (8.100) 𝑉𝑂 = 𝑉𝐷2 − 𝑉𝐷1 = Δ𝑅𝐷 𝐿 1 𝐿 2 𝐿
2 2
𝑊 𝑊 1 𝑊
Δ𝑅𝐷 𝑉𝑂𝑉 Δ𝑅𝐷 (8.103) = − Δ
(8.99) 𝑅𝐷2 = 𝑅𝐷 − (8.101) 𝑉𝑂𝑆 = 𝐿 2 𝐿 2 𝐿
2 2 𝑅𝐷
𝐼 Δ(𝑊/𝐿)
𝐼 Δ𝑅𝐷 (8.104) 𝐼1 = 1+
𝑉𝐷1 = 𝑉𝐷𝐷 − 𝑅𝐷 + 2 2(𝑊/𝐿)
2 2
𝐼 Δ(𝑊/𝐿)
𝐼 Δ𝑅𝐷 (8.105) 𝐼2 = 1−
𝑉𝐷2 = 𝑉𝐷𝐷 − 𝑅𝐷 − 2 2(𝑊/𝐿)
2 2

2𝐼𝐷 2 𝐼Τ2 𝐼 𝑉𝑂𝑉 Δ(𝑊/𝐿)

𝑔𝑚 = = = (8.106) 𝑉𝑂𝑆 =
𝑉𝑂𝑉 𝑉𝑂𝑉 𝑉𝑂𝑉 2 (𝑊/𝐿)

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 8.4.1 Input Offset Voltage of The MOS
Differential Amplifier
Δ𝑉𝑡
(8.107) 𝑉𝑡1 = 𝑉𝑡 +
2
Δ𝑉𝑡
(8.108) 𝑉𝑡2 = 𝑉𝑡 −
2

1 𝑊 Δ𝑉𝑡 2
𝐼 = 𝑘𝑛′ 𝑉𝐺𝑆 − 𝑉𝑡 −
2 𝐿 2

1 𝑊 Δ𝑉𝑡 2
= 𝑘𝑛′ (𝑉𝐺𝑆 − 𝑉𝑡 )2 1 −
2 𝐿 2(𝑉𝐺𝑆 −𝑉𝑡

1 ′𝑊 2
∆𝑉𝑡
𝐼1 ≅ 𝑘 𝑉 − 𝑉𝑡 1−
2 𝑛 𝐿 𝐺𝑆 𝑉𝐺𝑆 − 𝑉𝑡

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8.4.1 Input Offset Voltage of The MOS
Differential Amplifier
1 𝑊 Δ𝑉𝑡
𝐼2 ≃ 𝑘𝑛′ (𝑉𝐺𝑆 − 𝑉𝑡 )2 1 +
2 𝐿 𝑉𝐺𝑆 − 𝑉𝑡

1 ′𝑊 𝐼
𝑘𝑛 (𝑉𝐺𝑆 − 𝑉𝑡 )2 =
2 𝐿 2

𝐼 Δ𝑉𝑡 𝐼 Δ𝑉𝑡
Δ𝐼 = =
2 𝑉𝐺𝑆 − 𝑉𝑡 2 𝑉𝑂𝑉
(8.109) 𝑉𝑂𝑆 = Δ𝑉𝑡

2 2
𝑉𝑂𝑉 Δ𝑅𝐷 𝑉𝑂𝑉 Δ(𝑊/𝐿)
(8.110) 𝑉𝑂𝑆 = + + (Δ𝑉𝑡 )2
2 𝑅𝐷 2 𝑊/𝐿

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8.4.2 Input Offset Voltage of the Bipolar
Differential Amplifier

Figure 8.29 (a) The BJT differential pair with both inputs grounded.
Device mismatches result in a finite dc output VO. (b) Application of
the input offset voltage VOS ≡ VO/Ad to the input terminals with
opposite polarity reduces VO to zero.

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8.4.2 Input Offset Voltage of the Bipolar
Differential Amplifier
Δ𝑅𝐶
(8.111) 𝑅𝐶1 = 𝑅𝐶 +
2
𝐼
𝛼 (Δ𝑅𝐶 )
Δ𝑅𝐶 (8.113) 𝑉𝑂𝑆 = 2
(8.112) 𝑅𝐶2 = 𝑅𝐶 − 𝐴𝑑
2

𝛼𝐼 Δ𝑅𝐶 𝛼𝐼/2
𝑉𝐶1 = 𝑉𝐶𝐶 − 𝑅𝐶 + 𝑔𝑚 =
2 2 𝑉𝑇

𝛼𝐼 Δ𝑅𝐶 Δ𝑅𝐶
𝑉𝐶2 = 𝑉𝐶𝐶 − 𝑅𝐶 − (8.114) 𝑉𝑂𝑆 = 𝑉𝑇
2 2 𝑅𝐶

𝐼
𝑉𝑂 = 𝑉𝐶2 − 𝑉𝐶1 = 𝛼 (Δ𝑅𝐶 )
2

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8.4.2 Input Offset Voltage of the Bipolar
Differential Amplifier
Δ𝐼𝑆 𝐼 Δ𝐼𝑠
(8.115) 𝐼𝑆1 = 𝐼𝑆 + 𝑉𝑂 = 𝛼 𝑅𝐶
2 2 𝐼𝑠
Δ𝐼𝑆
Δ𝐼𝑆 (8.119) 𝑉𝑂𝑆 = 𝑉𝑇
(8.116) 𝐼𝑆1 = 𝐼𝑆 − 𝐼𝑆
2 2 2
Δ𝑅𝐶 Δ𝐼𝑆
(8.120) 𝑉𝑂𝑆 = 𝑉𝑇 + 𝑉𝑇
𝐼 Δ𝐼𝑠 𝑅𝐶 𝐼𝑆
(8.117) 𝐼𝐸1 = 1+
2 2𝐼𝑠 2 2
Δ𝑅𝐶 Δ𝐼𝑆
=𝑉 +
𝑅𝐶 𝐼𝑆
𝐼 Δ𝐼𝑠
(8.118) 𝐼𝐸1 = 1−
2 2𝐼𝑠

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8.4.3 Input Bias and Offset Currents of the
Bipolar Differential Amplifier
𝐼 Δ𝛽
𝐼/2 (8.125) 𝐼𝑂𝑆 =
(8.121) 𝐼𝐵1 = 𝐼𝐵2 = 2(𝛽 + 1) 𝛽
𝛽+1
𝐼𝐵1 + 𝐼𝐵2 𝐼
(8.126) 𝐼𝐵 ≡ =
(8.122) 𝐼𝑂𝑆 = 𝐼𝐵1 − 𝐼𝐵2 2 2(𝛽 + 1)
Δ𝛽
(8.127) 𝐼𝑂𝑆 = 𝐼𝐵
Δ𝛽 Δ𝛽 𝛽
𝛽1 = 𝛽 + ; 𝛽2 = 𝛽 −
2 2

𝐼 1 𝐼 1 Δ𝛽
(8.123) 𝐼𝐵1 = ≃ 1−
2 𝛽 + 1 + Δ𝛽/2 2 𝛽 + 1 2𝛽

𝐼 1 𝐼 1 Δ𝛽
(8.124) 𝐼𝐵2 = ≃ 1+
2 𝛽 + 1 − Δ𝛽/2 2 𝛽 + 1 2𝛽

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8.5 The Differential Amplifier with a Current-Mirror Load

Figure 8.30 A three-stage amplifier consisting of two differential-

in, differential-out stages, A1 and A2, and a differential-in, single-
ended-out stage A3.

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8.5.1 Differential-to Single-Ended Conversion

Figure 8.31 A simple but inefficient approach for

differential-to-single-ended conversion.
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 8.5.2 The Current-Mirror-Loaded MOS Differential Pair

Figure 8.32 (a) The current-mirror-loaded MOS differential pair. (b) The circuit at equilibrium assuming
perfect matching. (c) The circuit with a differential input signal applied and neglecting the ro of all
transistors.

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 8.5.3 Differential Gain of the Current-Mirror-Loaded
MOS Pair
(8.128) 𝐺𝑚 = 𝑔𝑚1,2
(8.129) 𝑅𝑜 = 𝑟𝑜2 ฮ𝑟4

𝑣𝑜
(8.130) 𝐴𝑑 ≡ = 𝐺𝑚 𝑅𝑜 = 𝑔𝑚1,2 𝑟𝑜2 ฮ𝑟4
𝑣𝑑
1 1
(8.131) 𝐴𝑑 = 𝑔𝑚 𝑟𝑜 = 𝐴0
2 2

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 8.5.3 Differential Gain of the Current-Mirror-
Loaded MOS Pair
Derivation of the Short-Circuit Transconductance, Gm

𝑣𝑖𝑑
(8.132) 𝑖𝑜 = 𝑔𝑚𝑠 − 𝑔𝑚4 𝑣𝑔𝑠4
2
(8.133) 𝑣𝑔𝑠4 = 𝑣𝑔𝑠3

𝑣𝑖𝑑 1
𝑣𝑔𝑠3 = −𝑔𝑚1 ฮ𝑟 ฮ𝑟
2 𝑔𝑚3 𝑜3 𝑜1

𝑔𝑚1 𝑣𝑖𝑑
(8.134) 𝑣𝑔𝑠3 ≃ −
𝑔𝑚3 2
𝑖𝑜 = 𝑔𝑚 𝑣𝑖𝑑 ⇒ 𝐺𝑚 = 𝑔𝑚

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 8.5.3 Differential Gain of the Current-Mirror-
Loaded MOS Pair
Derivation of the Output Resistance R0
𝑣𝑥
𝑅𝑜 ≡
𝑖𝑥
𝑖 = 𝑣𝑥 /𝑅𝑜2
𝑟𝑜1 + 𝑅𝐿 1 1/𝑔𝑚3 1
𝑅in1 = = + ≃
𝑔𝑚1 𝑟𝑜1 𝑔𝑚1 𝑔𝑚1 𝑟𝑜1 𝑔𝑚1
1 𝑔𝑚2
𝑅𝑜2 = 𝑅in1 + 𝑟𝑜2 + 𝑔𝑚2 𝑟𝑜2 𝑅in1 = + 𝑟𝑜2 + 𝑟
𝑔𝑚1 𝑔𝑚1 𝑜2
(8.135) 𝑅𝑜2 ≃ 2𝑟𝑜2

𝑣𝑥 𝑣𝑥 𝑣𝑥 𝑣𝑥
𝑖𝑥 = 𝑖 + 𝑖 + = 2𝑖 + =2 +
𝑟𝑜4 𝑟𝑜4 𝑅𝑜2 𝑟𝑜4
𝑣𝑥 𝑣𝑥
𝑖𝑥 = 2 +
2𝑟𝑜2 𝑟𝑜4
Figure 8.35 Circuit for determining Ro. The circled
𝑣𝑥 numbers indicate the order of the analysis steps.
(8.136) 𝑅𝑜 ≡ = 𝑟𝑜2 ฮ𝑟𝑜4
𝑖𝑥

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(REVIEW) 7.4.1 The CG Circuit

Figure 7.18 (a) A CG amplifier with the bias arrangement only

partially shown. (b) The circuit with the dc sources eliminated.

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 (REVIEW) 7.4.1 The CG Circuit
Input Resistance
𝑣𝑥
𝑅in ≡
𝑖𝑥
𝑣𝑥 = (𝑖𝑥 + 𝑔𝑚 𝑣𝑔𝑠 )𝑟𝑜 + 𝑖𝑥 𝑅𝐿

𝑟𝑜 + 𝑅𝐿
(7.53) 𝑅in =
1 + 𝑔𝑚 𝑟𝑜

1 𝑅𝐿
(7.54) 𝑅in ≃ +
𝑔𝑚 𝑔𝑚 𝑟𝑜

Figure 7.19 Determining the input resistance Rin of the CG amplifier.

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 (REVIEW) 7.4.2. The Output Resistance of a
Source-Degenerated CS Amplifier
Previous sections discuss benefits obtained when resistance RS is included in the
source lead of the CS amplifier.
Such a resistance is referred to as a source-degeneration resistance because of its
action is reducing the effective transconductance of the CS stage to gm/(1+gmRs).

Output resistance is defined as below.

(7.60) 𝑅𝑜 = 𝑟𝑜 + 𝑅𝑠 + 𝑔𝑚 𝑟𝑜 𝑅𝑠
(7.61) 𝑅𝑜 ≃ 1 + 𝑔𝑚 𝑅𝑠 𝑟𝑜

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8.5.4 The Bipolar Differential Pair with a
Current-Mirror Load
(8.137) 𝐺𝑚 = 𝑔𝑚1,2

(8.138) 𝑅𝑜 = 𝑟𝑜2 ฮ𝑟𝑜4

𝑣𝑜
(8.139) 𝐴𝑑 ≡ = 𝐺𝑚 𝑅𝑜 = 𝑔𝑚 (𝑟𝑜2 ฮ𝑟𝑜4 )
𝑣𝑖𝑑
1
(8.140) 𝐴𝑑 = 𝑔 𝑟
2 𝑚 0
(8.141) 𝑅𝑖𝑑 = 2𝑟𝜋

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 8.5.4 The Bipolar Differential Pair with a
Current-Mirror Load
Systematic Input Offset Voltage
𝐼4 1
(8.142) =
𝐼3 1 + 2
𝛽𝑃
𝛼𝐼/2
(8.143) 𝐼4 =
2
1+
𝛽𝑃
𝛼𝐼 𝛼𝐼/2 𝛼𝐼 2/𝛽𝑃 𝛼𝐼
(8.144) Δ𝑖 = − = ≃
2 1+ 2 2 1+ 2 𝛽𝑃
𝛽𝑃 𝛽𝑃
Δ𝑖
𝑉𝑂𝑆 = −
𝐺𝑚
Figure 8.37 The current-mirror-loaded BJT differential
𝛼𝐼/𝛽𝑃 2𝑉𝑇 pair suffers from a systematic input offset voltage
(8.145) 𝑉𝑂𝑆 = − =− resulting from the error in the current transfer ratio of
𝛼𝐼/2𝑉𝑇 𝛽𝑃
the current mirror.
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 (REVIEW) 7.2.3. BJT Circuits

𝐼𝑂 𝐼𝐶 1
(7.18) = =
𝐼REF 2 2
𝐼𝐶 1 + 1+
𝛽 𝛽

𝐼𝑂 𝑚
(7.19) =
𝐼REF 𝑚+1
1+
𝛽
Δ𝑉𝑂 𝑉𝐴2
(7.20) 𝑅𝑂 ≡ = 𝑟𝑜2 =
Δ𝐼𝑂 𝐼𝑂

𝑚 𝑉𝑂 − 𝑉𝐵𝐸
(7.21) 𝐼𝑂 = 𝐼REF 1+
Figure 7.8 Analysis of the current mirror 𝑚+1 𝑉𝐴2
1+
taking into account the finite β of the BJTs. 𝛽

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 8.5.4 The Bipolar Differential Pair with a
Current-Mirror Load
Systematic Input Offset Voltage

Figure 8.38 An current-mirror-loaded bipolar differential

amplifier employing a folded cascode stage (Q3 and Q4) and a
Wilson current-mirror load (Q5, Q6, and Q7).

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8.5.5 Common-Mode Gain and CMRR

Figure 8.39 Analysis of the current-mirror-loaded MOS differential amplifier to

determine its common-mode gain.

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 8.5.5 Common-Mode Gain and CMRR

Figure 8.39 Analysis of the current-mirror-loaded MOS differential amplifier to determine its
common-mode gain.

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 8.5.5 Common-Mode Gain and CMRR
(2𝑅𝑆𝑆 ԡ𝑟𝑜1 )
𝑣𝑠 = 𝑣𝑖𝑐𝑚 ≃ 𝑣𝑖𝑐𝑚
(2𝑅𝑆𝑆 ԡ𝑟𝑜1 ) + (1/𝑔𝑚1 )

𝑣𝑠 𝑣𝑖𝑐𝑚
𝑖𝑜 = ≃
2𝑅𝑆𝑆 2𝑅𝑆𝑆
𝑖𝑜 1
(8.148) 𝐺𝑚𝑐𝑚 ≡ =
𝑣𝑖𝑐𝑚 2𝑅𝑆𝑆
(8.149) 𝑅𝑜1 = 2𝑅𝑆𝑆 + 𝑟𝑜1 + (𝑔𝑚1 𝑟𝑜1 )(2𝑅𝑆𝑆 )
8.150 𝑅𝑜2 = 2𝑅𝑆𝑆 + 𝑟𝑜2 + 𝑔𝑚2 𝑟𝑜2 2𝑅𝑆𝑆
(8.151) 𝑖𝑖 ≃ 𝐺𝑚𝑐𝑚 𝑣𝑖𝑐𝑚
(8.152) 𝑣𝑜 = (𝐴𝑚 𝑖𝑖 − 𝐺𝑚𝑐𝑚 𝑣𝑖𝑐𝑚 )(𝑅𝑜𝑚 ฮ𝑅𝑜2 )

𝑣𝑜
(8.153) 𝐴𝑐𝑚 ≡ = −(1 − 𝐴𝑚 )𝐺𝑚𝑐𝑚 (𝑅𝑜𝑚 ฮ𝑅𝑜2 )
𝑣𝑖𝑐𝑚

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8.5.5 Common-Mode Gain and CMRR

1 𝐴𝑑
(8.154) 𝑅𝑖𝑚 = ฮ𝑟 (8.158) CMRR ≡ = 𝑔𝑚 𝑟𝑜2 ฮ𝑟𝑜4 2𝑔𝑚3 𝑅𝑆𝑆
𝑔𝑚3 𝑜3 𝐴𝑐𝑚

(8.155) 𝑅𝑜𝑚 = 𝑟𝑜4 (8.159) CMRR = (𝑔𝑚 𝑟𝑜 )(𝑔𝑚 𝑅𝑆𝑆 )

𝐴𝑚 𝑖𝑖 = −𝑔𝑚4 𝑣𝑔𝑠4 = −𝑔𝑚4 𝑣𝑔𝑠3

1
(8.156) 𝐴𝑚 = 1ൗ 1 +
𝑔𝑚3 𝑟𝑜3

1
(8.157) 𝐴𝑐𝑚 ≃ −
2𝑔𝑚3 𝑅𝑆𝑆

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8.5.5 Common-Mode Gain and CMRR
The Bipolar Case
1
(8.160) 𝐺𝑚𝑐𝑚 =
2𝑅𝐸𝐸

1
(8.161) 𝑅𝑖𝑚 = ฮ𝑟 ฮ𝑟 ฮ𝑟
𝑔𝑚3 𝜋3 𝑜3 𝜋4

1 2
(8.162) 𝑅𝑖𝑚 ≃ ะ
𝑔𝑚3 𝑟𝜋3
(8.163) 𝑅𝑜𝑚 = 𝑟𝑜4
(8.164) 𝐴𝑚 = 𝑔𝑚4 𝑅𝑖𝑚

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8.5.5 Common-Mode Gain and CMRR
The Bipolar Case
2
𝑟𝑜4 𝑟𝜋3
(8.165) 𝐴𝑐𝑚 ≃ −
2𝑅𝐸𝐸 𝑔 2
𝑚3 +
𝑟𝜋3
𝑟𝑜4 2 𝑟𝑜4
≃− =−
2𝑅𝐸𝐸 𝛽3 𝛽3 𝑅𝐸𝐸

𝐴𝑑 𝛽3 𝑅𝐸𝐸
(8.166) CMRR ≡ = 𝑔𝑚 𝑟𝑜2 ฮ𝑟04
𝐴𝑐𝑚 𝑟𝑜4

1
(8.167) CMRR = 𝛽 𝑔 𝑅
2 3 𝑚 𝐸𝐸

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8.6 Multistage Amplifiers
8.6.1 A Two-Stage CMOS Op Amp

Figure 8.40 Two-stage CMOS op-amp configuration.

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8.6.1 A Two-Stage CMOS Op Amp
Voltage Gain
(8.168) 𝐴1 = −𝑔𝑚1 𝑟𝑜2 ฮ𝑟𝑜4

(8.169) 𝐴2 = −𝑔𝑚6 𝑟𝑜6 ฮ𝑟𝑜7

(𝑊/𝐿)6
(8.170) 𝐼6 = (𝐼/2)
(𝑊/𝐿)4

(𝑊/𝐿)7
(8.171) 𝐼7 = 𝐼
(𝑊/𝐿)5

(𝑊/𝐿)6 (𝑊/𝐿)7
(8.172) =2
(𝑊/𝐿)4 (𝑊/𝐿)5

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8.6.2 A Bipolar OP Amp

Figure 8.41 A four-stage bipolar op amp.

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8.6.2 A Bipolar Op Amp
Analysis Using Current Gains

Figure 8.47 The circuit of the multistage amplifier of Fig. 8.41 prepared for small-signal
analysis. Indicated are the signal currents throughout the amplifier and the input resistances
of the four stages.

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 8.6.2 A Bipolar Op Amp
Analysis Using Current Gains
𝑣𝑜 = 𝑅6 𝑖𝑒8
𝑣𝑖𝑑 = 𝑅𝑖1 𝑖𝑖

𝑣𝑜 𝑅6 𝑖𝑒8
=
𝑣𝑖𝑑 𝑅𝑖1 𝑖𝑖

𝑖𝑒8 𝑖𝑒8 𝑖𝑏8 𝑖𝑐7 𝑖𝑏7 𝑖𝑐5 𝑖𝑐5 𝑖𝑐2

= × × × × × ×
𝑖𝑖 𝑖𝑏8 𝑖𝑐7 𝑖𝑏7 𝑖𝑐5 𝑖𝑏5 𝑖𝑐2 𝑖𝑖

𝑖𝑐5
= 𝛽5
𝑖𝑏5

𝑖𝑐5 (𝑅1 + 𝑅2 )
=
𝑖𝑐2 (𝑅1 + 𝑅2 ) + 𝑅𝑖2

𝑖𝑐2
= 𝛽2
𝑖𝑖

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 Summary

The differential-pair or differential-amplifier configuration is most widely used building block

in analog IC designs. The input stage of every op-amp is a differential amplifier.

There are two reasons for preferring differential to single-ended amplifiers: 1) differential
amplifiers are insensitive to interference and 2) they do not need bypass and coupling
capacitors.

For a MOS (bipolar) pair biased by a current source I, each device operates at a drain
(collector, assuming a = 1) current of I/2 and a corresponding overdrive voltage VOV (no
analog in bipolar). Each device has gm=1/VOV (aI/2VT for bipolar).

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 Summary

With the two input terminals connected to a suitable dc voltage VCM, the bias
current I of a perfectly symmetrical differential pair divides equally between the
two transistors of the pair, resulting in zero voltage difference between the two
drains (collectors). To steer the current completely to one side of the pair, a
difference input voltage vid of at least 21/2VOV is needed.

Superimposing a differential input signal vid on the dc common-mode input

voltage VCM such that vI1 = VCM + vid/2 and vI2 = VCM – vid/2 causes a virtual signal
ground to appear on the common-source (common-emitter) connection.

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 Summary

The analysis of a differential amplifier to determine differential gain, differential

input resistance, frequency response of differential gain, and so on is facilitated by
employing the differential half-circuit which is a common-source (common-
emitter) transistor biased at I/2.

An input common-mode signal vicm gives rise to drain (collector) voltage signals
that are ideally equal and given by –vicm(RD/2RSS)[-vicm(RC/2REE) for the bipolar pair],
where RSS (REE) is the output resistance of the current source that supplies the bias
current I.

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 Summary

While the input differential resistance Rid of the MOS pair is infinite, that for the
bipolar pair is only 2rp but can be increased to 2(b+1)(re+Re) by including
resistances Re in the two emitters. The latter action, however, lowers Ad.

Mismatches between the two sides of a differential pair result in a differential dc

output voltage (Vo) even when the two input terminals are tied together and
connected to a dc voltage VCM. This signifies the presence of an input offset
voltage VOS = VO/Ad. In a MOS pair, there are three main sources for VOS. Two
exist for the bipolar pair.

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