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A New Hardware Design and Implementation of QPSK Modulator in Normal

and 4-QAM Mode for 5G Communication Networks

Chapter · January 2020

DOI: 10.1007/978-3-030-33846-6_29

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Book Title Inventive Computation Technologies
Series Title
Chapter Title A New Hardware Design and Implementation of QPSK Modulator in Normal and 4-QAM Mode for 5G
Communication Networks
Copyright Year 2020
Copyright HolderName Springer Nature Switzerland AG
Corresponding Author Family Name Rameshkumar
Particle
Given Name R.
Prefix
Suffix
Role
Division
Organization KLEF
Address Vaddeswaram, Guntur, 522502, Andhra Pradesh, India
Email [email protected]
Author Family Name Swaminathan
Particle
Given Name J. N.
Prefix
Suffix
Role
Division
Organization Godavari Institute of Engineering and Technology
Address Rajahmundy, Andhra Pradesh, India
Email [email protected]

Abstract Digital information can be represented by Quadrature Phase Shift Keying (QPSK) modulation scheme. In
order to represent digital data, a finite variety of different signals is used in modulation schemes. For the
representation of digital signals, QPSK uses four unique phases. Due to the key features and performance
efficiency in bit error rate and optimal bandwidth, QPSK is commonly used in several modern digital
communication based applications. Satellite, wireless and mobile communication uses this technology.
QPSK modulators made with mux, counters and balanced modulators are already available in the market.
Due to the use of transformers for making these devices, they turn out to be bulky. This paper propose a
general purpose IC based novel QPSK modulator. This efficiently reduces the size and thereby the
complexity of the circuit.
Keywords Quadrature Phase Shift Keying (QPSK) - Pseudo Random Binary Sequence (PRBS) - Bit splitter -
Mutiplexer - Binary Phase Shift Keying (BPSK)
 A New Hardware Design and Implementation
Author Proof

of QPSK Modulator in Normal and 4-QAM

Mode for 5G Communication Networks

R. Rameshkumar1(&) and J. N. Swaminathan2

1
KLEF, Vaddeswaram, Guntur 522502, Andhra Pradesh, India
[email protected]
2
Godavari Institute of Engineering and Technology, Rajahmundy,
Andhra Pradesh, India
[email protected]

Abstract. Digital information can be represented by Quadrature Phase Shift

Keying (QPSK) modulation scheme. In order to represent digital data, a finite
variety of different signals is used in modulation schemes. For the representation
of digital signals, QPSK uses four unique phases. Due to the key features and
performance efficiency in bit error rate and optimal bandwidth, QPSK is com- AQ1
monly used in several modern digital communication based applications.
Satellite, wireless and mobile communication uses this technology. QPSK
modulators made with mux, counters and balanced modulators are already
available in the market. Due to the use of transformers for making these devices,
they turn out to be bulky. This paper propose a general purpose IC based novel
QPSK modulator. This efficiently reduces the size and thereby the complexity of
the circuit.

Keywords: Quadrature Phase Shift Keying (QPSK)
Pseudo Random Binary

Sequence (PRBS)
Bit splitter
Mutiplexer
Binary Phase Shift Keying
(BPSK)

1 Introduction

QPSK or Quadrature Phase-Shift Keying is a higher order modulation scheme used in

digital modulation. A QPSK signal can be generated by independently modulating two
carriers in quadrature (±cos xt and ±sin xt). Traditionally, QPSK waveform will be
generated by multiplying sine and cosine waveforms with odd and even bits from input
bit stream as shown in Fig. 1. It uses two balanced modulator each fed with carrier
signals generated from local oscillator. In our experiment, we try to generate QPSK
waveform without using balanced modulator or multiplier [2] as shown in Fig. 2.
A Pseudo Random Binary Sequence (PRBS) generator is used to generate random
binary data. The Serial to Parallel Converter splits the incoming data into even and odd
bits. Even and odd bits are used as address lines of 8:1 Multiplexer (4051). The signals,
±cos xt, ±sin xt are generated using function generators, phase shifter, inverters are
given to the input lines of multiplexer. Depending on Even and Odd bits, multiplexer
chooses any one of these signals to form the QPSK waveform. In this project we use
© Springer Nature Switzerland AG 2020
S. Smys et al. (Eds.): ICICIT 2019, LNNS 98, pp. 1–8, 2020.
https://doi.org/10.1007/978-3-030-33846-6_29
 2 R. Rameshkumar and J. N. Swaminathan

CMOS IC instead of TTL ICs. In CMOS ICs all unused pins must be grounded to
Author Proof

ensure proper functioning of the IC.

Fig. 1. Classical method of QPSK generation

Fig. 2. Proposed method of QPSK

 A New Hardware Design and Implementation 3

2 QPSK Constellation and Waveforms

Author Proof

In BPSK, there are two symbols since we use only one bit. Hence the phase shift
required between the symbols is 360/2 = 180°. QPSK has two bits per symbol and
hence there are 4 combinations: 00, 01, 10, 11. So the phase difference between any
two successive symbols is 360/4 = 90° [1]. These phase shifts are produced corre-
sponding to 4 different combinations of I and Q data (or Odd and Even data) (Table 1
and Fig. 3). AQ2

Table 1. QPSK wave form in 4-QAM mode

Even Odd Phase Waveform
1 1 45° A
0 1 135 B
0 0 235 C
1 0 335 D

Fig. 3. QPSK constellation and waveforms

In Fig. 4, first wave form is PRBS data. 2nd and 3rd wave are I and Q output from
bit splitter. The last wave form is QPSK wave form. Note that the waveform changes
phases.
 4 R. Rameshkumar and J. N. Swaminathan
Author Proof

Fig. 4. QPSK wave form and timing diagram

3 QPSK Modulator

3.1 Clock Pulse Generator

An astable multivibrator using 555 timer is used as clock frequency (square wave)
generator is shown in Fig. 5. This clock is used to feed clock signal to PRBS generator
and bit splitter. R1 = 3.3 kΩ R2 = 5.6 kΩ C = 0.1 µF Clock frequency f = 1/T T =
Ton + Toff Ton = 0.69R2C = 0.3864 ms Toff = 0.69(R1 + R2)C = 0.6141 ms
T = 1 ms f ¼ T1 ¼ 1 kHz.

3.2 PN-Sequence Generator

The random bit generator generates a bit sequence (PN-sequence) that is used as input
data for our QPSK modulator [4]. A PN-sequence generator circuit is constructed
(Fig. 6) using linear feedback shift register (LFSR). The output of 3rd and 4th flipflops
are combined using XOR gate and fed back to the D input of first flipflop. We use four
 A New Hardware Design and Implementation 5

D flip-flops (4013) and one XOR gate (4030) so we can generate 24-1 = 15 bits (1 1 1
Author Proof

1 0 0 0 1 0 0 1 1 0 1 0) and then the bits sequence (15 bits) will be repeated

periodically. The output of last flipflop (i-4) is fed to the bit splitter (Fig. 7). The even
and odd bit sequence are given in the Table 2. The Even bit sequence: 11000100 and
odd bit sequence: 11010111.

Fig. 5. 555 timer as astable multivibrator Fig. 6. PN-sequence generator

Table 2. PRBS output sequence

Xi-1 Xi-2 Xi-3 Xi-4 Xi Even Odd
1 1 1 1 0 1
0 1 1 1 0 1
0 0 1 1 0 1
0 0 0 1 1 1
1 0 0 0 0 0
0 1 0 0 0 0
0 0 1 0 1 0
1 0 0 1 1 1
1 1 0 0 0 0
0 1 1 0 1 0
1 0 1 1 0 1
0 1 0 1 1 1
1 0 1 0 1 0
1 1 0 1 1 1
1 1 1 0 1 0
1 1 1 1 0 1

The clock pulse is taken from the astable multivibrator. Hence the data rate is same
as that of the clock frequency.
 6 R. Rameshkumar and J. N. Swaminathan

3.3 Frequency Divider & Bit Splitter

Author Proof

This stage divides the input bit sequence from PRBS into even and odd bits. Bit splitter
is comprised by 3 D flip-flops(4013) (Fig. 7). The first D flipflop (Q and Q shorted)
divides the input clock into two. Now, Q and Q outputs of first flipflop are given as
clock to flipflops A and B. Data to A & B is from PRBSwhose common input data is
from PRBS generator. Flipflop A shifts only even bits (0, 2, 4…) and flipflop B shifts
only Odd bits (1, 3, 5, …) (Fig. 8).

Fig. 7. Bit splitter Fig. 8. Phase shifter

3.4 Integrated Circuit Diagram

Below is the complete circuit diagram of QPSK modulator. The power supply given to
ICs 4013, 4030, 4051 is 5 V and for Op-amp 741 is ±9 V. A 4 bit PRBS generator is
constructed by below steps.
1. Construct the clock generator as shown in the circuit diagram (Fig. 5)
2. Construct the PRBS generator as shown in Fig. 6
3. Using three D flip-flops (4013) construct the frequency divider and bit splitter as
shown in the circuit diagram (Fig. 7)
4. Using function generator, get the carrier frequency sin xt. Feed this to 90° phase
shifter to get cos xt.
5. Feed sin xt and cos xt to inverters to get  sin xt and  cos xt
6. Construct the multiplexer and feed  sin xt,  cos xt to input lines and I and Q
data to selection lines as shown in the circuit diagram.
7. Observe the QPSK waveform from 3rd pin of Mux (4051). Adjust the potentio
meter of phase shifters to get accurate phase shifts.
 A New Hardware Design and Implementation 7

4 Results and Discussion

Author Proof

Upper waveform is clock pulse obtained from the Astable multivibrator output and
lower one is PRBS data. The waveform swings between 0 and 5 V. (Unipolar) We can
observe the pattern 100110101111000 from the lower waveform. For each complete
cycle of square wave, one bit is assumed. This pattern will repeat periodically for every
15 bits (Figs. 9, 10, 11 and 12).

Fig. 9. Clock pulse and PRBS data Fig. 10. QPSK waveform (4 QAM)

Fig. 11. QPSK waveform1 Fig. 12. QPSK waveform2

5 Conclusion

The four unique phases of a QPSK signal are clearly expressed in the waveforms
shown in the result section. It is beyond the traditional textbook methodology. QPSK
and similar solid applications can be demonstrated and implemented using easily
available general purpose ICs. This overcomes the bulkiness, complexity and cost of
 8 R. Rameshkumar and J. N. Swaminathan

the balanced modulators that use transformers in their circuits. Other ICs such as
Author Proof

MC1496 provide higher accuracy but are more complex and expensive. These draw-
backs are overcome by the proposed circuit.

Acknowledgement. The Author like to acknowledge Er.Koneru Satyanarayana, President of

K L Deemed to be University,Green Fields, Vaddeswaram, Andhra Pradesh, India for providing
facility to do the research work.

References
1. Chowdhury, M.A.N., Mahfuz, M.U., Chowdhury, S.H., Kabir, M.M.: Design of an improved
QPSK modulation technique in wireless communication systems. In: IEEE International
Conference on Electrical Information and Communication Technology (EICT) (2017)
2. Pareek, V.: A novel implementation of QPSK modulator on FPGA. In: IEEE Students’
Conference on Electrical, Electronics and Computer Science (SCEECS) (2016)
3. Birla, N., Gautam, N., Patel, J., Balaji, P.: A novel QPSK modulator. In: IEEE International
Conference on Advanced Communications, Control and Computing Technologies (2014) AQ3
4. Jain, M., Kesharwani, P., Malviya, A.K., Khare, K., Shandilya, P., Haldar, S., Rai, H.,
Aggarwal, S.: Performance optimized digital QPSK modulator. In: International Conference
on Energy, Communication, Data Analytics and Soft Computing (ICECDS) (2017)
Author Proof

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