Scribd
Upload
28 views

Counter

This document describes implementing register and counter circuits. It discusses: 1. The objective is to learn how registers and counters work by implementing a 4-bit register on a digital trainer board and breadboard, and creating counter circuits in software and hardware. 2. Registers are made of flip-flops that store multiple bits, while counters are made of cascaded flip-flops that increment or decrement through numbers. 3. Synchronous up and down 4-bit counters are created using JK flip-flops and AND gates, with the external clock triggering all flip-flops simultaneously.

Uploaded by

Muhammad Suleman
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
28 views

Counter

This document describes implementing register and counter circuits. It discusses: 1. The objective is to learn how registers and counters work by implementing a 4-bit register on a digital trainer board and breadboard, and creating counter circuits in software and hardware. 2. Registers are made of flip-flops that store multiple bits, while counters are made of cascaded flip-flops that increment or decrement through numbers. 3. Synchronous up and down 4-bit counters are created using JK flip-flops and AND gates, with the external clock triggering all flip-flops simultaneously.

Uploaded by

Muhammad Suleman
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

Lab No.

9
Implementing circuits of Register and Counters
Objective: -
1. Learn how register and counter works.
2. Implement a 4-bit register.
3. Implement counter circuit on software and breadboard.
4. A basic concept of memory storage.

Equipment: -
1. Digital trainer board.
2. Connecting wires.
3. Proteus.
4. 7474 and 7476 IC’s.
5. Wire stripper.

Introduction: -
Flip-flop is a 1-bit memory cell which can be used for storing the digital data. To increase
the storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a group
of flip-flop is known as a Register. The n-bit register will consist of n number of flip-flop and it is
capable of storing an n-bit word.

Figure 1 Register

A counter circuit is usually constructed of a number of flip-flops connected in cascade.


Counters are a very widely used component in digital circuits, and are manufactured as
separate integrated circuits and also incorporated as parts of larger integrated circuits
Task 1:
Synchronous Up Counter

In the above image, the basic Synchronous counter design is shown which is Synchronous up
counter. A 4-bit Synchronous up counter start to count from 0 (0000 in binary) and increment
or count upwards to 15 (1111 in binary) and then start new counting cycle by getting reset. Its
operating frequency is much higher than the same range Asynchronous counter. Also, there is no
propagation delay in the synchronous counter just because all flip-flops or counter stage is in
parallel clock source and the clock triggers all counters at the same time.

The external clock is directly provided to all J-K Flip-flops at the same time in a parallel way. If
we see the circuit, the first flip-flop, FFA which is the least significant bit in this 4-bit
synchronous counter, is connected to a Logic 1 external input via J and K pin. Due to this
connection, HIGH logic across the Logic 1 signal, change the state of first flip-flop on every
clock pulse.

Next stage, the second flip-flop FFB, input pin of J and K is connected across the output of the
first Flip-flop. For the case of FFC and FFD, two separate AND gate provide the necessary logic
across them. Those AND gates create logic using the input and output from the previous stage
flip-flops.

Task 2:
Synchronous Down Counter
Slight changes in AND section, and using the inverted output from J-K flip-flop, we can
create Synchronous Down Counter. A 4-bit Synchronous down counter start to count from 15
(1111 in binary) and decrement or count downwards to 0 or 0000 and after that it will start a new
counting cycle by getting reset. In synchronous down counter, the AND Gate input is changed.
First Flip-flop FFA input is same as we used in previous Synchronous up counter. Instead of
directly feeding the output of the first flip-flop to the next subsequent flip-flop, we are using
inverted output pin which is used to give J and K input across next flip-flop FFB and also used as
input pin across the AND gate. Same as like the previous circuit, two AND gates are providing
necessary logic to the next two Flip-flops FFC and FFD.
Synchronous Counter Timing Diagram

In the above image, clock input across flip-flops and the output timing diagram is shown. On
each clock pulse, Synchronous counter counts sequentially. The counting output across four
output pin is incremental from 0 to 15, in binary 0000 to 1111 for 4-bit Synchronous up counter.
After the 15 or 1111, the counter reset to 0 or 0000 and count once again with a new counting
cycle.

For Synchronous down counter where the inverted output is connected across the AND gate,
exactly opposite counting step happens. The counter starts to count from 15 or 1111 to 0 or 0000
and then get restarted to start a new counting cycle and again start from 15 or 0000.

Conclusion:
Each student should write his/her own conclusion in provided report template.

You might also like