2022 6th International Conference on Devices, Circuits and Systems (ICDCS) | 21-22 April 2022 | Karunya Institute of Technology

and Sciences, Coimbatore, India.

Design of highly reusable interface for AHB

verification module
Mahendra Vignesh T D.S.Shylu Sam
Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering
Karunya Institute of Technology and Sciences Karunya Institute of Technology and Sciences
Coimbatore, India Coimbatore, India
[email protected] [email protected]
2022 6th International Conference on Devices, Circuits and Systems (ICDCS) | 978-1-6654-8094-9/22/$31.00 ©2022 IEEE | DOI: 10.1109/ICDCS54290.2022.9780767

A J Hernisha A Josephine Atchaya

Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering
Karunya Institute of Technology and Sciences Karunya Institute of Technology and Sciences
Coimbatore, India Coimbatore, India
[email protected] [email protected]

Abstract—Bus protocols are critical for the operation of a quicker advancement and reuse of verification environments
system as all communications are handled through the bus by and verification IP (VIP) all through the industry. It provides
following a predetermined structure. An IP is designed to standard libraries and databases for rapid development of the
verify if the system follows the specified protocol for seamless verification environment and inherits all the features of the
communications between multiple blocks in the system. As the system Verilog. The UVM architecture consists of a top
process technology decreases the number of sub-blocks in the block, an environment, agent, driver, sequencer, scoreboard,
system also increases thus the verification complexity and monitor [5] [10]. The connection between the
increases. In Traditional verification architecture, the design verification environment and the design is done through the
under test (DUT) signals are individually connected to the
interface as shown in Fig 1. The interface is instantiated and
verification environment by binding the interface to the sub-
blocks, signals are encapsulated and simplified to handle. In
the virtual interface is published to the configuration
this work, an AHB verification module is designed by database present in UVM. To communicate to the design the
employing the interface binding technique. components of the UVM such as driver and monitor must
invoke the virtual interface from the configuration database.
Keywords—AMBA AHB, UVM, Interfacing, Verification The traditional standard of connecting the test-bench to the
verification components has their limitations. In larger
designs, the maintenance of signals becomes hard as the no
I. INTRODUCTION
of signals increases. The signals must be manually
Due to expanding market necessity for low power, low instantiated and maintained for all instances. Any change to
region, minimal expense, and reduced process node size the the DUT hierarchy, every connection must be updated. It is
entire system is integrated inside a single chip. The internal necessary to design different test-bench environments for
sub-blocks must communicate and transfer data through the verifying at a different layer of integration. For verifying any
internal bus [6]. The common problem is transaction error standard protocol the connections must be driven in both
because of the incompatibilities between two blocks. directions between master and slave. That leads to defining
Ensuring the reliability of the data being communicated separate interfaces, which in turn doubles the maintenance.
becomes crucial. As the density of SoC increases the These can be overcome by binding the interface to the DUT.
handling of numerous hardcoded signals to the test
environment becomes hard. The lack of encapsulation
creates maintenance complexity. The signal mapping is
based on the DUT hierarchy. Any change in the hierarchy or
the change in instances, all the connection needs to be
updated. Manual instantiation must be made for every
instance of the subsystem. Encapsulation and binding the
interface to the DUT make it easy to handle. By binding the
interface to the DUT the change of the hierarchy or instance
does not affect the connections. Encapsulation of the
interface signals makes it easier to maintain. By binding the
interface to DUT the test environment can have direct access
to the RTL parameters. Hence enhancing the handling of the
signal between DUT and the best environment. By binding
the interface to the DUT, the average time spent on the Fig. 1. Traditional interface
interface is reduced. AMBA AHB bus protocol verification
module is designed by a binding method. B. Binding the interface
System Verilog allows the user to bind or add a portion
II. UVM INTERFACE of the code to the existing module. When added to the
module, System Verilog treats it as part of the module. This
A. Traditional interface is achieved using ‘bind’ a reserved keyword in System
The verification is done using Universal Verification Verilog [9]. This bind keyword is used to instantiate the
Methodology (UVM). UVM is a standard to empower interface module inside the design under test. By binding the
interface to the module the need for initiating the interface

Authorized licensed use limited to: KLE Technological University. Downloaded on November 23,2023 at 13:20:06 UTC from IEEE Xplore. Restrictions apply.
357
 2022 6th International Conference on Devices, Circuits and Systems (ICDCS) | 21-22 April 2022 | Karunya Institute of Technology and Sciences, Coimbatore, India.

inside the verification environment is eliminated and all the based the application and performance requirement [7]
instances of the module are modified. Hence any change in
the design hierarchy does not affect the interface connection
[3]. To bind the interface to the DUT the ports of the
interface must be declared as a wire by declaring it as wire
port coercion [4] is possible i.e. transfer of signal in both
directions. This can also be achieved by declaring the port as
input, but input cannot handle changes in port width. This
approach reduces the design time of multiple interfaces for
testing the master and slave side of the design as the signals
are driven in opposite direction. The created interface is
bound inside the design under test by [2].
bind<mоdulе_name> <intеrfacе_typе> <intеrfacе_namе>
The module_name is the target module, interface_type
denotes the interface and the interface_name is the name of
the current instance. An interface is created and bound to the
design under test shown in Fig 2. The interface is connected Fig. 3. Signals of AHB master
to the verification block by upward referencing.
AHB slaves cannot initiate a transfer from or to the
master. It samples the control and data signals given by the
master to further know about the transfer. The major signals
that contain information about the type of transfer are
HTRANS, HSIZE, HWRITE. HSIZE denotes the size of the
transfer. The HSIZE denotes the size of transfer warring
from 8 to 1024 bits. HWRITE denotes if the master is
performing the read or write operation. HTRANS signal
denotes the type of transfer to be performed, the transfer type
can be ideal, busy, non-sequential, and sequential. The slave
has HREADY and HRESP signals to represent the slave is
ready to accept the data read or write requests. Fig. 4.
describes the slave block with the input and output signals.

Fig. 2. Interface bound to DUT

III. AMBA ADVANCED HIGH-PERFORMANCE BUS

A. AMBA AHB
The AMBA AHB is used for high clock, frequency high-
performance system communication. AHB supports the
efficient communication between processors, off-chip
external memory, and on-chip memories interfaces. AMBA
AHB bus is intended on addressing high-performance
synthesizable design requirements [1]. The high-performance
master often includes a DMA controller or DSP modules.
AHB features include Burst transfers, Wider data bus
configurations, Split transactions, Non-tristate
implementation, Single-clock edge operation. Fig. 4. Signals of AHB slave
AHB master is capable of initiating write and read To design an interface to bind with the design the signals
operations by publishing control and address information. of the AHB master are declared as ports. By this, the
The control information includes the type of data transfer, designed interface can tolerate changes in bus width and
mode of operation, size of transfer, the direction of transfer, supports bidirectional signal thus reusable.
and the slave to be connected in case of multiple slave
configurations. Fig.3. represent the AHB master module with IV. RESULTS
the respective signals. AHB can accommodate multiple
master and multiple slave configuration [8]. Even at multiple A UVM verification environment is built to verify the
master multiple slave configuration there is only one bus that behavior of the AMBA AHB protocol. The verification tests
has to be shared for communication between the master and are designed to mimic all the types of transfer types provided
the slave devices. For seamless transfer the master has to by the protocol and verify them through simulation
request for the bus and transfer data when approved. The The types of transfer that are supported are non-
request is received by the arbiter and the transfer is approved sequential, incremental burst, and wrapping burst. The non-
based on the arbitration algorithm implemented in the arbiter. sequential transfer is indicated by the master through
The designer is given the liberty of choosing the algorithm HTRANS. A non-sequential transfer is performed if the

Authorized licensed use limited to: KLE Technological University. Downloaded on November 23,2023 at 13:20:06 UTC from IEEE Xplore. Restrictions apply.
358
 2022 6th International Conference on Devices, Circuits and Systems (ICDCS) | 21-22 April 2022 | Karunya Institute of Technology and Sciences, Coimbatore, India.

HTRANS is equal to 0010, and the transfer address is environment. The AHB is designed in a single master single
published by the master in HADDR. As the AHB data slave configuration. To minimize the manual effort on the
transfer takes place in a pipelined format the control signals verification phase, an interface that can be bound to the
are sent in one clock cycle and the data signals are sent in the design to be tested is employed. By binding the interface to
next clock cycle Fig. 5 shows the non-sequential transfer. the design the signals are encapsulated and become easy to
handle. The designed interface becomes more tolerant to
data bus width changes thus the reusability increases. It also
enables the transfer of data in both directions further
reducing the need for separate interfaces for verifying
master and slave blocks of the design. With the change in
the interface module, the functionality of the protocol is not
violated and all the features of AHB such as wrapping bust,
incremental burst are verified.
Fig. 5. Non-sequential transfer
ACKNOWLEDGMENT
The incremental bust is a type of transfer that is used for
continuous address operations. The type of burst is indicated
by the HBURST signal. HBURST signal with values 1,3,5,7 For facilitating this research work, the authors would
indicate the incremental of unspecified length (INCR) (till like to thank the management of Karunya Institute of
HTRANS indicate an ideal transfer), 4-beat incrementing Technology and Sciences and the VLSI lab at the School
burst (INCR4), 8-beat incrementing burst (INCR8), 16-beat of Engineering and Technology, ECE Department at
incrementing burst respectively (INCR16). Fig. 6 shows the KITS.
incremental burst between the master and the slave.

REFERENCES

[1] AMBA specification, version 2.0. ARM Ltd., 1999

[2] D. Larson, “UVM Harness Whitepaper: The Missing Link in
Connectivity”, Synapse Design Automation 2011
[3] Vance, J. Montesano, K. Johnston, “Verification Prowess with the
Fig. 6. Incremental burst transfer UVM Harness”, SNUG Austin, October 2017..
The wrap burst is similar to the incremental burst. Same [4] Jeff Vance, Jeff Montesano, Kevin Vasconcellos and Kevin Johnston,
as incremental burst the address is incremented based on “My Testbench Used to Break! Now it Bends: Adapting to Changing
Design Configurations”, Verilab Inc. , DVCon 2018
HSIZE, but on reaching the upper limit the address is
[5] Deeksha, L., and B. R. Shivakumar. "Effective design and
wrapped to the lower limit address. The type of burst is implementation of AMBA AHB bus protocol using Verilog." In 2019
indicated by the HBURST signal. HBURST signal with International Conference on Intelligent Sustainable Systems (ICISS),
values 2,4,6 indicates the wrapping of 4-beat wrapping burst pp. 1-5. IEEE, 2019.
(WRAP4), 8-beat wrapping burst (WRAP8), 16-beat [6] K. Dilip and V. P. A. M, “Design and Verification of AHB Protocol
wrapping burst (WRAP16) respectively. Fig. 7 shows the Using System Verilog and Universal Verification Methodology (
wrapping burst between the master and the slave. UVM ),” Int. J. Eng. Res. Appl., vol. 11, no. 7, 2021.
[7] S. I. Narendrappa, S. Y. RadhaSwamy, and L. He, “Performance
verification of multi-master AHB bus system,” Lect. Notes Eng.
Comput. Sci., vol. 2235, pp. 4–7, 2018
[8] Deeksha, L., and B. R. Shivakumar. "Effective design and
implementation of AMBA AHB bus protocol using Verilog." In 2019
International Conference on Intelligent Sustainable Systems (ICISS),
pp. 1-5. IEEE, 2019.
[9] “Standard for SystemVerilog – Unified Hardware Design,
Specification, and Verification Language”, IEEE Std 1800-2012.
Fig. 7. Wrapping burst transfer [10] Ni, Wei, and Jichun Zhang. "Research of reusability based on UVM
verification." In 2015 IEEE 11th International Conference on ASIC
(ASICON), pp. 1-4. IEEE, 2015.
V. CONCLUSION
In this work, the AMBA AHB protocol developed by
ARM is designed and verified using a UVM verification

Authorized licensed use limited to: KLE Technological University. Downloaded on November 23,2023 at 13:20:06 UTC from IEEE Xplore. Restrictions apply.
359