DESIGN OF UNIFIED LDPC AND POLAR CODE

DECODER FOR 5G COMMUNICATION

Submitted in partial fulfilment of the requirement of the degree of

Master of Technology
in

Electronic Instrumentation and Embedded Systems

By

PRIYA ANAND
Roll No. 22ECM1S04
Supervisor:
Prof. P. MURALIDHAR
Associate Professor
NIT Warangal

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL– 506004
TELENGANA STATE, INDIA
DECEMBER – 2023
 NATIONAL INSTITUTE OF TECHNOLOGY
WARANGAL

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING

CERTIFICATE
This is to certify that the project synopsis entitled “Design of Unified LDPC and Polar Code
Decoder for 5G Communication” is a bona-fide record of work carried out by PRIYA
ANAND (Roll No. 22ECM1S04) and submitted in fulfilment for the award of degree of
Master of Technology in Electronics & Communication Engineering with specialisation in
Electronic Instrumentation And Embedded Systems from National Institute of Technology,
Warangal.

Supervisor: Head of Department:

Prof. P. Muralidhar Prof. Vakula D
Associate Professor Professor
Department of ECE, Department of ECE,
NIT Warangal NIT Warangal
 ACKNOWLEDGEMENT
I wish to express my deep sense of respect and gratitude to my supervisor Prof. P. Muralidhar
(Associate Professor), Department of Electronics & Communication Engineering, National
Institute of Technology, Warangal. It has been a great privilege to work under his able and valuable
guidance. His continuous encouragement and kind cooperation have been a constant motivation
behind the successful continuation of this project. I also want to express my sincere gratitude to
Prof. Vakula (Head of Department of Electronics & Communication Engineering), and our faculty
advisor Dr. Prakash Kodali. (Assistant Professor), National Institute of Technology, Warangal,
who always encouraged me and assisted me whenever I needed. A word of gratitude also goes to
all of my faculty members who equipped me with the right kind of theoretical knowledge during
the first and second semesters of my M.Tech course. I am greatly indebted to my parents and friends
who constantly encouraged me to carry out my project work at the level best.

Priya Anand
M.Tech(EI&ES)
Roll No. – 22ECM1S04
 Abstract
With Low Density Parity Check (LDPC) codes and polarity codes designated as fifth-
generation standard codes (5G) enhanced mobile broadband scenario (eMBB), decoding an
architecture that supports simultaneous decoding control and data planes become necessary on
the terminal side fulfills the additional requirement of 5G network implementation. Because
Special structure of LDPC codes according to Release 15 (R15) 5G standard, a direct extension
of the existing one a reconfigurable system is usually complex. That's why here the project
proposes a unified decoding architecture that can be econfigured to either LDPC codes or
polarity codes. For different people differences between the two codes, such as parity check
matrices, codeword lengths and iterative methods, a common decoding algorithm is
implemented by reorganizing the basic decoding functions into one add-compare-add pattern
for both codes. Then with a pipeline respectively, the structure of the Reconfigurable Decoding
Unit (RDU) which is fully compatible with all decoding models R15 standard and proposed
with multiple levels of parallelism and reconfiguration system was implemented to improve
hardware utilization and decoding efficiency. This innovative approach ensures the successful
deployment of 5G communication systems in eMBB scenarios, meeting the critical
requirements of high data rates and low latency.
CONTENTS
Abstract

CHAPTER -1:Introduction

1.1 Overview…………………………………………………………………….1-3

1.2 Problem Statement……………………………………………………..........4

1.3 Objective………………………………………………………….….……...5

1.4 Advantages and Disadvantages…………………………………………….6-7

CHAPTER -2

2.1 Literature Survey…………………………………………………………...8-10

CHAPTER – 3: Theoretical Background

3.1 Channel coding………………………………………………………………11

3.2 Telecommunication standards……………………………………………….12

3.3 LDPC encoding and decoding……………………………………………….13

3.4 Methods/ Algorithms………………………………………………………...14-15

CHAPTER-4: System architecture and design

3.1 Work Flow…………………………………………………………………...16-17

3.2 Proposed Architecture……………………………………………………….18-20

CHAPTER-5: Simulation Results

5.1 RDU in different modes……………………………………………………. 21-23

5.2 Utilization Summary………………………………………………………...25

Conclusion………………………………………………………………………26

Future scope…………………………………………………………………….27

References………………………………………………………………………28
LIST OF FIGURES
1. Tanner Graph…………………………………………………………………2
2. Flow diagram of proposed work……………………………………………...16
3. Flow diagram of Belief Propagation Algorithm……………………………...17
4. Block diagram of RDU……………………………………………………….18
5. Block Diagram of Decoder…………………………………………………...20
 CHAPTER 1
Introduction
1.1 Overview
The advent of 5G networks has ushered in a new era of connectivity, offering not only blazing-
fast data speeds but also the promise of unprecedented levels of device interconnectivity.
However, as the data flows through the complex and dynamic wireless channels of 5G
networks, it encounters a myriad of challenges. These challenges include signal attenuation,
interference, and various forms of noise that can corrupt data during transmission. To ensure
the reliability and data integrity crucial for the success of 5G, sophisticated error correction
techniques are paramount. Among these techniques, Low-Density Parity-Check (LDPC) codes
have risen to prominence as a cornerstone technology for error correction in 5G networks.

LDPC codes are powerful error correction codes known for their exceptional performance and
efficiency in mitigating errors that occur during data transmission. They are particularly well-
suited for 5G networks due to their ability to achieve near-Shannon limit error-correcting
capabilities. LDPC codes have a unique structure characterized by a sparse parity-check matrix,
making them amenable to efficient decoding algorithms. This characteristic makes LDPC
decoders an essential component of 5G network infrastructure.

In this project, I will delve into the significance of LDPC decoders in the context of 5G
networks, exploring their architecture, capabilities, and contributions to the seamless and high-
performance operation of the 5G ecosystem. I will also discuss how LDPC decoders meet the
stringent requirements of 5G networks, including ultra-low latency, high data rates, and
massive device connectivity, ensuring that the promise of 5G is realized with the utmost
reliability and efficiency. Furthermore, I will examine the role of LDPC decoders in enabling
innovative 5G applications across various industries, from autonomous vehicles to the Internet
of Things (IoT). By the end of this project, I will have a comprehensive understanding of why
LDPC decoders are a critical enabler of the 5G revolution and how they contribute to meeting
the diverse and demanding requirements of this transformative technology.

Low-Density Parity-Check (LDPC) decoders are integral components in 5G networks due to

their widespread usage and numerous merits.

1
Here, it can be defined N bit long LDPC code in terms of M number of parity check equations
and describing those parity check equations with a M x N parity check matrix H.

Where,

M – Number of parity check equations

N – Number of bits in the codeword

Fig. 1.1 Tanner Graph

Here fi are check nodes and are variable nodes ck

Where I =0,1,2,3 and k =0,1,2,3,4,5,6,7

Row weight (wr) - number of ‘1’s in a row (Number of symbols taking part in a parity
check ) and Column weight (wc) - number of ‘1’s in a column.

The parity check matrix defines a rate R =K/N, (N,K) code where K=N-M

Codeword is said to be valid if it satisfies the syndrome calculation :

Z = CHT

Tanner graph is a graphical representation of parity check matrix specifying parity check
equations and Tanner graph consists of N number of variable nodes and M number of check
nodes.

2
Mathematical foundations of polar codes lay on the polarization effect of the matrix

1 0
G2 =
1 1
In an (N, K) polar code of length N = 2n , the polarization effect establishes N virtual channels,
through which a single bit ui is transmitted. Each bit-channel, or subchannel, has a different
reliability; message bits are allocated to the K most reliable channels. The polar code is hence
defined by the transformation matrix GN = (G2 )^n i.e. as the n-th Kronecker power of the
polarizing matrix, and either the frozen set F of size N − K, or its complementary information
set I = FC of size K, where I and F are subsets of the index set {0,1,2……2n-1}. A codeword d
is calculated as

d = u. GN (1.1)

where the input vector u = {u1 ,u2 , . . .uN-1 } is generated by assigning ui= 0 if i ∈ F, and
storing information in the remaining elements. Each index i identifies a different bit-channel.

d = [u1 u2]G2 = [ u1 + u2 u2} (1.2)

Fig.1.2 Binary tree representation of 2nd Kronecker power of matrix

G4 = G2 x G2 (1.3)

Fig.1.3 Binary tree representation of 4th Kronecker power of matrix

3
1.2 Problem Statement
In the context of fifth-generation (5G) enhanced Mobile Broadband (eMBB) scenarios, the
adoption of Low-Density Parity-Check (LDPC) codes and polar codes as standard coding
schemes presents a pressing challenge. The fundamental problem revolves around the
development of a decoding architecture capable of simultaneously supporting the decoding of
control and data planes, aligning with the rigorous demands of 5G network deployment.

The primary issues to be addressed are structural complexity and algorithmic adaptation. The
differences between LDPC and polar codes in terms of parity-check matrices, codeword
lengths, and iterative decoding methods require the development of a unified decoding
algorithm capable of accommodating both code types.

The challenge extends to the successful implementation of this unified decoding architecture
in both Field-Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit
(ASIC) technologies, ensuring state-of-the-art performance in terms of throughput and area
efficiency.

4
1.3 Objective
The primary objective of this project is to design, develop, and implement a versatile decoding
architecture tailored to the demands of 5G enhanced Mobile Broadband (eMBB) scenarios.
This architecture should achieve the following specific goals:

1. Create a decoding system capable of seamlessly accommodating both Low-Density

Parity-Check (LDPC) codes and polar codes, in accordance with the 5G Release 15
(R15) standard.
2. Develop a unified decoding algorithm that can effectively decode both LDPC and polar
codes, taking into account their distinct structural characteristics, parity-check matrices,
codeword lengths, and iterative decoding methods.
3. Design the decoding architecture with a focus on maximizing hardware utilization and
decoding efficiency, incorporating multiple levels of parallelism to meet the stringent
requirements of 5G networks.

By accomplishing these objectives, the project aims to provide 5G networks with a versatile,
high-performance, and efficient decoding solution that ensures reliable data transmission in the
eMBB era, contributing to the seamless deployment of 5G technology.

5
 CHAPTER 2
2.1 Literature Survey

S.No. Title of Paper Author Year of Remarks

Publication
1 A Reconfigurable and Shan Cao IEEE This paper proposed a
Pipelined Architecture for joint LDPC/polar
Ting Lin Transactions on
Standard-Compatible decoding algorithm is
Shunqing Vehicular introduced
LDPC and Polar Decoding
based on the BP
Zhang Technology
decoding algorithm.
Shugong Xu -2021 Based on that, a
reconfigurable
Chuan
decoding architecture
Zhang is proposed for
standard compatible
decoding of LDPC
codes and polar codes.
In the proposed
decoder, the structure
of basic decoding
units, decoding
dataflowand the
parallelism scheme are
all optimized to
improve
throughput and
hardware utilization.
2 A Universal Efficient Suwen Song IEEE This paper proposed
Circular-Shift Network for to develop an
, Hangxuan Transactions on
Reconfigurable Quasi- improved Banyan
Cui , and Very Large network (IBN) by
Cyclic LDPC Decoders
subtly adjusting the
Zhongfeng Scale
order of permutations,
Wang Integration which facilitates a
noticeable reduction
(VLSI) Systems
on area consumption
-2022 and critical path.
3 Design of High- Hangxuan IEEE This paper introduced
Performance and Area- an efficient
Cui Transactions on
Efficient 5G LDPC decoder
Decoder for 5G LDPC Fakhreddine Circuits and architecture. In the
proposed architecture,
Codes Ghaffari Systems-2021
first, a layer merging
Jun Lin technique benefitting
from the orthogonal
6
 Khoa Le structure of 5G LDPC
codes is proposed,
Zhongfeng
which could reduce
Wang the number of clock
cycles by 28.3%. By
David
further incorporating
Declercq with the proposed split
storage method, the
CTV memory
consumption could be
reduced.
4 High-Throughput Non- Youngjoo IEEE Journal of This paper proposes a
Binary LDPC Decoder high-throughput
Lee Solid-State
Architecture Using Parallel NBLDPC
Jeongwon Circuits decoder architecture
EMS Algorithm
by proposing the
Choe -2022
pEMS decoding
algorithm. Based on
the parallel ECN/EVN
operations, the
proposed decoder
manages multiple
message entries at a
time, significantly
reducing the number
of cycles per iteration
compared to the
previous serialized
decoding methods.
5 An Efficient FPGA R. Varshini International The Hardware
Implementation of LDPC Implementation of the
Devi Conference on
Decoder for 5G New LDPC decoder is done
Radio S. Rajaram Recent in FPGA using the
NMS Algorithm has
Advances in
been realized. The
Electrical, perplexity of the 5G
NR LDPC decoder
Electronics,
execution is also
Ubiquitous decreased with the
help of the Circular-
Communication,
Shift-Register
and approach and the
integrated circuit
Computational
design is done using
Intelligence Verilog.

7
 (RAEEUCCI)
2023
6. Performance Balanced Bingbing International This paper proposed a
General Decoder Design performance balanced
Wang Conference on
for QC-LDPC Codes LDPC
Using Vivado HLS Jing Kang Electronics decoder using Vivado
HLS. The decoder
Yan Zhu Information and
takes advantage of
Emergency the quasi-cyclic
properties of the PCM
Communication-
of QC-LDPC codes
2021 and uses compressed
storage and distributed
storage strategies
to reduce resource
usage and avoid
access conflicts.
7. A New VLSI Architecture Anuj Verma IEEE This paper describes
of Next-Generation QC- detail architectural
Rahul International
LDPC Decoder for 5G aspects of all the
New-Radio Wireless- Shrestha Symposium on internal modules of
Communication Standard QC-LDPC
Circuits and
decoder that is
Systems-2020 compliant to 5G
technology using the
specific BG1
matrix.

8
 CHAPTER 3

Theoretical Background
This chapter contains background information on channel coding and telecommunications.
This chapter also discusses related work on the LDPC channel coding chain, LDPC encoding
and decoding algorithms.
3.1 Channel coding
Channel coding has appeared since Shannon applied probability theory to study the
communication system. The errors induced by the noisy channel can be reduced to the desired
level by using a proper coding scheme for a given transmission rate less than or equal to channel
capacity. Channel coding can minimize the channel noise by using an encoder, which encodes
the information bits by adding redundant bits, and a decoder, which exploits the redundant bits
and retrieves the information bits using a decoding algorithm. Convolutional and Turbo codes
are used for Fourth-generation(4G) long-term evolution (LTE). In 3GPP 5G standard, Polar
codes and LDPC codes are recommended for 5G NR. Polar codes are applied to 5G NR control
channels and LDPC codes are suitable for 5G NR shared channels.
Polar codes
Polar codes were firstly proposed by Arikan in 2009. The capacity achievability of polar codes
can be proved with a specific realization .Moreover, simple successive cancellation decoding
is enough to achieve the output. In 5G, control information is usually transmitted with a small
amount of information bits and small block size, so low code rate with good performance in
lower BER is required. Polar codes can satisfy this requirement.
LDPC codes
Gallager invented LDPC codes in 1962 . LDPC codes are linear block codes based on sparse
parity-check matrix. It is forgotten for dozens of years because of the limited computation
ability. In recent years, LDPC codes attract more attention because of their decoding
algorithms, excellent error-correcting capability, and their performance close to the Shannon
limit for large code lengths. 5G needs to support high throughput up to 20 Gbps and a wide
range of block sizes with different code rates for the data channels and hybrid automatic repeat
request (HARQ). LDPC codes can fulfil the requirements. The base graphs defined in 3GPP
TS 38.212 are structured parity-check matrix, which can efficiently support HARQ and rate
compatibility that can support arbitrary amount of transmitted information bits with variable
code rates.

9
3.2 Telecommunication
3.2.1 3GPP
3GPP defines kinds of standards for 5G. In this project, 3GPP TS 38.212 V16.4.0 release 16.0
is mainly used. 3GPP TS 38.212 specifies the coding, multiplexing and mapping to physical
channels for 5G NR. The specifications of LDPC coding, which is also called LDPC encoding
and decoding chain, will be implemented in this project. The details of LDPC encoding and
decoding chain are explained in below section .
3.2.2 5G NR shared channel
The 5G NR shared channel, including Physical Downlink Shared Channel(PDSCH) and
Physical Uplink Shared Channel (PUSCH) carry the data information. The PDSCH is not only
the main physical channel of data transmission, but also for transmission of, for example,
paging information, Background 7random-access response messages, and delivery of parts of
the system information. PUSCH is the uplink counterpart to the PDSCH.
3.2.3 Modulation
In digital modulation, an analog carrier signal is modulated by a discrete signal. Digital
modulation methods can be considered as digital to analog conversion and the corresponding
demodulation or detection as analog to digital conversion. In this project, Phase-shift keying
(PSK) which conveys data by modulating the phase of a constant frequency reference signal
(the carrier wave) is used for modulation. According to 3GPPTS 38.214, Binary phase-shift
keying (BPSK), Quadrature phase-shift keying (QPSK), 16QAM, 64QAM, 256QAM are used
for modulations. The details of different kinds of PSK, 3GPP TS 38.211 is recommended. The
modulation and demodulation modules exist on 5G_lls. In this project, BPSK is used to test
different LDPC decoding algorithms. QPSK modulation is used when the optimized LDPC
decoding algorithms were implemented on 5Gs.
2.2.4 SNR and Eb/N0
SNR is defined as the ratio of signal power to the noise power, often expressed in decibels.
Energy per bit to noise power spectral density ratio (Eb/N0) is a normalized SNR, also known
as the "SNR per bit". The larger the value of Eb/N0 or SNR, the stronger of the signal. Eb/N0
and SNR are usually expressed in the form of decibel (dB). The relation between SNR and is
shown in equation below
SNR = 2R(Eb=N0) Where R is the code rate.

10
3.3 LDPC encoding
Due to the structure and feature of base graphs according to 3GPP TS 38.212, there are many
efficient LDPC encoding algorithms. A novel efficient encoding method and a high-throughput
low-complexity encoder architecture for 5G NR LDPC was proposed. By storing the quantized
value of the permutation information for each sub-matrix instead of the whole parity-check
matrix, the required memory storage size is considerably reduced. Several encoding algorithms
that entirely use the sparseness of the parity-check matrix were studied. The core of the
algorithms isthe diagonal sub-matrix in base graphs. The base graph 1 and base graph 2 in
3GPP TS 38.212 have the same structure which can be divided into 6sub-matrices. Sub-matrix
B is a unique matrix that corresponds to the first set of parity bits, and the first column of sub-
matrix B weights 3, while other columns of sub-matrix B have a double diagonal structure.
Double diagonal structure is useful in LDPC encoding, and it can work nicely and efficiently
to compute the parity bits. In this project, for the LDPC encoding, double diagonal structure in
base graphs was fully utilized.
LDPC Encoding aims to add redundant bits to the message from the sender to get codeword
which will be transmitted to the receiver. Assume the message to be encoded is denoted by
m1;m2;m3; …..mK, where K is the number of message bits. The redundant bits are called
parity bits denoted by p1; p2; p3; ….. pL, where L is the number of the parity bits. The encoded
message is called codeword denoted by c1; c2; c3;…… cN, where N is the number of encoded
message bits.

The message bits vector m , parity bits vector p and codeword bits vector

(3.1)

(3.2)

3.4 LDPC decoding

The LDPC codes are generally decoded by the message-passing algorithms such as the belief
propagation (BP) algorithm, which iteratively exchanges the messages through the edges
between variable nodes and check nodes. The BP algorithm achieves near optimal decoding

11
performance but suffers from high computational complexity. To find a better trade off
between performance and complexity, some efficient decoding algorithms are proposed using
Min-Sum (MS) approximation. A simple algorithm for implementation is the Min-Sum
Algorithm (MSA), but the outputs from variable nodes in MSA decoding are over estimated
compared to SPA. There are many methods to optimize MSA including OMSA, linear
approximation, self-corrected min-sum(SCMS) algorithms. A decoding scheme using the
linear approximation and the modified message passing can achieve performance very close to
that of the BP decoding. But it is difficult to hardware implementation because of heavy row
weights. A hybrid algorithm for the LDPC codes in 5G, where the normalised MSA decoding
and the linear approximation are applied has only a slight increase in complexity concerning
the NMSA and improved performance much closer to the BP decoding, especially for the low
rate codes. The proponents of LDPC codes have highlighted that inflexible LDPC decoders
can achieve throughputs of 20 Gbps with particularly attractive hardware and energy. Hybrid
turbo/LDPC solution for 5G is proposed. A flexible turbo code provides channel coding for
most use cases, but for 20 Gbps downlink use cases, such as fixed wireless broadband, the
channel coding is supported by an inflexible LDPC code. This hybrid approach can meet all of
the 5G requirements while offering hardware and energy efficiencies that are significantly
better than those of an LDPC only.

3.5 Sum Product Algorithm (SPA)

Sum Product Algorithm which is also known as Belief Propagation Algorithm (BP) is a basic
soft decision decoding with messages passed as probabilities. The input to LDPC decoder using
log-likelihood ratios (LLR) value, the following sum product decoding algorithm is based on
the decoding algorithm.

(3.3)

Where L(ci) is the input LLR to the decoder.

The variable nodes operation is shown in equation

12
 (3.4)

The check nodes operation is shown in equation

(3.5)

(3.6)

Where L(Qi) is the output LLR from the decoder and can be used to make decision.

Min-Sum Algorithm (MSA)

Min-Sum Algorithm(MSA) for LDPC decoding is a reduced complexity decoding algorithm
with min-sum approximation compared to Sum Product Algorithm(SPA). The operation on
check nodes is the same for both Min-Sum algorithm and Sum Product Algorithm. The
difference is the operation on variable nodes. The Min-Sum Algorithm (MSA) is an effective
approach for decoding Low-Density Parity-Check (LDPC) code which minimizes the complex
computational load and requirements of the Belief Propagation Algorithm (BPA). The Min-
Sum Algorithm for LDPC decoders is an iterative algorithm that uses soft-decision information
from a noisy communication channel to decode LDPC codes. The algorithm performs by
repeatedly transferring messages between parity check nodes and variable nodes, attempting
to find the most likely codeword given the channel information. The algorithm is based on the
min-sum approximation, which utilizes the lowest-cost approximation of the Sum-Product
Algorithm (SPA). The MS Algorithm is mostly employed in the design of 5G LDPC decoders,
owing to its effortless and excellent productivity.

(3.7)

An approximation which is shown in equation above which is used for Min-Sum Algorithm.
For Min-Sum Algorithm, other computations are the same with SPA.

(3.8)

13
 CHAPTER 4

System architecture and design

4.1 Work Flow

Initialisation

Message Passing
Algorithm

Iteration Control & Error

Correction

Testing and Verification

Fig. 4.1. Flow diagram of proposed work

1. Initialization: Initialize the necessary parameters for LDPC code, such as the code
length, code rate, and the parity-check matrix.
2. Message Passing Algorithm: Implement the belief propagation algorithm, which
involves the following steps:
Message Update: Compute and update messages between variable nodes and check
nodes.

Check Node Operation: Perform check node operations based on incoming messages.

Variable Node Operation: Update variable node values based on check node messages.

14
 Fig. 4.2. Flow diagram of Belief Propagation Algorithm

3. Parallel Architecture: Implement parallel processing for improved throughput. This

involves dividing the decoding process into multiple stages or using parallel hardware
resources like adders and multipliers.
4. Iteration Control: Decide on the number of iterations for the decoder. LDPC decoding
is an iterative process, and we'll need to control the number of iterations before
declaring a decoded message.
5. Error Correction: After decoding, implement error correction by selecting the most
likely codeword or performing any post-processing necessary.
6. Testing and Verification: Develop a testbench to verify the functionality of your
LDPC decoder. Test it with various input messages and known error patterns to ensure
it performs error correction correctly.

15
4.2 Reconfigurable Decoding Unit
A reconfigurable decoding unit (RDU) is introduced in this part, which works as the basic
decoding unit for both codes, based on the combined decoding characteristic of LDPC codes
and polar codes. The RDU structure is organized in the "ADD-CMPa- ADD" pattern, as shown
in Fig.. The RDU's datapath is separated into five pipeline phases that can be fully pipelined.
The ADD array is made up of multiple elements in the first and last phases. The key component
that can be employed is parallel ADD units.to compute for LDPC codes, and for the use of
polar codes. Several CMPa units are used in the middle three stages. integrated into each step
for both minimum-sum operations codes. Every RDU operates using a very-long instruction
word (VLIW) system, in which the control data is generated offline prior to decoding and
utilized to reconfigure the device. By three ADD units from stage 1 (or stage 5) and
reconfiguration three CMPa units (shown in Figure 5 by a CMPax3 unit)can function as a polar
code decoding PE starting at stage 2–4. In the same way, six ADD units (four from Stages 1
and 2 and six CMPa units (the CMPax6 unit in stage 2) is equivalent to two polar code decoding
PEs. ForLDPC codes, an update to a check node usually needs all 5 phases of an RDU.
Therefore, one or two checknode updates can be processed in parallel depending on the
connectivity with corresponding variable nodes.

Fig. 4.3 Block diagram of RDU

16
According to 3GPP R15 for the data channel coding, LDPC codes shall support base graph 1
(BG1) and base graph 2 (BG2), two types of rate compatible base graphs. Higher data rates
and longer block lengths are associated with BG1, whereas lower data rates and shorter block
lengths are associated with BG2. LDPC codes are encoded and decoded using the H matrix,
which has 46 × 68 and 42 × 52 dimensions for BG1 and BG2, respectively.

A check node and the variable nodes is attached to are modified in accordance with the LDPC
codes' optimum decoding strategy. Nj is the number of positive integers in the relevant row of
the H matrix, assuming that the number of variable nodes linked to the same check node is
represented by this symbol. Verify that nodes in the same sub-matrix have the same Nj due to
a characteristic of the H matrix. Each check node update necessitates 2×Nj ADD units and N2j−
2Nj CMPa units, per the rule. The range of values for Nj in BG1 is 3 to 19, but in BG2, the
range is 3 to 10 . The check nodes with Nj ≤ 5 accounts for a large proportion, while the value
of Nj is more than 11 only for check nodes in the few sub matrices of BG1. Therefore in the
structure of the RDU, a maximum Nj of 11 is supported, which can be either used for the check
node with Nj less than 11, or used for multiple check nodes that the sum of Nj is no more than
11. The RDU must calculate twice for check nodes whose Nj is more than 11. In each cycle,
check nodes without shared variable nodes can be updated all at once, whereas check nodes
with shared variable nodes need to be updated sequentially. Thus, if hardware permits, check
nodes within the same lifting block and check nodes within other lifting blocks may be updated
concurrently provided that their corresponding sub-matrices are orthogonal. Different lifting
blocks are processed concurrently in the same RDU if they do not share any variable nodes and
the sum of Nj does not exceed 11, hence improving hardware utilization and speeding up
computation. If there are numerous RDUs in the same block, check nodes can be performed in
parallel. This improves the RDU's hardware utilization in the LDPC decoding mode and
reduces the decoding latency in a single iteration by 12 × Z cycles for BG1 and 11 × Z cycles
for BG2. In the polar decoding mode, the RDU is reconstituted into several separate PEs, each
of which is a basic decoding unit for the calculation.

Reconfigurable Decoder

For joint decoding of LDPC codes and polar codes, a reconfigurable decoder architecture is
proposed based on the joint decoding algorithm and the RDU structure. As shown in Fig., the
decoder is composed of an RDUcluster, a decoding controller, a memory controller and the
reconfigurable memory. The decoder has 2 decoding modes (LDPC mode and polar mode), 20

17
decoding patterns to be compatible with the 5 G R15standard. The controlling information
generated accordingly for decoding units and memory by the decoding controller and memory
controller.

Fig. 4.4 Reconfigurable Decoder

18
 CHAPTER 5

Simulation Results

5.1 LDPC mode

Fig.5.1 Waveform for RDU in LDPC mode

19
Fig. 5.2 RTL view of RDU in LDPC mode

20
Fig.5.3 Waveform for RDU in Polar mode

21
Fig. 5.4 RTL view of RDU in Polar mode

22
5.2 Resource Utilization for RDU

Polar mode LDPC mode

LUT – 916/143600 LUT – 740/134600

IO – 160/400 IO – 176/400

Table 5.1 Resource utilisation for each modes

23
 Conclusion
In the realm of 5G communication, the synthesis of LDPC (Low-Density Parity-Check) and
polar codes through a reconfigurable decode unit (RDU) cluster emerges as a pivotal strategy
to cater to the diverse requirements inherent in contemporary wireless networks. As 5G
encompasses various application scenarios such as enhanced mobile broadband (eMBB),
massive machine-type communication (mMTC), and ultra-reliable low-latency communication
(URLLC), LDPC codes and polar codes exhibit specialized strengths tailored to distinct use
cases. LDPC codes, known for their adaptability and high throughput, find suitability in
scenarios demanding extensive data transfer, while polar codes, with their proficiency in low-
latency and reliability-critical situations, prove invaluable for ultra-responsive and dependable
communication. The integration of both coding schemes within a reconfigurable architecture
offers a unified solution that can dynamically switch between LDPC and polar decoding based
on prevailing communication needs. The RDU architecture for both LDPC and Polar code is
designed. This flexibility optimizes error correction performance in real-time, enabling the 5G
system to seamlessly adapt to varying channel conditions, traffic loads, and latency
requirements. The holistic approach of a unified architecture not only enhances error correction
capabilities but also future-proofs the system for evolving standards, ensuring its continued
relevance and effectiveness amid the dynamic landscape of wireless communication.

24
 Future scope
The integration of LDPC and polar codes in a reconfigurable decode unit (RDU) cluster sets
the stage for further exploration into adaptive and intelligent decoding schemes. As 5G
standards continue to evolve and new communication scenarios emerge, the versatility of the
unified architecture ensures its applicability to future coding schemes or modifications in the
standard. Future research could delve into enhancing the adaptability of the decoding algorithm
to accommodate upcoming 5G use cases beyond eMBB, such as massive machine-type
communication (mMTC) and ultra-reliable low-latency communication (URLLC).
Additionally, exploring ways to further optimize the reconfigurable decoding unit (RDU) for
increased efficiency and reduced power consumption could be an avenue for future
investigations.

25
 References
1. S. Cao, T. Lin, S. Zhang, S. Xu and C. Zhang, "A Reconfigurable and Pipelined
Architecture for Standard-Compatible LDPC and Polar Decoding," in IEEE
Transactions on Vehicular Technology, vol. 70, no. 6, pp. 5431-5444, June 2021, doi:
10.1109/TVT.2021.3075232.
2. S. Song, H. Cui and Z. Wang, "A Universal Efficient Circular-Shift Network for
Reconfigurable Quasi-Cyclic LDPC Decoders," in IEEE Transactions on Very Large
Scale Integration (VLSI) Systems, vol. 30, no. 10, pp. 1553-1557, Oct. 2022, doi:
10.1109/TVLSI.2022.3190317.
3. H. Cui, F. Ghaffari, K. Le, D. Declercq, J. Lin and Z. Wang, "Design of High-
Performance and Area-Efficient Decoder for 5G LDPC Codes," in IEEE Transactions
on Circuits and Systems I: Regular Papers, vol. 68, no. 2, pp. 879-891, Feb. 2021, doi:
10.1109/TCSI.2020.3038887.
4. J. Choe and Y. Lee, "High-Throughput Non-Binary LDPC Decoder Architecture Using
Parallel EMS Algorithm," in IEEE Journal of Solid-State Circuits, vol. 57, no. 10, pp.
2969-2978, Oct. 2022, doi: 10.1109/JSSC.2022.3176347.
5. R. V. Devi and S. Rajaram, "An Efficient FPGA Implementation of LDPC Decoder for
5G New Radio," 2023 International Conference on Recent Advances in Electrical,
Electronics, Ubiquitous Communication, and Computational Intelligence
(RAEEUCCI), Chennai, India, 2023, pp. 1-5, doi:
10.1109/RAEEUCCI57140.2023.10134365.
6. B. Wang, J. Kang and Y. Zhu, "Performance Balanced General Decoder Design for
QC-LDPC Codes Using Vivado HLS," 2021 IEEE 11th International Conference on
Electronics Information and Emergency Communication (ICEIEC)2021 IEEE 11th
International Conference on Electronics Information and Emergency Communication
(ICEIEC), Beijing, China, 2021, pp. 26-30, doi: 10.1109/ICEIEC51955.2021.9463813.
7. A. Verma and R. Shrestha, "A New VLSI Architecture of Next-Generation QC-LDPC
Decoder for 5G New-Radio Wireless-Communication Standard," 2020 IEEE
International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020, pp.
1-5, doi: 10.1109/ISCAS45731.2020.9181188.

26