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PE-EC-505A –L13: Introduction to Shrink-down

Approaches

module

module
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PE-EC-505A –L14: Non Ideal Effects in MOSFETs: Part-I

Non-ideal Effects
As with any semiconductor device, the experimental characteristics of MOSFETs deviate to
some degree from the ideal relations that have been theoretically derived using the various
assumptions and approximations. Here, we consider five effects that cause deviations from the
assumptions used in the ideal derivations. These effects are subthreshold conduction, channel
length modulation, mobility variations, velocity saturation, and ballistic transport.

1. Subthreshold Conduction
The ideal current–voltage relationship predicts zero drain current when the gate-to-source
voltage is less than or equal to the threshold voltage. Experimentally, ID is not zero when VGS ≤
VT. Figure 1 shows a comparison between the ideal characteristic that was derived, and the
experimental results. The drain current, which exists for VGS ≤ VT, is known as the subthreshold
current.

Figure 2 shows the energy-band diagram of an MOS structure with a p-type substrate biased so
that φS < 2 φS. At the same time, the Fermi level is closer to the conduction band than the
valence band, so the semiconductor surface develops the characteristics of a lightly doped n-type
material. We would expect, then, to observe some conduction between the n + sources and drain
contacts through this weakly inverted channel. The condition for φfp < φs < 2φfp is known as
weak inversion.

Figure 3 shows the surface potential along the length of the channel at accumulation, weak
inversion, and threshold for the case when a small drain voltage is applied. The bulk p-substrate
is assumed to be at zero potential. Figure 3b, c shows the accumulation and weak inversion
cases. There is a potential barrier between the n+ source and channel region which the electrons
must overcome in order to generate a channel current. A comparison of these barriers with those
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Figure. 1
Figure. 2

Figure. 3
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in pn junctions would suggest that the channel current is an exponential function of VGS. In the
inversion mode, shown in Figure 3d, the barrier is so small that we lose the exponential
dependence, since the junction is more like an ohmic contact. The actual derivation of the
subthreshold current is beyond the scope of this syllabus. We can write that

(1)

If VDS is larger than a few (kT/e) volts, then the subthreshold current is independent of VDS.

Figure 4 shows the exponential behavior of the subthreshold current for several body-to-source
voltages. Also shown on the curves are the threshold voltage values. Ideally, a change in gate
voltage on approximately 60 mV produces an order of magnitude change in the subthreshold
current. A detailed analysis of the subthreshold condition shows that the slope of the ID versus
VDS curve is a function of the semiconductor doping and is also a function of the interface state
density. The measurement of the slope of these curves has been used to experimentally
determine the oxide–semiconductor interface state density.

If a MOSFET is biased at or even slightly below the threshold voltage, the drain current is not
zero. The subthreshold current may add significantly to power dissipation in a large-scale
integrated circuit in which hundreds or thousands of MOSFETs are used. The circuit design must
include the subthreshold current or ensure that the MOSFET is biased sufficiently below the
threshold voltage in the “off ” state.

Figure. 4
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2. Channel Length Modulation

(2)

Figure. 5

(3)

(4)

(5)

(6)

(7)
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Figure. 6

(8)

(9)

(10)

(11)
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Figure. 7

(12)

(13, a)

(13, b)
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PE-EC-505A –L15: Non Ideal Effects in MOSFETs: Part-II

3. Mobility Variation
In the derivation of the ideal I–V relationship, we explicitly assumed that the mobility was a
constant. However, this assumption must be modified for two reasons. The first effect to be
considered is the variation in mobility with gate voltage. The second reason for a mobility variation
is that the effective carrier mobility decreases as the carrier approaches the velocity saturation limit.
This effect is discussed in the next section.

The inversion layer charge is induced by a vertical electric field, which is shown in Figure 1 for an
n-channel device. A positive gate voltage produces a force on the electrons in the inversion layer
toward the surface. As the electrons travel through the channel toward the drain, they are attracted
to the surface, but then are repelled by localized coulombic forces. This effect, schematically shown
in Figure 2, is called surface scattering. The surface scattering effect reduces mobility. If there is a
positive fixed oxide charge near the oxide-semiconductor interface, the mobility will be further
reduced due to the additional coulomb interaction.

Figure. 1 Figure. 2
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(1)

(1)

(2)

Figure. 3

The effective inversion charge mobility is a strong function of temperature because of lattice
scattering. As the temperature is reduced, the mobility increases.

The effective mobility is a function of gate voltage through the inversion charge density in
Equation (1). As the gate voltage increases, the carrier mobility decreases even further.

4. Velocity Saturation
In the analysis of the long-channel MOSFET, we assume the mobility to be constant, which means
that the drift velocity increases without limit as the electric field increases. In this ideal case, the
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carrier velocity increases until the ideal current is attained. However, we have seen that the carrier
velocity saturates with increasing electric field. Velocity saturation will become more prominent in
shorter-channel devices since the corresponding horizontal electric field is generally larger.

(3)

(4)

(5)

(4)

(6)

(7)
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Figure. 4

5. Ballistic Transport
Scattering events in a semiconductor limit the velocity of carriers to an average drift
velocity. The average drift velocity is a function of the mean time between collisions or the mean
distance between scattering events. In the long-channel device, the channel length L is much longer
than the mean distance between collisions l, so that an average carrier drift velocity exists. As the
MOSFET channel length is reduced, the mean distance between collisions l may become
comparable to L so that the previous analysis may not be valid. If the channel length is further
reduced so that L < l, then a large fraction of carriers could travel from the source to the drain
without experiencing a scattering event. This motion of carriers is called ballistic transport.

Ballistic transport means that carriers travel faster than the average drift velocity or the saturation
velocity, and this effect can lead to very fast devices. Ballistic transport occurs in submicron (L < 1
µm) devices. As the MOSFET technology continues to shrink the channel length toward the 0.1 µm
value, the ballistic transport phenomenon will become more important.
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PE-EC-505A –L16: CMOS Scaling: Constant Field

Scaling, Constant Voltage Scaling

Pre-requisite (Recapitulation): MOS-Characteristics

Introduction to MOSFET Scaling

The design of high-density chips in MOS VLSI (Very Large Scale Integration) technology
requires that the packing density of MOSFETs used in the circuits is as high as possible and,
consequently, that the sizes of the transistors are as small as possible. The reduction of the size,
i.e., the dimensions of MOSFETs, is commonly referred to as scaling.

As we know from our previous knowledge of MOSFETs, the frequency response of MOSFETs
increases as the channel length decreases. The driving force in CMOS technology evolution in
the last couple of decades has been reduced channel lengths. Channel lengths of 0.13 µm or less
are now the norm. One question that must be considered is what other device parameters must be
scaled as the channel length is scaled down.

Scaling of MOS transistors is concerned with systematic reduction of overall dimensions of the
devices as allowed by the available technology, while preserving the geometric ratios found in
the larger devices. The proportional scaling of all devices in a circuit would certainly result in a
reduction of the total silicon area occupied by the circuit, thereby increasing the overall
functional density of the chip. To describe device scaling, we introduce a constant scaling factor
S >1. All horizontal and vertical dimensions of the large-size transistor are then divided by this
scaling factor to obtain the scaled device. The extent of scaling that is achievable is obviously
determined by the fabrication technology and more specifically, by the minimum feature size. It
is seen that a new generation of manufacturing technology replaces the previous one about every
two or three years, and the down-scaling factor S of the minimum feature size from one
generation to the next is about 1.2 to 1.5.

S = 1/k, So k <1 as S>1. Typically, k≈0.7 per generation of a given technology.

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There are two main scaling techniques defined as follows:

1. Constant field scaling or full scaling

2. Constant voltage scaling

Constant Field scaling (Full Scaling)

This scaling option attempts to preserve the magnitude of internal electric fields (both horizontal
and vertical) in the MOSFET, while the dimensions are scaled down by a factor of S. To achieve
this goal, all potentials must be scaled down proportionally, by the same scaling factor. Note
that, this potential scaling also affects the threshold voltage. Finally, the Poisson equation
describing the relationship between charge densities and electric fields dictates that the charge
densities must be increased by a factor of S in order to maintain the field conditions.

In the constant field scaling, the dimensions of the MOSFET and the terminal voltages are
scaled with the same scale factor so that the electric field remains constant. To ensure that
the reliability of the scaled device is not compromised, the electric fields in the scaled device
must not increase.
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S = 1/k, So k <1 as S>1. Typically, k≈0.7 per generation of a given technology.

Fig:1

(1)

(2)
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Constant Voltage Scaling

While the full scaling strategy dictates that the power supply voltage and all terminal voltages
are to be scaled down proportionally with the device dimensions, the scaling of voltages may not
be very practical in many cases. In particular, the peripheral and interface circuitry may require
certain voltage levels for all input and output voltages, which in turn would necessitate multiple
power supply voltages and complicated level shifter arrangements. For these reasons, constant-
voltage scaling is usually preferred over full scaling. In constant-voltage scaling, all dimensions
of the MOSFET are reduced by a factor of S, as in full scaling. The power supply voltage and the
terminal voltages, on the other hand, remain unchanged. The doping densities must be increased
by a factor of s2 in order to preserve the charge-field relations

In the constant voltage scaling, the dimensions of the MOSFET are scaled but the terminal
voltages are kept constant. This type of scaling increases the electric field.
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Advantages and Disadvantages of MOSFET Scaling

Scaling of MOSFET has many advantages and disadvantages. Following are the

Advantages of Scaling:

i) More transistors can be integrated per chip; means more capability

ii) Improvement in speed
iii) Due to decrease in channel length L, transit time drastically reduces
iv) Increase in current
v) Hence improved parasitic capacitance charging time
vi) Improved ‘throughput’ of the chip

Disadvantages of Scaling:

i) Short channel effects

ii) Narrow channel effects
iii) Complex process technology
iv) Parasitic effects dominate over transistor effects

Summary: To summarize, constant-voltage scaling may be preferred over full (constant-field)

scaling in many practical cases because of the external voltage-level constraints. It must be
recognized, however, that constant-voltage scaling increases the drain current density and the
power density by a factor of S3. This large increase in current and power densities may
eventually cause serious reliability problems for the scaled transistor, such as electro migration,
hot-carrier degradation, oxide breakdown, and electrical over-stress.
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PE-EC-505A –L17: First Approximations, Generalized

Scaling

Threshold Voltage—First Approximation

In constant-field scaling, the device voltages are reduced by the scaling factor k. It would seem
appropriate that the threshold voltage should also be scaled by the same factor. The threshold
voltage, for a uniformly doped substrate, can be written as

(1)

The first two terms in Equation (1) are functions of material parameters that do not scale and are
only very slight functions of doping concentration. The last term is approximately proportional to
√k , so the threshold voltage does not scale directly with the scaling factor k. The effect of short
channels on the threshold voltage will be discussed further.

Generalized Scaling

In constant-field scaling, the applied voltages are scaled with the same scaling factor k as the
device dimensions. However, in actual technology evolution, voltages have not been reduced
with the same scaling factor. There has been reluctance, for example, to change standardized
power supply levels that have been used in circuits earlier. In addition, other factors that do not
scale, such as threshold voltage and sub-threshold currents, have made the reduction in applied
voltages less desirable. As a consequence, electric fields in MOS devices have tended to increase
as device dimensions shrinked.

Consequences of increased electric fields are reduced reliability and increased power density. As
the power density increases, the device temperature may increase. Increased temperature may
affect the device reliability. As the oxide thickness is reduced and the electric field is increased,
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gate oxides are closer to breakdown and oxide integrity may be more difficult to maintain. In
addition, direct tunneling of carriers through the oxide may be more likely to occur. Increased
electric fields may also increase the chances of hot-electron effects, which are discussed later in
this chapter. Reducing device dimensions, then, can introduce challenging problems that must be
solved.

Problem:
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PE-EC-505A –L18: Threshold Voltage Modifications:

Short-Channel Effects
Threshold Voltage Modifications
We have derived the ideal MOSFET relations previously, including expressions for threshold
voltage and for the current–voltage characteristics. We now consider some of the non-ideal
effects including channel length modulation. Additional effects on threshold voltage occur as the
devices shrink in size. A reduction in channel length increases the transconductance and
frequency response of the MOSFET, and a reduction in channel width increases the packing
density in an integrated circuit. A reduction in either or both the channel length and channel
width can affect the threshold voltage.

Short-Channel Effects
For the ideal MOSFET, we have derived the threshold voltage using the concept of charge
neutrality in which the sum of charges in the metal oxide inversion layer and semiconductor
space charge region is zero. We assumed that the gate area was the same as the active area in the
semiconductor. Using this assumption, we have considered only equivalent surface charge
densities and neglected any effects on threshold voltage that may occur due to source and drain
space charge regions that extend into the active channel region.

Figure. 1
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Figure 1.a shows the cross section of a long n-channel MOSFET at fl at band, with zero source
and drain voltage applied. The space charge regions at the source and drain extend into the
channel region but occupy only a small fraction of the entire channel region. The gate voltage,
then, will control essentially all of the space charge induced in the channel region at inversion as
shown in Figure 1.b.

As the channel length decreases, the fraction of charge in the channel region controlled by the
gate decreases. This effect can be seen in Figure 2 for the flat-band condition. As the drain
voltage increases, the reverse-biased space charge region at the drain extends further into the
channel area and the gate controls even less bulk charge. The amount of charge in the channel
region, Q/SD (max), controlled by the gate, affects the threshold voltage and can be seen from
Equation (1)

(1)

Figure: 3

(2)
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Figure. 3
Figure. 2

(3)

(4)

(5)

(5)

(6)

(7)
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Figure: 4
Before

Figure. 5
Figure. 4

Figure: 5
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PE-EC-505A –L19: Threshold Voltage Modifications:

Narrow-Channel Effects

Narrow-Channel Effects

Figure. 1

Figure. 1
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(1)

(2)

(3)

(4)

(5)
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Figure. 2

Figure. 3 a, b

Figure. 2

Figure. 3
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PE-EC-505A –L20: Additional Electrical Characteristics
ADDITIONAL ELECTRICALCHARACTERISTICS:

There is a tremendous volume of information on MOSFETs that cannot be included in an

introductory text on semiconductor physics and devices. However, two additional topics
should be included here: breakdown voltage and threshold adjustment by ion implantation.

Breakdown Voltage:

Several voltage breakdown mechanisms in the MOSFET must be considered, including

voltage breakdown across the oxide as well as the various voltage breakdown mechanisms in
the semiconductor junctions. Oxide Breakdown We have assumed that the oxide is a perfect
insulator. However, if the electric field in the oxide becomes large enough, breakdown can
occur, which can lead to a catastrophic failure. In silicon dioxide, the electric field at
breakdown is on the order of 6 X106 V /cm. This breakdown field is larger than that in
silicon, but the gate oxides are also quite thin. A gate voltage of approximately 30 V would
produce breakdown in an oxide with a thickness of 500 Å. However, a safety margin of a
factor of 3 is common, so that the maximum safe gate voltage with tox = 500 Å would be 10
V. A safety margin is necessary since there may be defects in the oxide that lower the
breakdown field. Oxide breakdown is normally not a serious problem except in power
devices and ultrathin oxide devices. Other oxide degradation problems are discussed later in
this chapter.

Avalanche Breakdown

Avalanche breakdown may occur by impact ionization in the space charge region near the
drain terminal. We have considered avalanche breakdown in pn junctions. In an ideal planar
one-sided pn junction, breakdown is a function primarily of the doping concentration in the
low-doped region of the junction. For the MOSFET, the low-doped region corresponds to the
semiconductor substrate. If a p-type substrate doping is Na =3 X 1016 cm-3, for example, the
pn junction breakdown voltage would be approximately 25 V for a planar junction. However,
the n+ drain contact may be a fairly shallow diffused region with a large curvature. The
electric fi eld in the depletion region tends to be concentrated at the curvature, which lowers
the breakdown voltage. This curvature effect is shown in Figure 1.

Fig1. Curvature effect on the electric field in the drain junction

Fig2. Current–voltage characteristic showing the snapback breakdown effect.

Near Avalanche and Snapback Breakdown

Another breakdown mechanism results in the S-shaped reakdown curve shown in Figure 2.
This breakdown process is due to second order effects and can be explained with the aid of
Figure 3. The n-channel enhancement-mode MOSFET geometry in Figure 3a shows the n-
type source and drain contacts along with the p-type substrate. The source and body are at
ground potential. The n(source)-p(substrate)-n(drain) structure also forms a parasitic bipolar
transistor. The equivalent circuit is shown in Figure 3b. Figure 4a shows the device when
avalanche breakdown is just beginning in the space charge region near the drain. We tend to
think of the avalanche breakdown suddenly occurring at a particular voltage. However,
avalanche breakdown is a gradual process that starts at low current levels and for electric
fields somewhat below the breakdown field. The electrons generated by the avalanche
process flow into the drain and contribute to the drain current. The avalanche-generated holes
generally flow through the substrate to the body terminal. Since the substrate has a nonzero
resistance, a voltage drop is produced as shown. This potential difference drives the source-
to-substrate pn junction into forward bias near the source terminal. The source is heavily
doped n-type; thus, a large number of electrons can be injected from the source contact into
the substrate under forward bias. This process becomes

Fig3. (a) Cross section of the n-channel MOSFET. (b) Equivalent circuit including the parasitic bipolar transistor.
Fig4. (a) Substrate current–induced voltage drop caused by avalanche multiplication at the drain. (b) Currents in the
parasitic bipolar transistor.

severe as the voltage drop in the substrate approaches 0.6 to 0.7 V. A fraction of the injected
electrons diffuses across the parasitic base region into the reverse-biased drain space charge
region where they also add to the rain current. The avalanche breakdown process is a function
of not only the electric field but the number of carriers involved. The rate of avalanche
breakdown increases as the number of carriers in the drain space charge region increases. We
now have a regenerative or positive feedback mechanism. Avalanche breakdown near the
drain terminal produces the substrate current, which produces the forward-biased source-
substrate pn junction voltage. The forward-biased junction injects carriers that can diffuse
back to the drain and increase the avalanche process. The positive feedback produces an
unstable system. The snapback or negative resistance portion of the curve shown in Figure 2
can now be explained by using the parasitic bipolar transistor. The potential of the base of the
bipolar transistor near the emitter (source) is almost floating, since this voltage is determined
primarily by the avalanche-generated substrate current rather than an externally applied
voltage. For the open-base bipolar transistor shown in Figure 4, we can write

----- (1)
where α is the common base current gain and ICB0 is the base-collector leakage current. For
an open base, IC = IE, so Equation (1) becomes

- ---- (2)
At breakdown, the current in the B–C junction is multiplied by the multiplication factor M, so
we have

----- (3)
Solving for IC we obtain

------- (4)
Breakdown is defi ned as the condition that produces IC → ∞. For a single reverse biased pn

junction, M → ∞ at breakdown. However, from Equation (4), breakdown is now defined to

be the condition when _M → 1 or, for the open-base condition, breakdown occurs when M →
1 / α, which is a much lower multiplication factor than for the simple pn junction. An
empirical relation for the multiplication factor is usually written as

-------- (5)
where m is an empirical constant in the range of 3 to 6 and VBD is the junction breakdown
voltage. The common base current gain factor α is a strong function of collector current for
small values of collector current. At low currents, the recombination current in the B-E
junction is a significant fraction of the total current so that the common base current gain is
small. As the collector current increases, the value of α increases. As avalanche breakdown
begins and IC is small, particular values of M and VCE are required to produce the condition of
α M = 1. As the collector current increases, α increases; therefore, smaller values of M and
VCE are required to produce the avalanche breakdown condition. The snapback, or negative
resistance, breakdown characteristic is then produced. Only a fraction of the injected
electrons from the forward-biased source-substrate junction are collected by the drain
terminal. A more exact calculation of the snapback characteristic would necessarily involve
taking into account this fraction; thus, the simple model would need to be modified.
However, the above discussion qualitatively describes the snapback effect. The snapback
effect can be minimized by using a heavily doped substrate that will prevent any significant
voltage drop from being developed. A thin epitaxial p-type layer with the proper doping
concentration to produce the required threshold voltage can be grown on a heavily doped
substrate.