Scribd
Upload
37 views2 pages

Problem 2 (15 Points)

The document describes a homework assignment on cache design with 6 problems. Problem 1 asks to calculate bits required for a direct mapped cache. Problem 2 gives details on a direct mapped cache and main memory. Problem 3 provides cache hit rates and sizes to calculate memory access times. Problem 4 asks to choose the best L1 and L2 cache design. Problem 5 provides memory addresses to identify hits and misses. Problem 6 gives block locations for sample addresses.

Uploaded by

Dom McK
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
37 views2 pages

Problem 2 (15 Points)

The document describes a homework assignment on cache design with 6 problems. Problem 1 asks to calculate bits required for a direct mapped cache. Problem 2 gives details on a direct mapped cache and main memory. Problem 3 provides cache hit rates and sizes to calculate memory access times. Problem 4 asks to choose the best L1 and L2 cache design. Problem 5 provides memory addresses to identify hits and misses. Problem 6 gives block locations for sample addresses.

Uploaded by

Dom McK
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

CECS-341: Computer Architecture and Organization

Semester: Spring 2023 (CSULB)


Homework 4 – Cache Design
Assigned: Dec 1, 2023
Due: Dec 7, 2023, 11PM

Submit your HW in Canvas. Your submission should be clearly and neatly to be considered grading.

Problem 1 (10 points):


Consider a direct mapped cache with a total data capacity of 2^B bytes, and a block size of 2^b
bytes. Assume that the input byte address is A bits. Calculate the total number of bits required to fabricate
this cache. You should consider both valid and dirty bit.

Problem 2 (15 points):

A system has a main memory with 16 MB of addressable locations and a 32 KB of direct-mapped


cache with 8 bytes per block. The minimum addressable unit is 1 byte.

a) How many blocks are in cache?


b) What is the address breakdown for main memory?

Problem 3 (15 points):

Assume that main memory accesses take 70 ns and that 36% of all instructions access data memory. The
following table shows data for L1 caches attached to each of two processors, P1 and P2.

Processor L1 Size L1 Miss Rate L1 Hit Time


P1 2 KB 8% 0.66 ns
P2 4 KB 6% 0.90 ns

a) Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective
clock rates?
b) What is the Average Memory Access Time (AMAT) for P1 and P2 (in cycles)?

Problem 4 (20 points):

You are designing the memory hierarchy for a new processor. The access latency of main memory is 200
cycles. You have the following choices for the L2 design:
• 2MB, 16-way set-associative. Hit time = 30 cycles. %miss = 1%
• 1MB, 8-way set associative. Hit time = 20 cycles. %miss = 5%
• 512KB, 4-way set associative. Hit time = 15 cycles. %miss = 10%

And the following choices for L1 design:


• 64KB, 8-way set associative. Hit time = 2 cycles. %miss = 4%
• 32KB, 4-way set associative. Hit Time = 1 cycle. %miss = 5%

1
CECS-341: Computer Architecture and Organization
Semester: Spring 2023 (CSULB)
Homework 4 – Cache Design
Assigned: Dec 1, 2023
Due: Dec 7, 2023, 11PM

Which cache design would you choose and why?

Problem 5 (20 points):

Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of
64-bits memory address references given as word addresses.
0x03, 0xb4, 0x2b, 0x02, 0xbf, 0x58, 0xbe, 0x0e, 0xb5, 0x2c, 0xba, 0xfd
For each of these references identify the binary word address, the tag, and the index given a direct
mapped cache with 16 one-word blocks. Also list whether each reference is a hit or a miss, assuming the
cache is initially empty.

Problem 6 (20 points):

A computer with 32-bit address size:

• Each block stores 16 words. A direct-mapped cache has 256 blocks. In which block of the cache
would we look for each of the following addresses?

a. 1A2BC012

b. FFFF00FF

c. 12345678

d. C109D532

You might also like