CHAPTER FOUR

CENTRAL PROCESSING UNIT

4.1 An Overview of the CPU

The Central Processing Unit (CPU) is the heart of a computer system. The CPU along with the
memory and the I/O sub-systems develops a powerful computer system.

Companies such as AMD, IBM, Intel, Motorola, SGI, and Sun manufacture CPUs that are used in
various kinds of computers such as desktops, mainframes, and supercomputers. A CPU comprises
thin layers of thousands of transistors. Transistors are microscopic bits of material that block
electricity at one voltage (non-conductor) and allow electricity to pass through them at different
voltage (conductor). These tiny bits of materials are the semiconductors that take two electrical
inputs and generate a different output when one or both inputs are switched on. As CPUs are small,
they are also referred to as microprocessors.

Did u know? CPU is an old term that was used for processor or multiprocessor.

Modern CPUs are called as integrated chips. It is so called because several types of components
such as execution core, Arithmetic Logic Unit (ALU), registers, instruction memory, cache
memory, and the input/output controller are integrated into a single piece of silicon.

Central Processing Unit (CPU) is the most important unit in a computer system. It is the component
which controls all internal and external devices as well as performs arithmetic and logic operations

to execute the set of instructions stored in the computer’s memory. A CPU comprises three major
components. They are:

 Register Set
 ALU
 Control Unit (CU)

Register Set

The register set differs from one system to another. The register set comprises many registers
which include general purpose registers and special purpose registers. The general purpose
registers do not perform any specific function. They store the temporary data that is required by a
program. The special purpose registers perform specific functions for the CPU.

Example: Instruction Register (IR) is a special purpose register that stores the instruction

that is currently being executed.

ALU

The ALU performs all the arithmetic, logical, and shift operations by providing necessary circuitry
that supports these computations.

Control Unit

The control unit fetches the instructions from the main memory, decodes the instructions, and then
executes it. The control unit is discussed in detail in the units ahead.

As shown in figure 4.1, the CPU consists of the register set, ALU, and CU.

The CPU interacts with the main memory and input/output devices. The CPU reads and writes
data to and from the memory system and transfers data to and from the I/O devices.
A simple execution cycle in the CPU can be described as below:

1. The CPU fetches the instruction to be executed from the main memory and stores it in the

Instruction Register (IR).

2. The instruction is decoded.

3. The operands are fetched from the memory system and stored in the CPU registers.

4. The instructions are then executed.

5. The results are transferred from the CPU registers to the memory system.

Notes Operand is the part of a computer instruction that is manipulated and operated. In the
addition of 5 + x, ‘5’ and ‘x’ are operands and ‘+’ is the operator.

If there are more instructions to be executed, the execution cycle repeats. Any pending interrupts
are also checked during the execution cycle.

Example: The interrupts such as I/O device request, arithmetic overflow, or pages is checked

during the execution cycle.

4.2 General Register Organization

A group of flip-flops form a register. A register is a special high speed storage area in the CPU.
They comprise combinational circuits that perform data processing. The data is always represented

in a register before processing. The registers speed up the execution of programs. Registers
perform two important functions in the CPU operation. They are:

1. Providing a temporary storage area for data. This helps the currently executing programs to

have a quick access to the data, if needed.

2. Storing the status of the CPU as well as information about the currently executing program.

Example: Address of the next program instruction, signals received from the external devices

and error messages, and such other information is stored in the registers.
We know that referring to memory locations is considered difficult and time consuming. Hence,
storing the pointers, return addresses, temporary results, and program counters into the register is
more efficient than the memory. The number of registers varies from one computer system to
another.

If a CPU contains a number of registers, then a common bus is used to connect these registers. A
Notes

general organization of seven CPU registers is shown in figure 4.2.

As observed in figure 4.2, the CPU bus system is operated by the control unit. The control unit
directs the information flow through the ALU by selecting the function of the ALU as well as
components of the system.

Consider R1 R2 + R3, the following are the functions performed within the CPU:

MUX A Selector (SELA): It is used to place R2 into bus A MUX B Selector (SELB): It is used to
place R3 into bus B
ALU Operation Selector (OPR): It selects the arithmetic addition (ADD) Decoder Destination
Selector (SELD): It transfers the result into R1.

The multiplexers of 3-state gates are implemented with the buses. The state of 14 binary selection
inputs specifies the control word. The 14-bit control word specifies a micro-operation.

The encoding of register selection fields is specified in table 4.1

3-state gates are the types of logic gates having three states of output: high (H), low (L) and high-
impedance (Z).

Various micro-operations are performed by the ALU. Some of the operations performed by the
ALU are listed in table 4.2

Some of the ALU micro-operations are shown in the table 4.3

Types of Registers

There are many different types of register available in the market. Some of them are:

1. Data Register: It is used to store data.

2. Accumulator Register: It is considered as a special data register.

3. Address Register: It holds the memory address.

4. Index Register: It holds the index of the memory address.

5. Condition Register: It determines whether the instruction should be executed or not.

6. General Purpose Register: It stores data and addresses.

7. Special Purpose Register: It stores the status of the programs.

8. Floating Point Register: It is a kind of data register that stores the floating point numbers.

9. Constant Register: It stores read-only values.

General purpose registers are also called as processor registers. These processor registers provide
the fastest means to access data.

4.3 Stack Organization

Stack, also called as Last In First Out (LIFO) list, is the most useful feature in the CPU. It stores
information such that the item stored last is retrieved first. Stack is a memory unit with an address
register. This register holds the address for the stack, which is called as Stack Pointer (SP). The
stack pointer always holds the address of the item that is placed at the top of the stack.

You can insert an item into or delete an item from the stack. The insertion operation is called as
push operation and the deletion operation is called as pop operation. In a computer stack, these
operations are simulated by incrementing or decrementing the SP register.

4.3.1 Register Stack

Stack can be organized as a collection of memory words or registers. Consider a 64-word register
stack organized as shown in figure 7.3. The stack pointer register contains a binary number, which
is the address of the item present at the top of the stack. The three items A, B, and C are placed in
the stack. The item C is at the top of the stack and the stack pointer holds the address of C that is,
3. The top item is popped from the stack by reading memory word at address 3 and decrementing
the stack pointer by 1. Now, B is at the top of the stack and the SP holds the address of B that is,
2. To insert a new word, the stack is pushed by incrementing the stack pointer by 1 and inserting
a word in that incremented location

Here, the stack pointer contains 6 bits, since 26 = 64, and the SP cannot exceed 63 (111111 in
binary) because if 63 is incremented by 1, then the result is 0(111111 + 1= 1000000). SP holds
only the six least significant bits. If 000000 is decremented by 1 then the result is 111111. Thus,
when the stack is full, the one-bit register ‘FULL’ is set to 1. If the stack is empty, then the one-
bit register ‘EMTY’ is set to 1. The data register DR holds the binary data which is written into or
read out of the stack.

First the SP is set to 0, EMTY is set to 1, and FULL is set to 0. Now, as the stack is not full (FULL
= 0), a new item is inserted using the push operation. The push operation is performed as below:

SP SP + 1, stack pointer is incremented

K[SP] DR, place an item on the top of the stack

If (SP = 0) then (FULL 1), check if stack is full

EMTY 0, if stack is full, then mark the stack as not empty

The stack pointer is incremented by 1 and the address of the next higher word is stored in the SP.
The word from DR is inserted into the stack using the memory write operation. As per figure 5.3,
the first item is stored at address 1 and the last item is stored at address 0. If the stack pointer is at
0, then the stack is full and ‘FULL’ is set to 1. This is the condition when the SP was in location
63 and after incrementing SP, the last item is stored at address 0. Once an item is stored at address
0,

there are no emptier registers in the stack. The stack is full and the ‘EMTY’ is set to 0. You can
perform pop operation (deletion) only if the stack is not empty. To delete an item from the stack,
the following micro-operations are performed.

DR K[SP], an item is read from the top of stack

SP SP – 1, stack pointer is decremented

If (SP = 0) then (EMTY 1), check if stack is empty

FULL 0, if stack empty, then mark the stack empty

The top item from the stack is read and sent to DR and then the stack pointer is decremented. If
the stack pointer reaches 0, then the stack is empty and ‘EMTY’ is set to 1. This is the condition
when the item in location 1 is read out and the SP is decremented by 1.

If stack is pushed when FULL = 1 or popped when EMTY = 1, you get an erroneous

result.

4.3.2 Memory Stack

Stack can be implemented in the CPU by allotting a portion of the computer memory to a stack
operation and using a processor register as a stack pointer. In this case, it is implemented in a
random access memory attached to the CPU.

In figure 4.4, a portion of the computer memory is divided into three segments: program, data and
stack. The address of the next instruction in the program is stored in the pointer Program Counter
(PC). The Address Register (AR) points to an array of the data. SP always holds the address of the
item present at the top of the stack. The three registers that are connected to the common bus are
PC, AR, and SP. PC is used to read the instruction during fetch phase. An operand is read during
execute phase using address register. An item is pushed into or popped from the stack using stack
pointer. Figure 4.4 depicts the memory stack.
In figure 4.4, the SP points to an initial value ‘2001’. Here, the stack grows with decreasing
addresses. The first item is stored at address 2000, the next item is stored at address 1999 and the
last item is stored at address 1000.

As we already know, data register is used to read an item into or from the stack. You use push
operation to insert a new item into the stack.

SP SP -1

K[SP] DR

To insert another item into the stack, the stack pointer is decremented by 1 so that it points at the
address of the next location/word. A word from DR is inserted into the top of the stack using
memory write operation.

To delete an item from the stack, you need to use the pop operation:

DR K[SP]

SP SP + 1

The top item is read into the DR and then the stack pointer is decremented to point to the next item
in the stack.

Here, two processor registers are used to check the stack limits. One processor register holds the
upper limit (1000) and the other holds the lower limit (2001). During push operation, the SP is
compared with the upper limit to check if the stack is full. During pop operation, the SP is
compared with the lower limit to check if the stack is empty.

An item in the stack is pushed or popped using two micro-operations. They are:

1. Accessing the memory through SP

2. Updating SP

A stack pointer is initially loaded with the bottom address of the stack in memory. Thereafter, SP
is automatically incremented or decremented depending on the operation performed (push or pop).
As the address is automatically updated in the stack pointer, the CPU can refer to the memory
stack without specifying the address.

4.4 Data Transfer and Manipulation

Computer systems consist of a set of instructions that help the users to easily carry out their
computational tasks. The instruction set differs from one computer system to another. The
operations are represented by binary codes and the binary code assignment in the operation field
of the instruction can be different in different computers. However, the actual operations in the
instruction set are not very different from one computer system to another. The symbolic names
of the instruction (assembly language notation) may also differ from one computer to another. An
instruction usually contains opcode, addressing field, and operand field. There are different types
of opcodes and based on the type of opcode, the instructions can be classified as follows:

1. Data Transfer Instructions

2. Data Manipulation Instructions

3. Program Control Instructions

Data transfer instructions transfer data from one location to another without causing any change
in the content present in the binary form. Data manipulation instructions perform arithmetic, logic,
and shift operations. Program control instructions provide decision making abilities and are able
to change the execution sequence. The program control instructions are explained in the next
section.
4.5 Data Transfer Instructions
Data transfer instructions move the data between memory and processor registers, processor
registers and I/O devices, and from one processor register to another. There are eight commonly
used data transfer instructions. Each instruction is represented by a mnemonic symbol. Table 4.1
shows the eight data transfer instructions and their respective mnemonic symbols.

The instructions can be described as follows:

1. Load: The load instruction is used to transfer data from the memory to a processor register,

which is usually an accumulator.

2. Store: The store instruction transfers data from processor registers to memory.

3. Move: The move instruction transfers data from processor register to memory or memory to

processor register or between processor registers itself.

4. Exchange: The exchange instruction swaps information either between two registers or
between

a register and a memory word.

5. Input: The input instruction transfers data between processor register and input terminal.

6. Output: The output instruction transfers data between processor register and output terminal.

7. Push and Pop: The push and pop instructions transfer data between a processor register and
memory stack.

All these instructions are associated with a variety of addressing modes. Some assembly
language instructions use different mnemonic symbols just to differentiate between the different
addressing modes.
Example: The mnemonic symbols for load immediate is LDI
Thus, it is necessary to be familiar with various addressing modes and different types of
instructions to write efficient assembly language programs for a computer.

4.6 Data Manipulation Instructions

Data manipulation instructions have computational capabilities. They perform arithmetic, logic,
and shift operations on data. There are three basic types of data manipulation instructions:

1. Arithmetic Instructions

2. Logical and Bit Manipulation Instructions

3. Shift Instructions

During execution of the instruction, each instruction goes through the fetch phase, where it reads
the binary code of the instruction from the memory. According to the rules of the instruction
addressing mode, the operands are brought in processor registers. Finally, the instruction in the
processor is executed.

Arithmetic Instructions
Arithmetic operations include addition, subtraction, multiplication and division. Some computers
provide instructions only for addition and subtraction operations, and generate multiplication and
division operations from these two operations. Each instruction is represented by a mnemonic
symbol. Table 4.2 illustrates some of the arithmetic instructions and their respective mnemonic
symbols.

The description of these instructions is as follows:

1. Increment: The increment instruction adds 1 to the value stored in register or memory word.
2. Decrement: The decrement instruction subtracts 1 from the contents stored in register or
memory
word.
3. Arithmetic Instructions: The arithmetic instructions are available for different types of data
such as floating point, binary, single precision, or double precision data.
During execution of arithmetic instructions, the processor status flags or conditional codes are set
to designate the outcome of the operation.

Logical and Bit Manipulation Instructions Notes

Logical instructions carry out binary operations on the bits stored in the registers. In logical
operations, each bit of the operand is treated as a Boolean variable. Logical instructions can
change bit value, clear a group of bits, or can even insert new bit value into operands that are
stored in registers or memory words. Each logical instruction is represented by mnemonic
symbols.

Table 4.3 illustrates some of the logical instructions and their respective mnemonic symbols.

The clear instruction replaces the specific operand by 0’s. The complement instruction inverts all
the bits of the operand and produces 1’s complement. The AND, OR, and XOR instructions
perform logical operations on each bit or group of bits of the operand.
Logical instructions can also manipulate individual bits or group of bits. The bit manipulation
operation can clear a bit to 0, can set a bit to 1, or can complement a bit.
The AND instruction can clear a bit or group of bits of an operand. For Boolean variable a, the
relationship ‘ab0 = 0’ and ‘ab1 = a’ indicates that the binary variable when ANDed with 0 changes
the value to 0. However, the variable when ANDed with 1 does not change the value. Thus, bits
of an operand can be cleared by ANDing the operand with another operand that has to clear all 0
bits in its position. It is also known as mask because it masks 0s in selected bit positions of an
operand.
The OR instruction can set a bit or group of bits of an operand. For Boolean variable a, the
relationship ‘a + 1 =1’ and ‘a + 0 = a’ indicates that the binary variable when ORed with 1, changes
the value to 1. However, the variable when ORed with 0 does not change the value. Thus, OR
instruction is used to set the bits to 1 by ORing the bits of an operand with another operand that
has 1s in its bit positions.
The XOR instruction can complement bits of an operand. For Boolean variable a, the relationship
‘a + 1 = a’ and ‘a + 0 = a’ indicates that the binary variable is complemented when XORed with
1. However, the variable does not change value when XORed with 0.
The carry bits can be cleared, set, or complemented with appropriate instructions. The bit
manipulation instructions can also enable or disable the interrupt facility, which is controlled by
the flip-flops.
Shift Instructions
Shift instruction helps to shift the bits of an operand to the right or to the left. The direction of shift
is based on specific instructions. The operand is first loaded into the accumulator and then the shift
operation is performed bit by bit.

4.7 Program Control

Instructions of the computer are always stored in consecutive memory locations. These instructions
are fetched from successive memory locations for processing and executing. When an instruction
is fetched from the memory, the program counter is incremented by 1 so that it points to the address
of the next consecutive instruction in the memory. Once a data transfer and data manipulation
instruction is executed, the program control along with the program counter, which holds the
address of the next instruction to be fetched, is returned to the fetch cycle.

Data transfer and manipulation instructions specify the conditions for data processing operations,
whereas the program control instructions specify the conditions that can alter the content of the
program counter. The change in the content of program counter can cause an interrupt/break in the
instruction execution. However, the program control instructions control the flow of program
execution and are capable of branching to different program segments.

Some of the program control instructions are listed in table 4.4.

The branch is a one-address instruction. It is represented as BR ADR, where ADR is a mnemonic
for an address. The branch instruction transfers the value of ADR into the program counter. The
branch and jump instructions are interchangeably used to mean the same. However, sometimes
they denote different addressing modes.

Branch and jump instructions can be conditional or unconditional. The unconditional branch
instruction creates a branch to the specified address without any conditions
Exampl JMP DisplaydiagramThe JMP instruction transfers the flow of
e: execution, without considering the
actual condition of the flags, to the indicated operator. The above instruction makes the control
jump to the part of the code where Displaydiagram is specified.
The conditional branch instructions such as ‘branch if positive’, or ‘branch if zero’ specify the
condition to transfer the flow of execution. When the condition is met, the branch address is loaded
in the program counter.
Figure 4.7 depicts the conditional branch instructions.

Conditional Branch Instruction

The conditional branch instruction checks the conditions for branching using the status bits. Some
of the commonly used conditional branch instructions are shown in table 4.5.
Thus, when the status condition is true, the program control is transferred to the address specified
in the instruction, otherwise the control continues with the instructions that are in the subsequent
locations. The conditional instructions are also associated with the program control instructions
such as jump, call, or return.
The zero status bit checks if the result of the ALU is zero or not. The carry bit checks if the most
significant bit position of the ALU has a carry out. It is also used with rotate instruction to check
whether or not the bit is shifted from the end position of a register into a carry position. The sign
bit indicates the state of the most significant bit of the output from the ALU (S = 0 denotes positive
sign and S = 1 denotes negative sign). The branch if plus and branch if minus is used to check
whether the value of the most significant bit represents a sign or not. The overflow and underflow
instructions are used in conjunction with arithmetic operations performed on signed numbers. The
higher and lower words are used to denote the relations between unsigned numbers, whereas the
greater and lesser words are used to denote the relations between signed numbers.

Example: Consider two numbers M = 11110000 and N = 00010100. When we perform M - N

operation, the result obtained is
1111000
M:
0
 0001010
N:
0
M-N: 11011100
The compare instruction updates the status bits:
C =1: Carry out of the last stage
S = 1: Left most bit is 1
Z = 0: Last two carries are equal to 1
V = 0: Result is not equal to 0
Consider the numeric value, where M = 60 and B =10 (unsigned numbers). Here, M > N and M
N. Therefore, the instructions that will cause branch are BHI, BHE and BNE.
If M = -8 and N = 10, then we have M < N and M N. Therefore, the
instructions that will cause branch are BLT, BLE, and BNE

4.8 RISC and CISC

The design of the instruction set for the processor is considered as an important aspect of computer
architecture. The machine language program is developed based on the instruction set chosen for
that particular computer.

Earlier, the hardware components of the computer were expensive and to minimize this expense,
the programmers started to build simple and small instructions. With the advent of integrated
circuits, the digital hardware became cheaper and the computer instructions started to increase in
number and complexity. Many computers have more than 100 instruction sets. Such computers
with large number of instructions are classified as a Complex Instruction Set Computers (CISC).

In 1980s, computer architects started to design computers with fewer instructions in order to
execute programs at a much faster rate within the CPU. Such computers with less number of
instructions are classified as a Reduced Instruction Set Computer (RISC).

4.8. 1 Complex Instruction Set Computer (CISC)

A Complex Instruction Set Computer (CISC) comprises a complex instruction set. It incorporates
variable length instruction format. Instructions that require register operands may take only two
bytes. However, the instructions that require two memory addresses may take five bytes to include
the complete instruction code. Thus, CISC has variable length encoding of instructions and the
execution of instructions may take varying number of clock cycles. The CISC processor provides
direct manipulation of operands that are in memory.

Example: An ADD instruction will use index addressing to specify one operand in memory

and direct addressing to specify second operand in memory. This instruction would use another
memory location to store the result. Thus, this instruction would use three memory references for
execution.

Many CISC architectures read the inputs and write their outputs in the memory system instead of
a register file. As CISC architecture takes large number of addressing modes, more hardware logic
is required to implement them. This reduces the computation speed.

Basically, the CISC architecture attempts to provide a single machine instruction for the statements
that are written in a high-level language.

4.8.2 Reduced Instruction Set Computer (RISC)

In Reduced Instruction Set Computer (RISC) architecture, the instruction set of the computer is
simplified to reduce the execution time. RISC has a small set of instructions, which generally
include register-to-register operations. Thus, data is stored in processor registers for computations
and results of the computations are transferred to the memory using store instructions. All
operations are performed within the registers of the CPU. In RISC, all instructions have simple
register addressing and hence use less number of addressing modes.
RISC uses relatively a simple instruction format and is easy to decode. Here, the instruction length
can be fixed and aligned on word boundaries. The RISC processors have the ability to execute one
instruction per clock cycle. This is done using pipelining, which involves overlapping the fetch,
decode, and execute phases of two or three instructions.
As RISC takes relatively a large number of registers in the processor unit, it takes less time to
execute its program when compared to CISC.
Example: The Scalable Processor Architecture (SPARC) is an example of RISC architecture.

4.8.2.1 RISC Instruction Set

RISC instruction set includes simpler instructions with hard-wired control, large number of
registers, simpler processor pipeline and increased clock-rate. The RISC processor’s instruction
set is restricted to load and store instructions when there is an interaction between memory and
CPU. All other instructions are executed within registers without any reference to memory.
 Example: Consider an example program for a RISC-type CPU, which include
load and store
instructions that have one memory and one register address, and arithmetic
instructions that are specified by processor registers. The below program
evaluates X = (P + Q)*(R + S)
LOAD R1 P R1 M[P]
LOAD R2 Q R2 M[Q]
LOAD R3 R R3 M[R]
LOAD R4 S R4 M[S]
ADD R1, R1, R2 R1 R1 + R2
ADD R3, R3, R4 R3 R3 + R4
MUL R1, R1, R3 R1 R1 + R3
STORE X, R1 M[X] R1
The LOAD instructions transfer the operand P, Q, R and S from memory to CPU registers R1, R2,
R3, and R4 respectively. The ADD and MUL instructions execute the addition and multiplication
operations with the data in the registers without referring to the memory. The STORE instruction
stores the result of the computation in the memory (M[X]).

4.8.2 RISC Versus CISC Notes

There are some significant differences between RISC and CISC processors. The comparison
between the common characteristics of RISC and CISC processor is shown in table 4.8.
Today, RISC and CISC architectures are becoming more alike. Many RISC chips now support
instructions of CISC chips also. Similarly, CISC chips are using many techniques associated with
RISC chips.