SN65176B, SN75176B

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SNx5176B Differential Bus Transceivers

Check for Samples: SN65176B, SN75176B

1FEATURES DESCRIPTION
• Bidirectional Transceivers The SN65176B and SN75176B differential bus
transceivers are integrated circuits designed for
• Meet or Exceed the Requirements of ANSI bidirectional data communication on multipoint bus
Standards TIA/EIA-422-B and TIA/EIA-485-A transmission lines. They are designed for balanced
and ITU Recommendations V.11 and X.27 transmission lines and meet ANSI Standards
• Designed for Multipoint Transmission on TIA/EIA-422-B and TIA/EIA-485-A and ITU
Long Bus Lines in Noisy Environments Recommendations V.11 and X.27.
• 3-State Driver and Receiver Outputs The SN65176B and SN75176B devices combine a 3-
• Individual Driver and Receiver Enables state differential line driver and a differential input line
receiver, both of which operate from a single 5-V
• Wide Positive and Negative Input/Output Bus
power supply. The driver and receiver have active-
Voltage Ranges high and active-low enables, respectively, that can be
• ± 60-mA Max Driver Output Capability connected together externally to function as a
• Thermal Shutdown Protection direction control. The driver differential outputs and
the receiver differential inputs are connected
• Driver Positive and Negative Current Limiting internally to form differential input/output (I/O) bus
• 12-kΩ Min Receiver Input Impedance ports that are designed to offer minimum loading to
• ± 200-mV Receiver Input Sensitivity the bus when the driver is disabled or VCC = 0. These
ports feature wide positive and negative common-
• 50-mV Typ Receiver Input Hysteresis
mode voltage ranges, making the device suitable for
• Operate From Single 5-V Supply party-line applications.
The driver is designed for up to 60 mA of sink or
source current. The driver features positive and
negative current limiting and thermal shutdown for
protection from line-fault conditions. Thermal
shutdown is designed to occur at a junction
temperature of approximately 150°C. The receiver
features a minimum input impedance of 12 kΩ, an
input sensitivity of ±200 mV, and a typical input
hysteresis of 50 mV.
The SN65176B and SN75176B devices can be used
in transmission-line applications employing the
SN75172 and SN75174 quadruple differential line
drivers and SN75173 and SN75175 quadruple
differential line receivers.

SN65176B D OR P PACKAGE
SN75176B D, P, OR PS PACKAGE
(TOP VIEW)

R 1 8 VCC
RE 2 7 B
DE 3 6 A
D 4 5 GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 1985–2014, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65176B, SN75176B
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Function Tables
XXX
Driver (1)
INPUT ENABLE OUTPUTS
D DE
A B
H H H L
L H L H
X L Z Z

(1) H = high level,

L = low level,
? = indeterminate,
X = irrelevant,
Z = high impedance (off)

Receiver (1)
DIFFERENTIAL
ENABLE OUTPUT
INPUTS
RE R
A–B
VID ≥ 0.2 V L H
–0.2 V < VID < 0.2 V L ?
VID ≤ –0.2 V L L
X H Z
Open L ?

(1) H = high level,

L = low level,
? = indeterminate,
X = irrelevant,
Z = high impedance (off)

Logic Diagram (Positive Logic)

3
DE
4
D
2
RE 6
1 A
R 7 Bus
B

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SCHEMATICS OF INPUTS AND OUTPUTS

XXX
EQUIVALENT OF EACH INPUT TYPICAL OF A AND B I/O PORTS TYPICAL OF RECEIVER OUTPUT

VCC VCC VCC

85 Ω
R(eq) NOM

16.8 kΩ 960 Ω
Input NOM NOM

960 Ω
NOM Output

GND
Driver input: R(eq) = 3 kΩ NOM Input/Output
Enable inputs: R(eq )= 8 kΩ NOM Port
R(eq) = Equivalent Resistor

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Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
(2)
VCC Supply voltage 7 V
Voltage range at any bus terminal –10 15 V
VI Enable input voltage 5.5 V
D package 97
θJA Package thermal impedance (3) (4) P package 85 °C/W
PS package 95
TJ Operating virtual junction temperature 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
(3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.

Recommended Operating Conditions

MIN TYP MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
12
VI or VIC Voltage at any bus terminal (separately or common mode) V
–7
VIH High-level input voltage D, DE, and RE 2 V
VIL Low-level input voltage D, DE, and RE 0.8 V
VID Differential input voltage (1) ±12 V
Driver –60 mA
IOH High-level output current
Receiver –400 µA
Driver 60
IOL Low-level output current mA
Receiver 8
SN65176B –40 105
TA Operating free-air temperature °C
SN75176B 0 70

(1) Differential input/output bus voltage is measured at the noninverting terminal A, with respect to the inverting terminal B.

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Driver Section
Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS (1) MIN TYP (2) MAX UNIT
VIK Input clamp voltage II = –18 mA –1.5 V
VO Output voltage IO = 0 0 6 V
|VOD1| Differential output voltage IO = 0 1.5 3.6 6 V
(3)
RL = 100 Ω, see Figure 1 1/2 VOD1 or 2
|VOD2| Differential output voltage V
RL = 54 Ω, see Figure 1 1.5 2.5 5
(4)
VOD3 Differential output voltage See 1.5 5 V
Change in magnitude of
∆|VOD| RL = 54 Ω or 100 Ω, see Figure 1 ±0.2 V
differential output voltage (5)
+3
VOC Common-mode output voltage RL = 54 Ω or 100 Ω, see Figure 1 V
–1
Change in magnitude of
∆|VOC| common-mode output RL = 54 Ω or 100 Ω, see Figure 1 ±0.2 V
voltage (5)
VO = 12 V 1
IO Output current Output disabled (6) mA
VO = –7 V –0.8
IIH High-level input current VI = 2.4 V 20 µA
IIL Low-level input current VI = 0.4 V –400 µA
VO = –7 V –250
VO = 0 –150
IOS Short-circuit output current mA
VO = VCC 250
VO = 12 V 250
Outputs enabled 42 70
ICC Supply current (total package) No load mA
Outputs disabled 26 35

(1) The power-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and
outputs.
(2) All typical values are at VCC = 5 V and TA = 25°C.
(3) The minimum VOD2 with a 100-Ω load is either 1/2 VOD1 or 2 V, whichever is greater.
(4) See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2.
(5) Δ|VOD| and Δ|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level
to a low level.
(6) This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does not
apply for a combined driver and receiver terminal.

Switching Characteristics
VCC = 5 V, RL = 110 Ω, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(OD) Differential-output delay time RL = 54 Ω, see Figure 3 15 22 ns
tt(OD) Differential-output transition time RL = 54 Ω, see Figure 3 20 30 ns
tPZH Output enable time to high level See Figure 4 85 120 ns
tPZL Output enable time to low level See Figure 5 40 60 ns
tPHZ Output disable time from high level See Figure 4 150 250 ns
tPLZ Output disable time from low level See Figure 5 20 30 ns

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Symbol Equivalents
DATA SHEET
TIA/EIA-422-B TIA/EIA-485-A
PARAMETER
VO Voa, Vob Voa, Vob
|VOD1| Vo Vo
|VOD2| Vt (RL = 100 Ω) Vt (RL = 54 Ω)
Vt (test termination
|VOD3|
measurement 2)
∆|VOD| | |Vt| – |Vt| | | |Vt – |Vt| |
VOC |Vos| |Vos|
∆|VOC| |Vos – Vos| |Vos – Vos|
IOS |Isa|, |Isb|
IO |Ixa|, |Ixb| Iia, Iib

Receiver Section
Electrical Characteristics
over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VIT+ Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V
VIT– Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA –0.2 (2) V
Vhys Input hysteresis voltage (VIT+ – VIT–) 50 mV
VIK Enable Input clamp voltage II = –18 mA –1.5 V
VOH High-level output voltage VID = 200 mV, IOH = –400 µA, see Figure 2 2.7 V
VOL Low-level output voltage VID = –200 mV, IOL = 8 mA, see Figure 2 0.45 V
IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA
VI = 12 V 1
II Line input current Other input = 0 V (3) mA
VI = –7 V –0.8
IIH High-level enable input current VIH = 2.7 V 20 µA
IIL Low-level enable input current VIL = 0.4 V –100 µA
rI Input resistance VI = 12 V 12 kΩ
IOS Short-circuit output current –15 –85 mA
Outputs enabled 42 55
ICC Supply current (total package) No load mA
Outputs disabled 26 35

(1) All typical values are at VCC = 5 V, TA = 25°C.

(2) The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-
mode input voltage and threshold voltage levels only.
(3) This applies for both power on and power off. Refer to EIA Standard TIA/EIA-485-A for exact conditions.

Switching Characteristics
VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output 21 35
VID = 0 to 3 V, see Figure 6 ns
tPHL Propagation delay time, high- to low-level output 23 35
tPZH Output enable time to high level 10 20
See Figure 7 ns
tPZL Output enable time to low level 12 20
tPHZ Output disable time from high level 20 35
See Figure 7 ns
tPLZ Output disable time from low level 17 25

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Parameter Measurement Information

RL
2 ID
VOD2 VOH
RL +IOL –IOH
VOC
2 VOL

Figure 1. Driver VOD and VOC Figure 2. Receiver VOH and VOL

3V
Input 1.5 V 1.5 V
CL = 50 pF 0V
(see Note A) td(OD) td(OD)
RL = 54 Ω
Generator 50 Ω Output
90% ≈2.5 V
(see Note B)
Output 50% 50%
10% 10% ≈–2.5 V
3V
tt(OD) tt(OD)
TEST CIRCUIT VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.

Figure 3. Driver Test Circuit and Voltage Waveforms

Output 3V
S1 Input 1.5 V 1.5 V
0 V or 3 V 0V
CL = 50 pF tPZH 0.5 V
RL = 110 Ω
(see Note A) VOH
Generator
50 Ω Output 2.3 V
(see Note B)
tPHZ Voff ≈0 V

TEST CIRCUIT VOLTAGE WAVEFORMS

A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.

Figure 4. Driver Test Circuit and Voltage Waveforms

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Parameter Measurement Information (continued)

5V
3V
RL = 110 Ω Input 1.5 V 1.5 V
S1 Output 0V
3 V or 0 V
CL = 50 pF tPZL tPLZ
(see Note A)
Generator 50 Ω 5V
(see Note B) 0.5 V
Output 2.3 V
VOL

TEST CIRCUIT VOLTAGE WAVEFORMS

A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.

Figure 5. Driver Test Circuit and Voltage Waveforms

3V
Input 1.5 V 1.5 V
Generator Output 0V
51 Ω
(see Note B) tPLH tPHL
1.5 V CL = 15 pF
(see Note A) VOH
Output 1.3 V 1.3 V
0V
VOL
TEST CIRCUIT VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.

Figure 6. Receiver Test Circuit and Voltage Waveforms

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Parameter Measurement Information (continued)

1.5 V S1

2 kΩ S2
–1.5 V 5V

CL = 15 pF
(see Note A) 5 kΩ 1N916 or Equivalent

Generator
50 Ω
(see Note B)
S3

TEST CIRCUIT

3V 3V
Input 1.5 V Input 1.5 V
S1 to 1.5 V S1 to –1.5 V
0V S2 Open 0 V S2 Closed
tPZH S3 Closed S3 Open
tPZL
VOH
1.5 V ≈4.5 V
Output
Output 1.5 V
0V
VOL

3V 3V
S1 to 1.5 V S1 to –1.5 V
Input 1.5 V S2 Closed Input 1.5 V S2 Closed
S3 Closed S3 Closed
0V 0V
tPHZ
tPLZ
VOH ≈1.3 V
0.5 V
Output Output 0.5 V
≈1.3 V VOL

VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤1 MHz, 50% duty cycle, tr ≤ 6
ns, tf ≤ 6 ns, ZO = 50 Ω.

Figure 7. Receiver Test Circuit and Voltage Waveforms

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Typical Characteristics
5 5
VCC = 5 V VCC = 5 V
4.5 TA = 25°C 4.5 TA = 25°C
VOH – High-Level Output Voltage – V

VOL – Low-Level Output Voltage – V

4 4

3.5 3.5

3 3

2.5 2.5

2 2

1.5 1.5
VOH

1 1

0.5 0.5

0 0
0 –20 –40 –60 –80 –100 –120 0 20 40 60 80 100 120
IOH – High-Level Output Current – mA IOL – Low-Level Output Current – mA
Figure 8. Driver High-Level Output Voltage Figure 9. Driver Low-Level Output Voltage
vs vs
High-Level Output Current Low-Level Output Current

4 5
VID = 0.2 V
VCC = 5 V
4.5 TA = 25°C
3.5 TA = 25°C
VOD – Differential Output Voltage – V

VOH – High-Level Output Voltage – V

4
3
3.5
2.5
3

2 2.5
VCC = 5.25 V
2 VCC = 5 V
1.5
1.5
VCC = 4.75 V
1
VOD

1
VOH

0.5 0.5

0 0
0 10 20 30 40 50 60 70 80 90 100 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50
IO – Output Current – mA IOH – High-Level Output Current – mA
Figure 10. Driver Differential Output Voltage Figure 11. Receiver High-Level Output Voltage
vs vs
Output Current High-Level Output Current

5 0.6
VCC = 5 V VCC = 5 V
4.5 VID = 200 mV TA = 25°C
VOL – Low-Level Output Voltage – V

IOH = –440 µA
VOH – High-Level Output Voltage – V

0.5
4

3.5
0.4
3

2.5 0.3

2
0.2
1.5
VOL

1
VOH

0.1
0.5

0 0
–40 –20 0 20 40 60 80 100 120 0 5 10 15 20 25 30
TA – Free-Air Temperature – °C IOL – Low-Level Output Current – mA

Only the 0°C to 70°C portion of the curve applies to the SN75176B
device.
Figure 12. Receiver High-Level Output Voltage Figure 13. Receiver Low-Level Output Voltage
vs vs
Free-Air Temperature Low-Level Output Current

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Typical Characteristics (continued)

0.6 5
VCC = 5 V VID = 0.2 V
VID = –200 mV Load = 8 kΩ to GND
VOL – Low-Level Output Voltage – V

0.5 IOL = 8 mA TA = 25°C

4 VCC = 5.25 V

VO – Output Voltage – V
0.4
VCC = 5 V
3 VCC = 4.75 V

0.3

2
0.2

VO
VOL

1
0.1

0 0
–40 –20 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3
TA – Free-Air Temperature – °C VI – Enable Voltage – V
Figure 14. Receiver Low-Level Output Voltage Figure 15. Receiver Output Voltage
vs vs
Free-Air Temperature Enable Voltage

6
VID = –0.2 V
VCC = 5.25 V
Load = 1 kΩ to VCC
5 TA = 25°C
VCC = 4.75 V
VO – Output Voltage – V

VCC = 5 V
4

2
VO

0
0 0.5 1 1.5 2 2.5 3
VI – Enable Voltage – V
Figure 16. Receiver Output Voltage
vs
Enable Voltage

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APPLICATION INFORMATION
SN65176B SN65176B
SN75176B SN75176B

RT RT

Up to 32
Transceivers

The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line
should be kept as short as possible.

Figure 17. Typical Application Circuit

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REVISION HISTORY

Changes from Revision D (April 2003) to Revision E Page

• Updated document to new TI data sheet format - no specification changes. ...................................................................... 1

• Deleted Ordering Information table. ...................................................................................................................................... 1
• Added ESD warning. ............................................................................................................................................................ 2

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN65176BD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 65176B
& no Sb/Br)
SN65176BDE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 65176B
& no Sb/Br)
SN65176BDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 65176B
& no Sb/Br)
SN65176BDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 105 65176B
& no Sb/Br)
SN65176BDRE4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 65176B
& no Sb/Br)
SN65176BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 65176B
& no Sb/Br)
SN65176BP ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 105 SN65176BP
(RoHS)
SN65176BPE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 105 SN65176BP
(RoHS)
SN75176BD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 75176B
& no Sb/Br)
SN75176BDE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 75176B
& no Sb/Br)
SN75176BDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 75176B
& no Sb/Br)
SN75176BDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 75176B
& no Sb/Br)
SN75176BDRE4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 75176B
& no Sb/Br)
SN75176BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 75176B
& no Sb/Br)
SN75176BP ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 SN75176BP
(RoHS)
SN75176BPE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 SN75176BP
(RoHS)
SN75176BPSR ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 A176B
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN75176BPSRG4 ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 A176B

& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Feb-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65176BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65176BDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75176BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75176BDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75176BPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Feb-2014

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65176BDR SOIC D 8 2500 340.5 338.1 20.6
SN65176BDRG4 SOIC D 8 2500 340.5 338.1 20.6
SN75176BDR SOIC D 8 2500 340.5 338.1 20.6
SN75176BDRG4 SOIC D 8 2500 340.5 338.1 20.6
SN75176BPSR SO PS 8 2000 367.0 367.0 38.0

Pack Materials-Page 2
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