UNIT I INTRODUCTION TO MOS TRANSISTOR

1.1. MOS logic families (NMOS and CMOS)

1.2. Ideal and Non Ideal IV Characteristics
1.3. CMOS devices.
1.4. MOS(FET) Transistor Characteristic under Static and Dynamic Conditions
1.5. Technology Scaling
1.6. Power consumption MOS Transistor
Classification Logic families:

MOS Logic family

MOS logic family implements the logic gates using MOSFET devices. MOSFETs are high
density devices which can easily and economically fabricated on ICs. MOS logic gates can be
fabricated using either only NMOS or only PMOS devices.
MOS logic is vastly used in LSI and VLSI devices, such as microprocessor chips, due to their
high density characteristic.

NMOS NOR gate is shown in figure.

If both transistors T1 and T2 are off i.e. A = B = LOW, then output is HIGH = VDD.
If either of the inputs is HIGH, then corresponding transistor(s) is/are ON, thus connecting
output to GND i.e. LOW.

If both inputs are ON, then only both T1 and T2 are ON and output is LOW; otherwise
(when either or both transistors are OFF,) the output is HIGH.

This is NAND operation on applied inputs.

!! Caution for using MOS devices:

If any of input of MOS is left unconnected, the open input terminal which has very
high input impedance may take any stray electric charge as input and can develop extreme
dangerous high voltage which can damage the device and may also harm the person
handling the device.
Thus, none of the un-used inputs of MOS device should be left unconnected. It must
connected to ground or supply. Even for storage of device, all pins must be shorted.

CMOS Logic family

CMOS stands for complementary-MOS, in which both p-channel and n-channel
enhancement MOSFET devices are fabricated on same chip. This causes density to be
reduced and complex fabrication process. However, CMOS devices consume negligible
power and hence are preferred over MOS devices in battery operated applications.

A CMOS NAND gate is shown in figure aside.

T1 and T2 are n-channel MOSFETs while T3 and T4 are p-channel MOSFETs.

When both inputs A & B are HIGH, then T1 & T2 are ON while T3 & T4 are OFF. Hence,
output is connected to GND i.e. LOW.

If either input is LOW, then either T3 or T4 is ON, connecting output is +Vcc i.e. HIGH.
Similar is working of CMOS NOR gate shown in figure aside. Here, p-channel devices are in
series and n-channel devices are in parallel.

1. Explain in detail about the operation of NMOS transistor with neat sketch.
or
Explain the operation of n-channel enhancement transistor with neat sketch.

Answer:

NMOS (N-channel Metal – Oxide – Semiconductor) Transistor

Introduction

 The MOS transistor is a majority-carrier device in which the current, in a conducting channel
between the source and drain, is controlled by a voltage applied to the gate.

 In an nMOS transistor, the majority carriers are electrons; in a pMOS transistor, the majority
carriers are holes.
 Symbol of NMOS Transistor

Simple MOS structure:The behaviour of MOS transistor can be understood by examining the
isolated MOS structure with a gate and body as shown in Fig.1.

1. The top layer of the structure is a good conductor (metal or poly-silicon) called the
gate.
2. The middle layer is a very thin insulating film of SiO2 called the gate oxide
3. The bottom layer is the doped silicon (semiconductor) body.

 In Fig.1(a), a negative voltage is applied to the

gate, resulting in some negative charge on the gate
 The holes in the body are attracted to the region
beneath the gate.
 This is called the accumulation mode. Fig.1.(a)

 In Fig.1(b), a small positive voltage is applied to

the gate, resulting in some positive charge on the
gate.
 The holes in the body are repelled from the region
directly beneath the gate. Fig.1.(b)
 The region, with depleted of carriers, is called
depletion region.
 In Fig.1(c), a higher positive potential exceeding
a critical (threshold) voltage,Vt, is applied to the
gate.
 The holes are repelled further and some free
electrons in the body are attracted to the region
beneath the gate.
Fig.1.(c)
 This conductive layer of electrons in the p-type
body is called the inversion layer.
 The threshold Gate voltage, Vt, depends on the
number of dopants in the body and the thickness
tox of the oxide.

Three mode(Region) of Operation for nMOS Transistor:

 Depends on the supply voltage to the three terminals (Source, Gate, Drain) of the nMOS
transistor, there are three mode of operations (cut-off, linear, Saturation).
Cut-off Mode (Region):
o In Fig. 2(a), the gate-to-source voltage Vgs is less than
the threshold voltage(Vgs<Vt).
o The source and drain have free electrons, but the body
has no free electrons.
o Therefore, almost zero current flows. We say the
Fig.2.(a)
transistor is OFF, and this mode of operation is
called cutoff.

Linear Mode (Region):

o In Fig.2(b), the gate-to-source voltage is greater than
the threshold voltage(Vgs>Vt).
o Now, an inversion region of electrons (majority
carriers) called the channel connects the source and
drain as shown in Fig.2(b), creating a conductive path
Fig.2.(b)
and turning the transistor ON.
o The number of carriers and the conductivity increases
with the gate voltage.
o When a small positive potential Vds is applied to the
drain (Fig.2(c)), current Ids flows through the channel
from drain to source.
o This mode of operation is termed linear, resistive, Fig.2.(c)
triode, non-saturated, or unsaturated; the current increases with both the drain
voltage and gate voltage.

Saturation Mode (Region) :

o In Fig.2(d), the gate-to-source voltage is greater
o than the threshold voltage(Vgs>Vt).
o If Vds becomes sufficiently large that Vds>Vgs - Vt,
the channel is no longer inverted near the drain
and becomes pinched-off as shown in Fig.2(d).
o However, conduction is still brought about by the drift ofFig.2.(d)
electrons under the
influence of the positive drain voltage.
o As electrons reach the end of the channel, they are injected into the depletion
region near the drain and accelerated toward the drain.
o Above this drain voltage the current Ids is controlled only by the gate voltage and
ceases to be influenced by the drain. This mode is called saturation.
Summary of I-V characteristics : The nMOS transistor has three modes of operation.
1. IfVgs<Vt, the transistor is cut-off (OFF).
2. If Vgs>Vt and Vdsis small(0<Vds<(Vgs-Vt)), the transistor acts as a linear resistor in
which the current flow is proportionalto Vds.
3. If Vgs>Vtand Vdsis large(Vds> (Vgs-Vt)), the transistor acts as a current source in
which the current flow becomes independent of Vds.

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 Ques:
Explain in detail about the operation of PMOS transistor with neat sketch.
OR
Explain the operation of p-channel enhancement transistor with neat sketch.

PMOS ( P-channel Metal Oxide Semiconductor ) Transistor

1. A reversal of n-type and p-type regions yields a p-channel MOS transistor.
2. Application of negative gate voltage (w.r.t source) draws holes into the region below
the gate, resulting in the channel changing from n-type to p-type.
3. The conduction results from the movement of holes in the channel.

Symbol of pMOS Transistor

Ideal (Long-Channel) Model I-V Characteristics

MOS transistors have three regions of operation:
1. Cutoff or sub-threshold region
2. Linear region
3. Saturation region
The model assumes that the channel length is long enough that the lateral electric field (the field
between source and drain) is relatively low.
This model is variously known as the long-channel, ideal, first-order, or Shockley model. The
long-channel model assumes that the current through an OFF transistor is 0(Cut-off).
Current in the Linear Region:
(i) When a transistor turns ON (Vgs>Vt), the electrons drift from source to drain at a
rate proportional to the electric field between these regions.
(ii)We can compute the current between source and drain (I ds), if we know the amount
of charge in the channel and the rate at which it moves.
 (iii)The time required for carriers to cross the channel is the channel length(L) divided by
the carrier velocity(V): time = L/v.

Therefore, Ids = …(1)

We know that the charge on each plate of a capacitor is Q = CV.

Thus, the charge in the channel,Qchannel = Cg (Vgc – Vt ) ….(2)
Where, Cg- is the capacitance of the gate to the channel.
(Vgc– Vt) - is the minimum voltagerequired to form a channel.

Vgc - is the average gate to channel potential.

We can model the gate as a parallel plate capacitor with capacitance proportional toarea over
thickness. If the gate has length L and width W and the oxide thickness is tox, as shown in Fig.3, the

capacitance, Cg = kox o = ox = CoxWL ….(3)

General form for Capacitance, C = , where, A- area; = ; d-distance b/w two parallel plates.

Where, o-permittivity of free space, 8.85 x 10–14 F/cm ;

Kox( )–relative permittivity of SiO2, Kox =3.9 ;

Often, the ox /tox term is called Cox, the capacitance per unitarea of the gate oxide.

Each carrier in the channel is accelerated to an average velocity, v, proportional to thelateral

electric field, i.e., the field between source and drain. The constant of proportionality is called the

mobility.Therefore, Velocity, = E …..(4)

(iii)The electric field,E,is the voltage difference between drain and source ,Vds,divided by the

channel length,L. E= ..…(5)

Eqns .(1),(2),(3)and (4) :Ids = = =

….(6)

Where, = ;

Eqn.(6) describes the linear region of operation, for Vgs>Vt, but Vds relatively small. It iscalled
linear or resistive because when Vds<<(Vgs – Vt), Ids increases almost linearly with Vds,just like an
ideal resistor.

Current in the Saturation Region:

If Vds>Vdsat( , wesay it is pinched off. Beyond this point, called the drain saturation

voltage, increasing thedrain voltage has no further effect on current.

Ids = ….(7)

This expression is valid for Vgs>Vtand Vds>Vdsat. Thus, long-channel MOS transistorsare said to
exhibit square-law behavior in saturation.
EQ (2.10) summarizes the current in the three regions:

Ids = …..(8)
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3. Explain in detail about the DC Transfer Characteristics of CMOS inverter.
OR
Describe the CMOS inverter and Derive its DC characteristics.

 Fig.1shows the schematic and symbol for a CMOS

inverter or NOT gate using one nMOS transistor and
one pMOS transistor.
 The bar at the top indicates VDD and the triangle at
the bottom indicates GND.
 When the input A is 0, the nMOS transistor is OFF
and the pMOS transistor is ON.
 Thus, the output Y is pulled up to 1 because it is
connected to VDD but not to GND.
 Conversely, when A is 1, the nMOS is ON, the pMOS
is OFF, and Y is pulled down to ‘0.’ Fig.1. CMOS inverter

DC Transfer Characteristics
The DC transfer characteristics (sometimes called the voltage-transfer characteristic) of a
CMOS inverter relate the output voltage to the input voltage, assuming the input changes slowly
enough that capacitances have plenty of time to charge or discharge. Specific ranges of input and
output voltages are defined as valid 0 and 1 logic levels.
The operation of the CMOS inverter can be divided into five regions indicated on Figure. The
state of each transistor in each region is shown in Table.
In region A, the nMOS transistor is OFF so the pMOS transistor pulls the output to VDD.
In region B, the nMOS transistor starts to turn ON, pulling the output down.
In region C, both transistors are in saturation.
In region D, the pMOS transistor is partially ON
In region E, the pMOS transistor is completely OFF, leaving the nMOS transistor to pull the
output down to GND.

Fig.2. DC Characteristics
 Derivation for the
Output voltage, Vout:
Let us derive the DC transfer function (Vout vs. Vin) for the static CMOS inverter shown in Fig.
The output voltage can be derived by solving Idsn= - Idsp
Let, Vtn- threshold voltage of the n-channel device; Vtp - threshold voltage of the p-channel device.
As the source of the nMOS transistor is grounded,
Vgsn= Vin and Vdsn= Vout. …..(1)
As the source of the pMOS transistor is tied to VDD,
Vgsp= Vin – VDDand Vdsp= Vout – VDD. ……(2)

Source-to-drain current (Ids) in three regions:

Ids= …..(3)

Region A (0 ≤Vin ≤Vtn):

In this region, the ‘n’ device is in cut off region(represented by an open circuit) and the ‘p’
device is in linear region(represented by a resistor).The equivalent circuit is shown in Fig.2.
Since, Idsn= 0 Idsp = Vdsp= 0. VDD

substituting, Vdsp value in Eqn.(2): Vdsp(= 0) = Vout – VDD ;

Vout
The output voltage, Vout = VDD Fig.2. Equivalent ckt.

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Region B (Vtn ≤Vin ≤VDD /2 ) :
In this region, the ‘n’ device is in saturation region (represented by a Current source) and the ‘p’
device is in linear region.The equivalent circuit is shown in Fig.3.
VDD

Eqns.(3) and (1): Idsn = = …..(4)

Vout

Fig.3. Equivalent ckt.

Eqns.(3) and (2): Idsp =

= ..(5)

Equating Eqns.(4) and (5):

Vout= (Vin – Vtp) + …..(6)

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Region C ( ):

In this region, both the ‘n’ and ‘p’ devices are in saturation. The equivalent circuit is shown in Fig.4.

Eqns.(3) and (1): Idsn = = …..(7) VDD

Eqns.(3) and (2): Idsp = = …..(8) Vout

Equating Eqns.(7) and (8): Fig.4. Equivalent ckt.

Vin – Vtn<Vout< Vin - Vtp

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Region D (VDD /2 ≤Vin ≤ VDD - |Vtp|) :
In this region, the ‘n’ device is in linear regionand the ‘p’ device is in saturation region.The
equivalent circuit is shown in Fig.5.
VDD
Eqns.(3) and (1): Idsn =
Vout

Fig.5. Equivalent ckt.

= …..(9)

Eqns.(3) and (2): Idsp = = .(10)

Vout= (Vin – Vtn) - …..(6)

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Region E (0 ≤Vin ≤Vtn): VDD

Vout

Fig.6. Equivalent ckt.

 In this region, the ‘n’ device is in linear region and the ‘p’ device is in
cut-off region.The equivalent circuit is shown in Fig.6.

The output voltage, Vout = 0.

 Explain the various second order effects. Or Nonideal effects
1. Mobility Degradation and Velocity Saturation
o Carrier drift velocity, and hence current, is proportional to the lateral electric field Elat =
Vds/L between source and drain.
o The constant of proportionality is called the carrier mobility, . The long-channel model
assumed that carrier mobility is independent of the applied fields. This is a good
approximation for low fields, but breaks-down when strong lateral or vertical fields are
applied.
o Therefore, at high lateral field strengths(Vds/L), carrier velocity ceases to increase linearly
with field strength. This is called velocity saturation and results in lower Ids than expected
at high Vds.
o At high vertical field strengths(Vgs/tox ), the carriers scatter off the oxide interface more
often, slowing their progress. This mobility degradation effect also leads to less current
than expected at high Vgs.
o In other words, A high voltage at the gate of the transistor attracts the carriers to the edge
of the channel, causing collisions with the oxide interface that slow the carriers. This is
called mobility degradation.

2. Channel Length Modulation

o Ideally, Ids is independent of Vds for a transistor in
saturation, making the transistor a perfect current source.
o A p-n junction between the drain and body forms a
depletion region with a width Ld that increases with Vdb, as
shown in Fig.
o The depletion region effectively shortens the channel
length to
o Leff = L – Ld
o Channel length modulation is very important to analog designers because it reduces the
gain of amplifiers.

3. Threshold Voltage Effects

o The threshold voltage Vt increases with the source voltage, decreases with the body
voltage, decreases with the drain voltage, and increases with channel length. This section
models each of these effects.
Body Effect:
o Until now, we have considered a transistor to be a three-terminal device with gate,
source, and drain. However, the body is an implicit fourth terminal. When a voltage
Vsb is applied between the source and body, it increases the amount of charge
required to invert the channel, hence, it increases the threshold voltage. The
threshold voltage can be modeled as
 o where Vt0 is the threshold voltage when the source is at the body potential, is the
surface potential at threshold and is the body effect coefficient.

o In turn, these depend on the doping level in the channel, NA.

Short-Channel Effect:
o The threshold voltage typically increases with channel length(L).
o This phenomenon is especially pronounced for small L where the source and drain
depletion regions extend into a significant portion of the channel, and hence is called the
short channel effect .
Drain-Induced Barrier Lowering:
o The drain voltage Vds creates an electric field that affects the threshold voltage.
o This drain-induced barrier lowering (DIBL) effect is especially pronounced in short-channel
transistors. It can be modeled as
Vt = Vt0 - Vds

o Where is the DIBL coefficient, typically on the order of 0.1 (often expressed as 100 mV/V).

o Drain-induced barrier lowering causes Ids to increase with Vds in saturation, in much the
same way as channel length modulation does. More significantly, DIBL increases sub-
threshold leakage at high Vds.
4. Leakage
o Even when transistors are nominally OFF, they leak small amounts of current. Leakage
mechanisms include sub-threshold conduction between source and drain, gate leakage from
the gate to body, and junction leakage from source to body and drain to body, as illustrated
in Fig.
o Sub-threshold conduction is caused by thermal emission of
carriers over the potential barrier set by the threshold.
o Gate leakage is a quantum-mechanical effect caused by
tunneling through the extremely thin gate dielectric.
Junction leakage is caused by current through the p-n
junction between the source/drain diffusions and the body.
o In processes with feature sizes above 180 nm, leakage was
typically insignificant except in very low power applications.
o In 90 and 65 nm processes, threshold voltage has reduced to
the point that sub-threshold leakage reaches levels of 1s to 10s of nA per transistor, which
is significant when multiplied by millions or billions of transistors on a chip.
Fig.(c): In 45 nm processes, oxide thickness reduces to the point that gate leakage becomes
o
comparable to sub-threshold leakage unless high-k gate dielectrics are employed. Overall,
leakage has become an important design consideration in nanometer processes.
5. Temperature Dependence
Transistor characteristics are influenced by temperature. Carrier mobility decreases with
temperature. An approximate relation is
 =

Where, T is the absolute temperature, Tr is room temperature, and is a fitting parameter with a

typical value of about 1.5.

The magnitude of the threshold voltage decreases nearly linearly with temperature and
may be approximated by
Vt(T) = Vt (Tr) - kvt(T – Tr) where, kvtis typically about 1–2 mV/K.
Write short notes on i) Static CMOS, ii) Bubble pushing, iii)Compound gates.

Static CMOS
1. Static CMOS circuits with complementary nMOS pull-down and pMOS pull-up networks
are used for the vast majority of logic gates in integrated circuits.
2. They have good noise-margins, and are fast, low power, insensitive to device variations,
easy to design, widely supported by CAD tools, and readily available in standard cell
libraries.
3. When noise does exceed the margins, the gate delay increases because of the glitch, but
the gate eventually will settle to the correct answer.
4. Most design teams now use static CMOS exclusively for combinational logic.
5. The most important alternative is dynamic circuits. However, we begin by considering
ratioed circuits, which are simpler and offer a helpful conceptual transition between static
and dynamic.

6. Designers accustomed to AND and OR functions must learn to think in terms of NAND
and NOR to take advantage of static CMOS.
7. In manual circuit design, this is often done through bubble pushing. Compound gates are
particularly useful to perform complex functions with relatively low logical efforts.
8. When a particular input is known to be latest, the gate can be optimized to favor that
input. Similarly, when either the rising or falling edge is known to be more critical, the
gate can be optimized to favor that edge.
9. We have focused on building gates with equal rising and falling delays; however, using
smaller pMOS transistors can reduce power, area, and delay.
10. In processes with multiple threshold Voltages, multiple flavors of gates can be
constructed with different speed/leakage power trade-offs.
2.2 Bubble Pushing
1. CMOS stages are inherently inverting, so AND and OR functions must be built from
NAND and NOR gates.
2. DeMorgan’s law helps with this conversion:
(9.2)
 3. These relations are illustrated graphically in Figure 9.1.

4. A NAND gate is equivalent to an OR of inverted inputs.

5. A NOR gate is equivalent to an AND of inverted inputs.
6. The same relationship applies to gates with more inputs. Switching between these
representations is easy to do on a white-board and is often called bubble pushing.

2.3 Compound Gates

1. Static CMOS also efficiently handles compound gates computing various inverting
combinations of AND/OR functions in a single stage.
2. The function F = AB + CD can be computed with an AND-OR-INVERT-22 (AOI22)
gate and an inverter, as shown in Fig.9.3.

3. In general, logical effort of compound gates can be different for different inputs. Fig. 9.4
shows how logical efforts can be estimated for the AOI21, AOI22, and a more complex
compound AOI gate.
4. The transistor widths are chosen to give the same drive as a unit inverter.
5. The logical effort of each input is the ratio of the input capacitance of that input to the
input capacitance of the inverter.
 6. For the AOI21 gate, this means the logical effort is slightly lower for the OR terminal (C)
than for the two AND terminals (A, B).
7. The parasitic delay is crudely estimated from the total diffusion capacitance on the output
node by summing the sizes of the transistors attached to the output.
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-

Input Ordering Delay Effect

1. The logical effort and parasitic delay of different gate inputs are often different.
2. Some logic gates, like theAOI21 in the previous section, are inherently asymmetric in
that one input sees less capacitance than another.
3. Other gates like NANDs and NORs, are nominally symmetric but actually have slightly
different logical effort and parasitic delays for the different inputs.

4. Figure 9.6 shows a 2-input NAND gate annotated with diffusion capacitances.
5. Consider the falling output transition occurring when one input held a stable 1 value and
the other rises from 0 to 1.
6. If input B rises last, node x will initially be at VDD – Vt VDD because it was pulled-up
through the nMOS transistor on input A.
7. The Elmore delay is (R/2)(2C) + R(6C) = 7RC= 2.33 .
8. On the other hand, if input A rises last, node x will initially be at 0 V because it was
discharged through the nMOS transistor on input B.
9. No charge must be delivered to node x, so the Elmore delay is simply R(6C) = 6RC = 2
.
10. In general, we define the outer input to be the input closer to the supply rail (e.g., B) and
the inner input to be the input closer to the output (e.g., A).
Write a short notes on (i) Asymmetric gates
(ii) Skewed Gates

Asymmetric Gates
1. When one input is far less critical than another, even nominally symmetric gates can be
made asymmetric to favor the late input at the expense of the early one.
 2. In a series network, this involves connecting the early input to the outer transistor and
making the transistor wider so that it offers less series resistance when the critical input
arrives.
3. In a parallel network, the early input is connected to a narrower transistor to reduce the
parasitic capacitance.
4. For example, consider the path in Figure 9.7(a). Under ordinary
conditions, the path acts as a buffer between A and Y.
5. When reset is asserted, the path forces the output low. If reset only
occurs under exceptional circumstances and can take place slowly, the
circuit should be optimized for input-to-output delay at the expense of
reset.
6. This can be done with the asymmetric NAND gate in Figure 9.7(b).
7. The pull-down resistance is R/4 +R/(4/3) = R, so the gate still offers the
same driver as a unit inverter. However, the capacitance on input A is
only 10/3, so the logical effort is 10/9.
8. This is better than 4/3, which is normally associated with a NAND gate.
9. In the limit of an infinitely large reset transistor and unit-sized nMOS
transistor for input A, the logical effort approaches 1, just like an inverter.
10. The improvement in logical effort of input A comes at the cost of much higher effort on
the reset input. Note that the pMOS transistor on the reset input is also shrunk.
11. This reduces its diffusion capacitance and parasitic delay at the expense of slower
response to reset.
12. For asymmetric gates, the equivalent width is that of the inner (narrower)
transistor. The equivalent length increases by the sum of the reciprocals of the
relative widths.
13. In other circuits such as arbiters, we may wish to build gates that are perfectly
symmetric
14. so neither input is favored. Figure 9.8 shows how to construct a symmetric
NAND gate.
Skewed Gates
1. In other cases, one input transition is more important than the other.
2. HI-skew gates to favor the rising output transition and LO-skew gates to favor the falling
output transition.
3. This favoring can be done by decreasing the size of the noncritical transistor.
4. The logical efforts for the rising (up) and falling (down) transitions are called gu and
gd, respectively, and are the ratio of the input capacitance of the skewed gate to the
input capacitance of an unskewed inverter with equal drive for that transition.
5. Figure 9.9(a) shows how a HI-skew inverter is constructed by downsizing the nMOS
transistor.
6. This maintains the same effective resistance for the critical transition while reducing the
input capacitance relative to the unskewed inverter of Figure 9.9(b), thus reducing the
logical effort on that critical transition to gu=2.5/3 = 5/6.
7. Of course, the improvement comes at the expense of the effort on the non-critical
transition.
8. The logical effort for the falling transition is estimated by comparing the inverter to a
smaller unskewed inverter with equal pull-down current, shown in Figure 9.9(c), giving a
logical effort of gd= 2.5/1.5 = 5/3.
9. The degree of skewing (e.g.,the ratio of effective resistance for the fast transition relative
to the slow transition) impacts the logical efforts and noise margins; a factor of two is
common.
10. Figure 9.10 catalogs HI-skew and LO-skew gates with a skew factor of two. Skewed
gates are sometimes denoted with an H or an L on their symbol in a schematic.
 11. Alternating HI-skew and LO-skew gates can be used when only one transition is
important. Skewed gates work particularly well with dynamic circuits.
Write a short note on P/N ratio circuits.
P/N Ratios
1. Notice in Figure 9.10 that the average logical effort of the LO-skew NOR 2 is actually
better than that of the unskewed gate.
2. The pMOS transistors in the unskewed gate are enormous in order to provide equal rise
delay. They contribute input capacitance for both transitions, while only helping the
rising delay.
3. By accepting a slower rise delay, the pMOS transistors can be downsized to reduce input
capacitance and average delay significantly.
4. For processes with a mobility ratio of n/ p = 2 as we have generally been assuming, the
best ratios are shown in Figure 9.11.
 5. Reducing the pMOS size from 2 to for the inverter gives the theoretical fastest average
delay, but this delay improvement is only 3%.
6. However, this significantly reduces the pMOS transistor area. It also reduces input
capacitance, which in turn reduces power consumption.
7. Excessively slow rising outputs can also cause hot electron degradation and reducing the
pMOS size.

Multiple Threshold Voltages:

1. Some CMOS processes offer two or more threshold voltages.
2. Transistors with lower threshold voltages produce more ON current, but also leak
exponentially more OFF current.
3. Libraries can provide both high- and low-threshold versions of gates.
4. The low-threshold gates can be used sparingly to reduce
the delay of critical paths.
5. Skewed gates can use low-threshold devices on only the
critical network of transistors.

Write a short note on P/N ratio circuits.

Ratioed Circuits

1. Ratioed logic is an attempt to reduce the number of transistors required to implement

a given logic function, at the cost of reduced robustness and extra power dissipation.
2. The purpose of the PUN (Pull-up Network) in complementary CMOS is to provide a
conditional path between VDD and the output when the PDN (Pull-down network) is
turned off.
3. In ratioed logic, the entire PUN is replaced with a single unconditional load device that
pulls up the output for a high output in Figure(a).
4. Instead of a combination of active pull-down and pull-up networks, such a gate consists
of an NMOS pull-down network that realizes the logic function, and a simple load device.
5. Figure(b) shows an example of ratioed logic, which uses a grounded PMOS load and is
referred to as a pseudo-NMOS gate.
6. The clear advantage of pseudo-NMOS is the reduced number of transistors.
 7. The nominal high output voltage (VOH) for this gate is VDD since the pull-down devices are
turned off when the output is pulled high(assuming that VOLis below VTn).
8. On the other hand, the nominal low output voltage is not 0 V since there is a fight
between the devices in the PDN and the grounded PMOS load device.
9. This results in reduced noise margins and more importantly static power dissipation.
10. The sizing of the load device relative to the pull-down devices can be used to trade-off
parameters such a noise margin, propagation delay and power dissipation.
11. Since the voltage swing on the output and the overall functionality of the gate depends
upon the ratio between the NMOS and PMOS sizes, the circuit is called ratioed.
12. This is in contrast to the ratioless logic styles, such as complementary CMOS, where the
low and high levels do not depend upon transistor sizes.
Ganged CMOS
1. When one input is “0” and the other ‘1’, the gate can be viewed as a pseudo-nMOS circuit
.
2. When both inputs are ‘0’, both pMOS transistors are ON, pulling the output high faster
than ordinary pseudo-nMOS.
3. When both inputs are ‘1’ , both pMOS transistors are OFF,saving static power dissipation.
4. Hence, the symmetric NOR achieves both better performance and lower power dissipation
than a 2- input pseudo- nMOS NOR.

Source Follower Pull- up Logic (SFPL)

1. It is similar to a pseudo nMOS except that the pull-up is controlled by the inputs.
2. N6 – N9 and P1 form a pseudo-nMOS NOR function.
3. The gate of the pull-up P1 is driven by a parallel source follower consisting of
drive transistors N1-N4 and load transistor Nload .
4. When one input turns on, the source follower pulls node x to approximately V DD
/2.
5. This tends to partially turn off P1, which allows smaller nMOS pulldown N6-N9
to be used.
6. N1 – N4 also load the input.
7. SFPL is primarily applicable to constructing
wide NOR gates.
Differential Cascode Voltage Switch Logic (DCVSL)
1. It is possible to create a ratioed logic style that completely eliminates static currents and
provides rail-
to-rail swing. Such a gate combines two concepts: differential logic and positive
feedback.
2. A differential gate requires that each input is provided in complementary format, and
produces complementary outputs in turn. The feedback mechanism ensures that
the load device is turned off when not needed.
3. A example of such a logic family, called Differential Cascode Voltage Switch Logic (or
DCVSL), is presented conceptually in Fig(a).

4. The pull-down networks PDN1 and PDN2 use NMOS devices and are mutually exclusive
(this is, when PDN1 conducts, PDN2 is off, and when PDN1 is off, PDN2 conducts),
such that the required logic function and its inverse are simultaneously implemented.
5. Assume now that, for a given set of inputs, PDN1 conducts while PDN2 does not, and

that Out and are initially high and low, respectively. Turning on PDN1, causes Out to

be pulled down, although there is still a fight between M1 and PDN1.

is in a high impedance state, as M2 and PDN2 are both turned off.

6.
7. This in turn enables Out to discharge all the way to GND.
8. Figure (b) shows an example of an XOR/XNOR gate. Notice that it is possible to share
transistors among the two pull-down networks, which reduces the implementation
overhead.
9. The resulting circuit exhibits a rail-to-rail swing, and the static power dissipation is
eliminated: in steady state, none of the stacked pull-down networks and load devices are
simultaneously conducting.
10. However, the circuit is still ratioed since the sizing of the PMOS devices relative to the
pull-down devices is critical to functionality, not just performance.
11. In addition to the problem of increase complexity in design, this circuit style still has a
power-dissipation problem that is due to cross-over currents.
12. During the transition, there is a period of time when PMOS and PDN are turned on
simultaneously, producing a short circuit path.
Dynamic Circuits
 Ratioed circuits reduce the input capacitance by replacing the pMOS transistors
connected to the inputs with a single resistive pull-up.
 The drawbacks of ratioed circuits include slow rising transitions, contention on the falling
transitions, static power dissipation, and a nonzero VOL.
 Dynamic circuits circumvent these drawbacks by using a clocked pull-up transistor rather
than a pMOS that is always ON.
 Figure 9.21 compares (a) static CMOS, (b) pseudo-nMOS, and (c) dynamic inverters.

 Dynamic circuit operation is divided into two modes, as shown in Figure 9.22.
1. During precharge, the clock is 0, so the clocked pMOS is ON and initializes the
output Y high.
2. During evaluation, the clock is 1 and the clocked pMOS turns OFF.
 The output may remain high or may be discharged low through the pull-down network.
 Dynamic circuits are the fastest commonly used circuit family because they have lower
input capacitance and no contention during switching.
 They also have zero static power dissipation. However, they require careful clocking,
consume significant dynamic power, and are sensitive to noise during evaluation.
 In Figure 9.21(c), if the input A is 1 during precharge, contention will take place because
both the pMOS and nMOS transistors will be ON.
 When the input cannot be guaranteed to be 0 during precharge, an extra clocked
evaluation transistor can be added to the bottom of the nMOS stack to avoid contention
as shown in Figure 9.23.
 The extra transistor is sometimes called a foot. Figure 9.24 shows generic footed and
unfooted gates.
Domino Logic
 A Domino logic module consists of an n-type dynamic logic block followed by a
static inverter (Figure 6.65).
 During precharge, the output of the n-type dynamic gate is charged up to VDD, and the
output of the inverter is set to 0.
 During evaluation, the dynamic gate conditionally discharges, and the output of the
inverter makes a conditional transition from 0 1. If one assumes that all the inputs
of a Domino gate are outputs of other Domino gates3, then it is ensured that all inputs
are set to 0 at the end of the precharge phase, and that the only transitions during
evaluation are 0 1 transitions.
 Consider now the operation of a chain of Domino gates. During precharge, all inputs
are set to 0. During evaluation, the output of the first Domino block either stays at 0
or makes a 0 1 transition, affecting the second gate. This effect might ripple
through the whole chain, one after the other, similar to a line of falling dominoes—
hence the name.

Domino CMOS has the following properties:


Since each dynamic gate has a static inverter, only non-inverting logic can be
implemented. Although there are ways to deal with this, as is discussed in a
subsequent section, this is major limiting factor, and pure Domino design has become
rare.
 Very high speeds can be achieved: only a rising edge delay exists, while tpHL equals
zero. The inverter can be sized to match the fan-out, which is already much smaller
than in the complimentary static CMOS case, as only a single gate capacitance has to
be accounted for per fan-out gate.
np-CMOS
 The Domino logic presented in the previous section has the disadvantage that each
dynamic gate requires an extra static inverter in the critical path to make the circuit
functional.
 np-CMOS, provides an alternate approach to cascading dynamic logic by using two
flavors (n-tree and p-tree) of dynamic logic. In a p-tree logic gate, PMOS devices are
 used to build a pull-up logic network, including a PMOS evaluation transistor (Figure
6.71)
 The NMOS predischarge transistor drives the output low during precharge. The
output conditionally makes a 0 to 1 transition during evaluation depending on its
inputs.
 np-CMOS logic exploits the duality between n-
tree and p-tree logic gates to eliminate the
cascading problem. If the n-tree gates are
controlled by CLK, and p-tree gates are controlled
using CLK, n-tree gates can directly drive p-tree
gates, and vice-versa.
 Similar to Domino, n-tree outputs must go through
an inverter when connecting to another n-tree gate.
 During the precharge phase (CLK = 0), the output
of the n-tree gate, Out1, is charged to VDD, while
the output of the p-tree gate, Out2, is pre-
discharged to 0V. Since the n-tree gate connects
PMOS pull-up devices, the PUN of the p-tree is turned off at that time.
 During evaluation, the output of the n-tree gate can only make a 1 to 0 transition,
conditionally turning on some transistors in the p-tree. This ensures that no accidental
discharge of Out2 can occur.
 Similarly, n-tree blocks can follow p-tree gates without any problems, as the inputs to
the n-gate are precharged to 0.
 A disadvantage of the np-CMOS logic style is that the p-tree blocks are slower than
the n-tree modules, due to the lower current drive of the PMOS transistors in the logic
network. Equalizing the propagation delays requires extra area.

Explain the concept of Transistor Scaling.

 As transistors become smaller, they switch faster, dissipate less power, and are
cheaper to manufacture.
 However, scaling also worsen reliability issues, increases complexity, and
introduces new problems.
 Designers need to be able to predict the effect of this feature size scaling on chip
performance to plan future products, ensure existing products will scale
gracefully to future processes for cost reduction, and anticipate looming design
challenges.
 Dennard’s Scaling Law predicts that the basic operational characteristics of a
MOS transistor can be preserved and the performance improved if the critical
parameters of a device are scaled by a dimensionless factor S.
  These parameters include the following:
1. All dimensions (in the x, y, and z directions)
2. Device voltages
3. Doping concentration densities
 This approach is also called constant field scaling because the electric fields
remain the same as both voltage and distance shrink. In contrast, constant
voltage scaling shrinks the devices but not the power supply.
 Another approach is lateral scaling, in which only the gate length is scaled. This
is commonly called a gate shrink because it can be done easily to an existing
mask database for a design.
 This constant voltage scaling offered quadratic delay improvement as well as
cost reduction. It also maintained continuity in I/O voltage standards.
 Constant voltage scaling increased the electric fields in devices. By the 1 μm
generation, velocity saturation was severe enough that decreasing feature size
no longer improved device current.
 Device breakdown from the high field was another risk. And power consumption
became unacceptable. Therefore, Dennard scaling has been the rule since the
half-micron node.

Interconnect Scaling

 Wires also tend to be scaled equally in width and thickness to maintain an aspect
ratio close to 2.1 Table 7.5 shows the resistance, capacitance, and delay per unit
length.
 Wires can be classified as local, semiglobal, and global. Local wires run within
functional units and use the bottom layers of metal. Semiglobal (or scaled ) wires
run across larger blocks or cores, typically using middle layers of metal.
 Both local and semiglobal wires scale with feature size. Global wires run across
the entire chip using upper levels of metal. For example, global wires might
connect cores to a shared cache.
 Global wires do not scale with feature size; indeed, they may get longer (by a
factor of Dc , on the order of 1.1) because die size has been gradually increasing.
 Most local wires are short enough that their resistance does not matter. Like
gates, their capacitance per unit length is remaining constant, so their delay is
improving just like gates.
 Semiglobal wires long enough to require repeaters are speeding up, but not as
fast as gates. This is a relatively minor problem.
 Global wires, even with optimal repeaters, are getting slower as technology
scales. The time to cross a chip in a nanometer process can be multiple cycles,
and this delay must be accounted for in the microarchitecture.
 Observe that when wire thickness is scaled, the capacitance per unit length
remains constant. Hence, a reasonable initial estimate of the capacitance of a
minimum-pitch wire is about 0.2 fF/􀁒m, independent of the process.
 In other words, wire capacitance is roughly 1/5 of gate capacitance per unit
length.
To accommodate the three models ,two scaling factors – 1/ α and 1/β are used.
1/β – scaling factor for VDD and gate oxide thickness D.
1/α – used for all other linear dimensions, both horizontal and vertical chip surface.
For the constant field model and constant voltage model, β= α and β = 1 are applied.
1. Gate Area Ag :
Ag = L.W
Both are scaled by 1/α, Ag = 1/α2
2. Gate capacitance per unit area C0 or Cox.

3.Gate Capacitance Cg :

4.Parasitic Capacitance Cx:

5.Carrier density in channel Qon :

6.Channel Resistance Ron :

7.Gate delay Td :

8.Maximum operating frequency f0 :

9.Saturation Current Idss :

10.Current density J:

So, J is scaled by
1/α2 β
11. Switching energy per gate Eg :

12. Power dissipation per gate Pg :

 13. Power dissipation per unit area Pa :

14.Power speed product PT :

Explain the static and dynamic power dissipation in CMOS circuits with necessary diagrams
and expression.
OR
List out different methods of reducing i)Static power dissipation in CMOS circuits(8)
ii)Dynamic power dissipation in CMOS circuits
Power Dissipation:
 Static CMOS gates are very power-efficient because they dissipate nearly zero power
while idle.
 For much of the history of CMOS design, power was a secondary consideration
behind speed and area for many chips.
 As transistor counts and clock frequency have increased, power consumption has
increased and now is a primary constraint.
 Power dissipation in CMOS circuits comes from two components:
Static dissipation due to
1. Subthreshold conduction through OFF transistors
2.Tunneling current through gate oxide
 3.Leakage through reverse-biased diodes
4.Contention current in ratioed circuits
Dynamic dissipation due to
1.Charging and discharging of load capacitances
2.“short-circuit” current while both pMOS and nMOS networks are partially ON
3. Ptotal = Pstatic + Pdynamic

Static Dissipation
 Considering the static CMOS inverter as shown in Fig. If the input = “0”, the
associated nMOS transistor is OFF and the pMOS transistor is ON. The output
voltage is VDD or logic ‘1’.
 When the input = “1”, the associated nMOS transistor is ON and the pMOS transistor
is OFF. The output voltage is logic ‘0’(GND).
 Since one of the transistor is always OFF, ideally, no current flows through the OFF
transistor. So the power dissipation is zero, when the circuit is quiescent.
 However, secondary effects including sub-threshold conduction, tunneling, and
leakage lead to small amounts of static current flowing through the OFF transistor.
 The static power dissipation is the product of total leakage current and
the supply voltage.
Pstatic = Istatic . VDD
Dynamic Dissipation:
 The primary dynamic dissipation component is charging the load
capacitance.
 Suppose a load ‘C’ is switched between GND and VDD at an average
frequency fsw.
 Over any interval of time T, the load will be charged and discharged T.fsw times.
 Current flows from VDD to the load to charge it. Current then flows from the load to
GND during discharge.
 In one complete charge/discharge cycle, a total charge of Q = C VDD is thus
transferred from VDD to current.
 The average dynamic power dissipation is

Short – circuit Dissipation:

The short-circuit power dissipation is given by
Psc = Imean . VDD
From the fig.

Assume that Vtn = - Vtp and βn = βp(=β) and that the behavior is symmetrical around t2.

With

6.4 Total Power Dissipation

1. Total power dissipation can be obtained from the sum of the three dissipation component,
so
Ptotal = Ps + Pd + Psc
2. To calculate the power dissipation for the complex circuits, Calculate the total capacitance
driven by gate outputs and to estimate the percentage activity of the circuit operating at
the maximum clock frequency,
Pd = percentage – activity x CTotal VDD2 / tp
3. Partition the circuit into smaller parts where the activity factor may be calculated more
accurately and repeat the above calculation.
4.For the switch level circuit, Pd = CTOTAL- SWITCHED . VDD2 / TOTAL-NUMBER OF CYCLES x
tp