ISA Memory Instructions

CS353 – Computer Architecture

Najeeb-Ur-Rehman
Assistant Professor
Department of Computer Science
Faculty of Computing & IT
University of Gujrat
1
 Memory Addressing
 How do we specify memory addresses?
 This issue is independent of type of ISA
(they all need to address memory)

 We need to specify
 (1) Operand sizes
 (2) Address alignment
 (3) Byte ordering for multi-byte operands
 (4) Addressing Modes

2
 Operand Sizes
 Byte (8 bits), half-word (16 bits), word (32 bits),
double word (64 bits)
 An ISA may (and typically does) support
multiple operand sizes
 Instruction must specify the operand size
 E.g. LOAD.b R1,A vs. LOAD.w R1,A
 Why? Make sure there’s no “garbage data”
 But usually there is a “default” size
 Most commonly “word” on 32-bit machines

3
 Alignment
 For multi-byte memory operands

 An aligned address for an n-byte operand is an

address that is a multiple of n
 Word-aligned: 0, 4, 8, 12, etc.

 An ISA can require alignment of operands

 MIPS: all memory operands must be aligned

4
More Notes about Memory Alignment
 MIPS requires that all words start at byte addresses that
are multiples of 4 bytes
Last hex digit
0 1 2 3
of address is:
Aligned 0, 4, 8, or Chex
Not 1, 5, 9, or Dhex
Aligned 2, 6, A, or Ehex
3, 7, B, or Fhex

• Called Alignment: objects fall on address that is

multiple of their size.
5
 Byte Ordering (“Endianness”)
 Layout of multi-byte operands in memory

 Little endian (x86)

 Least significant byte at lowest address in
memory
 Big endian (most other ISAs)
 Most significant byte at lowest address in
memory
 Some ISAs support both byte ordering
 E.g. MIPS has a Big-endian mode

6
 Another view of Endianness
 No, we’re not making this up.
 at word address 100 (assume a 4-byte word)
long a = 11223344;
 big-endian (MSB at word address) layout
100 101 102 103
100 11 22 33 44

 little-endian (LSB at word address) layout

103 102 101 100
11 22 33 44 100

7
 Addressing Modes
 What is the location of an operand?

 Three basic possibilities

 Register: operand is in a register
 Register number encoded in the instruction
 Immediate: operand is a constant
 Constant encoded in the instruction
 Memory: operand is in memory
 Many address modes possibilities

8
 MIPS Memory
 MIPS memory organized as 32-bit word
 Byte Addressing
 Alignment Restriction
 Big Endian

1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte

4 8 16
3 6 12
2 4 8
1 2 4
0 0 0

9
 Load from Memory Instruction
 lw register, constant (register)
 Memory address = constant + register
 Memory address = offset + Base
Register
 lw $s1, 2($s2)
 C code: g = h + A[8];
 MIPs code: lw $t0, 32($s3)
add $s1, $s2, $t0
10
 Store to Memory Instruction
 sw register, constant (register)
 Memory address = constant + register
 Memory address = offset + Base
Register
 sw $s1, 2($s2)
 C code: A[12] = h + A[8];
 MIPs code: lw $t0, 32($s3)
add $t0, $s2, $t0
11 sw $t0, 48($s3)
 Variable Array Index
 C Code: g = h + A[i];
 g, h, i variables in registers $s1, $s2,
$s4
 Base address in register $s3
 MIP Code: add $t1, $s4, $s4
add $t1, $t1, $t1
add $t1, $t1, $s3
lw $t0, 0($t1)
12 add $s1, $s2, $t0
 Pointers v. Values

 Key Concept: A register can hold any 32-bit value.

That value can be a (signed) int, an unsigned
int, a pointer (memory address), and so on
 If you write add $t2,$t1,$t0
then $t0 and $t1 better contain values
 If you write lw $t2,0($t0)
then $t0 better contain a pointer
 Don’t mix these up!

13
 §2.5 Representing Instructions in the Computer
Representing Instructions
 Instructions are encoded in binary
 Called machine code
 MIPS instructions
 Encoded as 32-bit instruction words
 Small number of formats encoding operation code
(opcode), register numbers, …
 Regularity!
 Register numbers
 $t0 – $t7 are reg’s 8 – 15
 $t8 – $t9 are reg’s 24 – 25
 $s0 – $s7 are reg’s 16 – 23
14
 Instruction Format
 MIP Instructions are 32-bit
 Field: Segment of instruction
 Opcode (operation code) field: 6 bits
 rs (register source) field: 5 bits
 rt (register source) field: 5 bits
 rd (register destination) field: 5 bits
 shamt (shift amount) field: 5 bits
 funct (function) field: 6 bits
15
 R-format Example
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

add $t0, $s1, $s2

special $s1 $s2 $t0 0 add

0 17 18 8 0 32

000000 10001 10010 01000 00000 100000

000000100011001001000000001000002 = 0232402016

16
 Instruction Format
 add $t0, $s1, $s2
 000000 10001 10010 01000 00000
100000
 Opcode rs rt rd shamt funct
 Registers $s0 - $s7 (16-23)
 Registers $t0 - $t7(08-15)
 Remaining registers discussed latter

17
 MIPS I-format Instructions
op rs rt constant or address
6 bits 5 bits 5 bits 16 bits

 Immediate arithmetic and load/store instructions

 rt: destination or source register number
 Constant: –215 to +215 – 1
 Address: offset added to base address in rs
 Design Principle 4: Good design demands good
compromises
 Different formats complicate decoding, but allow 32-bit
instructions uniformly
 Keep formats as similar as possible

18
 Instruction Format
 Should all MIP instructions be of the
same format?
 lw $t0, 32($s3)
 Could specify constant using the 5-bit
rt field?
 Design Principle 3:
 Good Design demands good
compromises

19
 MIP Instruction Formats
 R-format
 I-format
 used by data transfer instructions
 Opcode 6-bit
 rs 5-bit
 rt 5-bit
 address 16-bit
 +/- 215 bytes or 213 words

20
 Instruction Format
 Multiple formats complicate
hardware
 Complexity reduced by keeping
formats similar
 R-format & I-format first three fields
same
 Address field spans over three fields
 Opcode differentiates between formats

21
 Instruction Format

Instruction Format op rs rt rd shamt funct

add R 0 reg reg reg 0 32

sub R 0 reg reg reg 0 34

lw I 35 reg reg address

sw I 43 reg reg address

22
Instruction Format
 A[300] = h + A[300]; $t1=A, $s2=h
 lw $t0, 1200($t1)
add $t0, $s2, $t0
sw $t0, 1200($t1)

op rs rt rd shamt funct
100011 01001 01000 0000 0100 1011 0000
000000 10010 01000 01000 00000 100000
101011 01001 01000 0000 0100 1011 0000
23
 Registers vs. Memory
 Registers are faster to access than memory
 Operating on memory data requires loads and
stores
 More instructions to be executed
 Compiler must use registers for variables as
much as possible
 Only spill to memory for less frequently used
variables
 Register optimization is important!

24
 Immediate Operands
 Constant data specified in an instruction
addi $s3, $s3, 4
 No subtract immediate instruction
 Just use a negative constant
addi $s2, $s1, -1
 Design Principle 3: Make the common case fast
 Small constants are common
 Immediate operand avoids a load instruction

25
 So Far...
 All instructions so far only manipulate
data…we’ve built a calculator of sorts.
 In order to build a computer, we need
ability to make decisions…
 C (and MIPS) provide labels to support
“goto” jumps to places in code.
 C: Horrible style; MIPS: Necessary!

26
 Home Reading @ Review

27
 §2.4 Signed and Unsigned Numbers
Unsigned Binary Integers
 Given an n-bit number

n1 n2
x  xn12  x n2 2    x12  x 0 2
1 0

 Range: 0 to +2n – 1
 Example
 0000 0000 0000 0000 0000 0000 0000 10112
= 0 + … + 1×23 + 0×22 +1×21 +1×20
= 0 + … + 8 + 0 + 2 + 1 = 1110
 Using 32 bits
 0 to +4,294,967,295
28
 2s-Complement Signed Integers
 Given an n-bit number

n1 n2
x  xn12  x n 2 2    x12  x 0 2
1 0

 Range: –2n – 1 to +2n – 1 – 1

 Example
 1111 1111 1111 1111 1111 1111 1111 11002
= –1×231 + 1×230 + … + 1×22 +0×21 +0×20
= –2,147,483,648 + 2,147,483,644 = –410
 Using 32 bits
 –2,147,483,648 to +2,147,483,647
29
 2s-Complement Signed Integers

 Bit 31 is sign bit

 1 for negative numbers
 0 for non-negative numbers
 –(–2n – 1) can’t be represented
 Non-negative numbers have the same
unsigned and 2s-complement representation
 Some specific numbers
 0: 0000 0000 … 0000
 –1: 1111 1111 … 1111
 Most-negative: 1000 0000 … 0000
 Most-positive: 0111 1111 … 1111

30
 Signed Negation
 Complement and add 1
 Complement means 1 → 0, 0 → 1

x  x  1111...1112  1

x  1  x

 Example: negate +2
 +2 = 0000 0000 … 00102
 –2 = 1111 1111 … 11012 + 1
= 1111 1111 … 11102
31
 Sign Extension
 Representing a number using more bits
 Preserve the numeric value
 In MIPS instruction set
 addi: extend immediate value
 lb, lh: extend loaded byte/halfword
 beq, bne: extend the displacement
 Replicate the sign bit to the left
 c.f. unsigned values: extend with 0s
 Examples: 8-bit to 16-bit
 +2: 0000 0010 => 0000 0000 0000 0010
 –2: 1111 1110 => 1111 1111 1111 1110

32