Lab title:

Design and implementation 8-bit Conditional Sum Adder.

Learning Objective:
In this lab the student would learn how to implement and simulate a Verilog Hdl module for a 8 bit
conditional sum adder circuit. Instantiating modules within the modules, learning about the effect of gate
delays on the result of a circuit using the Modelsim software. Calculating an approx. delay of the circuit.

Literature Background:
Students are required to have the knowledge of
• Conditional adder circuit.
• It’s working.
• Maximum delay calculation for the circuit.
• Gate level Verilog Hdl code for modules inside the main carry look ahead module.
• Instantiation of modules according to the circuit diagram in Verilog Hdl.

Procedure:
• First of all labeled circuit diagrams are needed.(which in this case is 8bit Conditional sum adder)
• Truth table for the circuit’s.(for 6-8 test cases)
• Verilog code for all internal modules of 8 bit conditional sum adder circuit (It should be according to
the labeling of the diagram).
• Verilog code for 8bit conditional sum adder module and test bench.
• Use 15 time unit’s delay i.e., #15in test bench in default case.
• Take at least 6-8 test cases for each simulation.
• Take at least one case in which you think that maximum delay would occur.

Task#1: Simulate the module 8 bit conditional sum adder in Modelsim and verify the functionality of
the circuit by comparing it’s output wave forms with the truth table.

Task#2: Once the modules have been verified now add one time unit delay #1 in each gate of the circuit’s.
The delay of #15 time unit’s in test bench should not be changed. Simulate the modules again.

Task#3: Keeping the #15 delay in test bench now change the #1 delay introduced in task #2, to 3 time unit
delays i.e., #3. Again run the simulation and read the wave forms.
Circuit Diagram:

Figure 1: Conditional Cell.

Figure 2: Conditional Sum Adder

Verilog code for all modules :

module ha
(
input wire a,b,
output wire s,c
);
xor x1(s,a,b);
and a1(c,a,b);
endmodule
//Module CC1
module CCo
(
input wire A,B,
output wire [1:0]S,C
);
xor x2(S[0],A,B);
and a2(C[0],A,B);
or o1(C[1],A,B);
not n1(S[1],S[0]);
endmodule

module onebitmux
(
input wire I0,I1,sel,
output wire f0
);
wire w1,w2,w3;
not n1(w1,sel);
and a1(w2,I0,w1);
and a2(w3,I1,sel);
or b3(f0,w3,w2);
endmodule

module twobitsmux
(
input wire [1:0]I0,I1,
input wire sel,
output wire [1:0]f0
);
onebitmux mux1(.I0(I0[0]),.I1(I1[0]),.sel(sel),.f0(f0[0]));
onebitmux mux2(.I0(I0[1]),.I1(I1[1]),.sel(sel),.f0(f0[1]));
endmodule

module threebitsmux
(
input wire [2:0]I0,I1,
input wire sel,
output wire [2:0]f0
);
onebitmux k1(.I0(I0[0]),.I1(I1[0]),.sel(sel),.f0(f0[0]));
onebitmux k2(.I0(I0[1]),.I1(I1[1]),.sel(sel),.f0(f0[1]));
onebitmux k3(.I0(I0[2]),.I1(I1[2]),.sel(sel),.f0(f0[2]));
endmodule

module fivebitsmux
(
input wire [4:0]I0,I1,
input wire sel,
output wire [4:0]f0
);
onebitmux v1(.I0(I0[0]),.I1(I1[0]),.sel(sel),.f0(f0[0]));
onebitmux v2(.I0(I0[1]),.I1(I1[1]),.sel(sel),.f0(f0[1]));
onebitmux v3(.I0(I0[2]),.I1(I1[2]),.sel(sel),.f0(f0[2]));
onebitmux v4(.I0(I0[3]),.I1(I1[3]),.sel(sel),.f0(f0[3]));
onebitmux v5(.I0(I0[4]),.I1(I1[4]),.sel(sel),.f0(f0[4]));
endmodule
module con_sum
(
input wire [7:0]A,B,
output wire [7:0]S,
output wire Cout
);
wire [7:0]S0,C0;
wire [7:1]S1,C1;
wire [0:6]M,M0;
wire YC;
wire [3:0]Y;
wire [5:0]X;
wire [3:1]XC;

ha h2(.s(S0[0]),.c(C0[0]),.a(A[0]),.b(B[0]));
CCo g1(.S({S0[1],S1[1]}),.C({C0[1],C1[1]}),.A(A[1]),.B(B[1]));
CCo g2(.S({S0[2],S1[2]}),.C({C0[2],C1[2]}),.A(A[2]),.B(B[2]));
CCo g3(.S({S0[3],S1[3]}),.C({C0[3],C1[3]}),.A(A[3]),.B(B[3]));
CCo g4(.S({S0[4],S1[4]}),.C({C0[4],C1[4]}),.A(A[4]),.B(B[4]));
CCo g5(.S({S0[5],S1[5]}),.C({C0[5],C1[5]}),.A(A[5]),.B(B[5]));
CCo g6(.S({S0[6],S1[6]}),.C({C0[6],C1[6]}),.A(A[6]),.B(B[6]));
CCo g7(.S({S0[7],S1[7]}),.C({C0[7],C1[7]}),.A(A[7]),.B(B[7]));

twobitsmux h1(.f0({M[0],M0[0]}),.I0({S0[1],C0[1]}),.I1({S1[1],C1[1]}),.sel(C0[0]));
twobitsmux h9(.f0({M[1],M0[1]}),.I0({S0[3],C0[3]}),.I1({S1[3],C1[3]}),.sel(C0[2]));
twobitsmux h4(.f0({M[4],M0[4]}),.I0({S0[3],C0[3]}),.I1({S1[3],C1[3]}),.sel(C1[2]));
twobitsmux h3(.f0({M[2],M0[2]}),.I0({S0[5],C0[5]}),.I1({S1[5],C1[5]}),.sel(C0[4]));
twobitsmux h5(.f0({M[5],M0[5]}),.I0({S0[5],C0[5]}),.I1({S1[5],C1[5]}),.sel(C1[4]));
twobitsmux h6(.f0({M[3],M0[3]}),.I0({S0[7],C0[7]}),.I1({S1[7],C1[7]}),.sel(C0[6]));
twobitsmux h7(.f0({M[6],M0[6]}),.I0({S0[7],C0[7]}),.I1({S1[7],C1[7]}),.sel(C1[6]));
threebitsmux j1(.f0({X[0],X[1],XC[1]}),.I0({S0[2],M[1],M0[1]}),.I1({S1[2],M[4],M0[4]}),.sel(M0[0]));
threebitsmux j2(.f0({X[2],X[3],XC[2]}),.I0({S0[6],M[3],M0[3]}),.I1({S1[6],M[6],M0[5]}),.sel(M0[2]));
threebitsmux j3(.f0({X[4],X[5],XC[3]}),.I0({S0[6],M[3],M0[3]}),.I1({S1[6],M[6],M0[5]}),.sel(M0[5]));

fivebitsmux
j4(.f0({Y[0],Y[1],Y[2],Y[3],YC}),.I0({S0[4],M[2],X[2],X[3],XC[2]}),.I1({S1[4],M[2],X[4],X[5],XC[3]
}),.sel(XC[1]));

assign S[0]=S0[0];
assign S[1]=M[0];
assign S[2]=X[0];
assign S[3]=X[1];
assign S[4]=Y[0];
assign S[5]=Y[1];
assign S[6]=Y[2];
assign S[7]=Y[3];
assign Cout=YC;
endmodule

module tb_Con_sum;
reg [7:0]in1,in2;
wire [7:0]S_out;
wire C_out;
con_sum CSA01(.S(S_out),.Cout(C_out),.A(in1),.B(in2));
initial
begin
in1=8'b11100111;in2=8'b11010110;
#15 in1=8'b00101011;in2=8'b00000001;
#15 in1=8'b00111011;in2=8'b11111100;
#15 in1=8'b11101000;in2=8'b11101001;
#15 in1=8'b10010110;in2=8'b00111010;
#15$stop;
end
endmodule
With one units delay of 8bits conditional sum adder:
module ha_d1
(
input wire a,b,
output wire s,c
);
xor #1 x1(s,a,b);
and #1 a1(c,a,b);
endmodule
//Module CC1
module CCo_d1
(
input wire A,B,
output wire [1:0]S,C
);
xor #1 x2(S[0],A,B);
and #1 a2(C[0],A,B);
or #1 o1(C[1],A,B);
not #1 n1(S[1],S[0]);
endmodule

module onebitmux_d1
(
input wire I0,I1,sel,
output wire f0
);
wire w1,w2,w3;
not #1 n1(w1,sel);
and #1 a1(w2,I0,w1);
and #1 a2(w3,I1,sel);
or #1 b3(f0,w3,w2);
endmodule

module twobitsmux_d1
(
input wire [1:0]I0,I1,
input wire sel,
output wire [1:0]f0
);
onebitmux_d1 mux1(.I0(I0[0]),.I1(I1[0]),.sel(sel),.f0(f0[0]));
onebitmux_d1 mux2(.I0(I0[1]),.I1(I1[1]),.sel(sel),.f0(f0[1]));
endmodule

module threebitsmux_d1
(
input wire [2:0]I0,I1,
input wire sel,
output wire [2:0]f0
);
onebitmux_d1 k1(.I0(I0[0]),.I1(I1[0]),.sel(sel),.f0(f0[0]));
onebitmux_d1 k2(.I0(I0[1]),.I1(I1[1]),.sel(sel),.f0(f0[1]));
onebitmux_d1 k3(.I0(I0[2]),.I1(I1[2]),.sel(sel),.f0(f0[2]));
endmodule
module fivebitsmux_d1
(
input wire [4:0]I0,I1,
input wire sel,
output wire [4:0]f0
);
onebitmux_d1 v1(.I0(I0[0]),.I1(I1[0]),.sel(sel),.f0(f0[0]));
onebitmux_d1 v2(.I0(I0[1]),.I1(I1[1]),.sel(sel),.f0(f0[1]));
onebitmux_d1 v3(.I0(I0[2]),.I1(I1[2]),.sel(sel),.f0(f0[2]));
onebitmux_d1 v4(.I0(I0[3]),.I1(I1[3]),.sel(sel),.f0(f0[3]));
onebitmux_d1 v5(.I0(I0[4]),.I1(I1[4]),.sel(sel),.f0(f0[4]));
endmodule

module con_sum
(
input wire [7:0]A,B,
output wire [7:0]S,
output wire Cout
);
wire [7:0]S0,C0;
wire [7:1]S1,C1;
wire [0:6]M,M0;
wire YC;
wire [3:0]Y;
wire [5:0]X;
wire [3:1]XC;

ha_d1 h2(.s(S0[0]),.c(C0[0]),.a(A[0]),.b(B[0]));
CCo_d1 g1(.S({S0[1],S1[1]}),.C({C0[1],C1[1]}),.A(A[1]),.B(B[1]));
CCo_d1 g2(.S({S0[2],S1[2]}),.C({C0[2],C1[2]}),.A(A[2]),.B(B[2]));
CCo_d1 g3(.S({S0[3],S1[3]}),.C({C0[3],C1[3]}),.A(A[3]),.B(B[3]));
CCo_d1 g4(.S({S0[4],S1[4]}),.C({C0[4],C1[4]}),.A(A[4]),.B(B[4]));
CCo_d1 g5(.S({S0[5],S1[5]}),.C({C0[5],C1[5]}),.A(A[5]),.B(B[5]));
CCo_d1 g6(.S({S0[6],S1[6]}),.C({C0[6],C1[6]}),.A(A[6]),.B(B[6]));
CCo_d1 g7(.S({S0[7],S1[7]}),.C({C0[7],C1[7]}),.A(A[7]),.B(B[7]));

twobitsmux_d1 h1(.f0({M[0],M0[0]}),.I0({S0[1],C0[1]}),.I1({S1[1],C1[1]}),.sel(C0[0]));
twobitsmux_d1 h9(.f0({M[1],M0[1]}),.I0({S0[3],C0[3]}),.I1({S1[3],C1[3]}),.sel(C0[2]));
twobitsmux_d1 h4(.f0({M[4],M0[4]}),.I0({S0[3],C0[3]}),.I1({S1[3],C1[3]}),.sel(C1[2]));
twobitsmux_d1 h3(.f0({M[2],M0[2]}),.I0({S0[5],C0[5]}),.I1({S1[5],C1[5]}),.sel(C0[4]));
twobitsmux_d1 h5(.f0({M[5],M0[5]}),.I0({S0[5],C0[5]}),.I1({S1[5],C1[5]}),.sel(C1[4]));
twobitsmux_d1 h6(.f0({M[3],M0[3]}),.I0({S0[7],C0[7]}),.I1({S1[7],C1[7]}),.sel(C0[6]));
twobitsmux_d1 h7(.f0({M[6],M0[6]}),.I0({S0[7],C0[7]}),.I1({S1[7],C1[7]}),.sel(C1[6]));

threebitsmux_d1
j1(.f0({X[0],X[1],XC[1]}),.I0({S0[2],M[1],M0[1]}),.I1({S1[2],M[4],M0[4]}),.sel(M0[0]));
threebitsmux_d1
j2(.f0({X[2],X[3],XC[2]}),.I0({S0[6],M[3],M0[3]}),.I1({S1[6],M[6],M0[5]}),.sel(M0[2]));
threebitsmux_d1
j3(.f0({X[4],X[5],XC[3]}),.I0({S0[6],M[3],M0[3]}),.I1({S1[6],M[6],M0[5]}),.sel(M0[5]));

fivebitsmux_d1
j4(.f0({Y[0],Y[1],Y[2],Y[3],YC}),.I0({S0[4],M[2],X[2],X[3],XC[2]}),.I1({S1[4],M[2],X[4],X[5],XC[3]
}),.sel(XC[1]));
]));

With three units delay of 8bits conditional sum adder:

module ha_d3
(
input wire a,b,
output wire s,c
);
xor #3 x1(s,a,b);
and #3 a1(c,a,b);
endmodule
//Module CC1
module CCo_d3
(
input wire A,B,
output wire [1:0]S,C
);
xor #3 x2(S[0],A,B);
and #3 a2(C[0],A,B);
or #3 o1(C[1],A,B);
not #3 n1(S[1],S[0]);
endmodule

module onebitmux_d3
(
input wire I0,I1,sel,
output wire f0
);
wire w1,w2,w3;
not #3 n1(w1,sel);
and #3 a1(w2,I0,w1);
and #3 a2(w3,I1,sel);
or #3 b3(f0,w3,w2);
endmodule

module twobitsmux_d3
(
input wire [1:0]I0,I1,
input wire sel,
output wire [1:0]f0
);
onebitmux_d3 mux1(.I0(I0[0]),.I1(I1[0]),.sel(sel),.f0(f0[0]));
onebitmux_d3 mux2(.I0(I0[1]),.I1(I1[1]),.sel(sel),.f0(f0[1]));
endmodule

module threebitsmux_d3
(
input wire [2:0]I0,I1,
input wire sel,
output wire [2:0]f0
);
onebitmux_d3 k1(.I0(I0[0]),.I1(I1[0]),.sel(sel),.f0(f0[0]));
onebitmux_d3 k2(.I0(I0[1]),.I1(I1[1]),.sel(sel),.f0(f0[1]));
onebitmux_d3 k3(.I0(I0[2]),.I1(I1[2]),.sel(sel),.f0(f0[2]));
endmodule

module fivebitsmux_d3
(
input wire [4:0]I0,I1,
input wire sel,
output wire [4:0]f0
);
onebitmux_d3 v1(.I0(I0[0]),.I1(I1[0]),.sel(sel),.f0(f0[0]));
onebitmux_d3 v2(.I0(I0[1]),.I1(I1[1]),.sel(sel),.f0(f0[1]));
onebitmux_d3 v3(.I0(I0[2]),.I1(I1[2]),.sel(sel),.f0(f0[2]));
onebitmux_d3 v4(.I0(I0[3]),.I1(I1[3]),.sel(sel),.f0(f0[3]));
onebitmux_d3 v5(.I0(I0[4]),.I1(I1[4]),.sel(sel),.f0(f0[4]));
endmodule

module con_sum
(
input wire [7:0]A,B,
output wire [7:0]S,
output wire Cout
);
wire [7:0]S0,C0;
wire [7:1]S1,C1;
wire [0:6]M,M0;
wire YC;
wire [3:0]Y;
wire [5:0]X;
wire [3:1]XC;

ha_d3 h2(.s(S0[0]),.c(C0[0]),.a(A[0]),.b(B[0]));
CCo_d3 g1(.S({S0[1],S1[1]}),.C({C0[1],C1[1]}),.A(A[1]),.B(B[1]));
CCo_d3 g2(.S({S0[2],S1[2]}),.C({C0[2],C1[2]}),.A(A[2]),.B(B[2]));
CCo_d3 g3(.S({S0[3],S1[3]}),.C({C0[3],C1[3]}),.A(A[3]),.B(B[3]));
CCo_d3 g4(.S({S0[4],S1[4]}),.C({C0[4],C1[4]}),.A(A[4]),.B(B[4]));
CCo_d3 g5(.S({S0[5],S1[5]}),.C({C0[5],C1[5]}),.A(A[5]),.B(B[5]));
CCo_d3 g6(.S({S0[6],S1[6]}),.C({C0[6],C1[6]}),.A(A[6]),.B(B[6]));
CCo_d3 g7(.S({S0[7],S1[7]}),.C({C0[7],C1[7]}),.A(A[7]),.B(B[7]));

twobitsmux_d3 h1(.f0({M[0],M0[0]}),.I0({S0[1],C0[1]}),.I1({S1[1],C1[1]}),.sel(C0[0]));
twobitsmux_d3 h9(.f0({M[1],M0[1]}),.I0({S0[3],C0[3]}),.I1({S1[3],C1[3]}),.sel(C0[2]));
twobitsmux_d3 h4(.f0({M[4],M0[4]}),.I0({S0[3],C0[3]}),.I1({S1[3],C1[3]}),.sel(C1[2]));
twobitsmux_d3 h3(.f0({M[2],M0[2]}),.I0({S0[5],C0[5]}),.I1({S1[5],C1[5]}),.sel(C0[4]));
twobitsmux_d3 h5(.f0({M[5],M0[5]}),.I0({S0[5],C0[5]}),.I1({S1[5],C1[5]}),.sel(C1[4]));
twobitsmux_d3 h6(.f0({M[3],M0[3]}),.I0({S0[7],C0[7]}),.I1({S1[7],C1[7]}),.sel(C0[6]));
twobitsmux_d3 h7(.f0({M[6],M0[6]}),.I0({S0[7],C0[7]}),.I1({S1[7],C1[7]}),.sel(C1[6]));

threebitsmux_d3
j1(.f0({X[0],X[1],XC[1]}),.I0({S0[2],M[1],M0[1]}),.I1({S1[2],M[4],M0[4]}),.sel(M0[0]));
threebitsmux_d3
j2(.f0({X[2],X[3],XC[2]}),.I0({S0[6],M[3],M0[3]}),.I1({S1[6],M[6],M0[5]}),.sel(M0[2]));
threebitsmux_d3
j3(.f0({X[4],X[5],XC[3]}),.I0({S0[6],M[3],M0[3]}),.I1({S1[6],M[6],M0[5]}),.sel(M0[5]));

fivebitsmux_d3
j4(.f0({Y[0],Y[1],Y[2],Y[3],YC}),.I0({S0[4],M[2],X[2],X[3],XC[2]}),.I1({S1[4],M[2],X[4],X[5],XC[3]
}),.sel(XC[1]));

Results:

Figure 3: 8bit Conditional Sum Adder Simulation Results for #0 delay.

Figure 4: 8bit Conditional Sum Adder Simulation Results for #1 delay.

 Figure 5: 8bit Conditional Sum Adder Simulation Results for #3 delay.

Q/A:

Q.# 01. Compare it with ripple carry adder, carry select adder and carry look ahead adder in terms of
hardware and speed.
A: 8bit ripple carry adder has area of 40 gates, 8bit carry select adder has area of 120 gates, 8bit carry
lookahead adder has area of 57 gates and conditional sum adder has area of 114 gates. In terms of area
conditional sum adder lies at 3rd best position.
8bit ripple carry adder has delay of 17 gates, 8bit carry select adder has delay of 15 gates, 8bit carry
lookahead adder has delays of 7 gates and conditional sum adder has delays of 11 gates. In terms of speed
conditional sum adder 2nd fastest adder.

Q.#02. When the delay of #1 is introduced in the module under test how the result is changed and why is it
changed. What are we trying to get by introducing #1 delay.
A: Before introducing #1 delay we were getting output instantaneously. After introducing #1 delay we were
getting output delayed by 7 time units. In theory, the maximum delay is 11 time units. By introducing the
#1 delay we are try to evaluate how fast or slow our circuit is. We suppose the delay of every gate is 1 time
unit than how many time units it takes to give valid output.
Q.#03. When the delay of #3 is introduced in the module under test how the result is changed and why is
it changed. Is it acceptable now? What changes we can introduce to get the right result as compared with
ripple carry adder, carry look ahead adder and carry select adder
A: After introducing #3 the result is changed to undefined value. Because in theory we have 3*11=33
maximum delay when we introduce #3 delay. Since we are having output after every #15 time units
therefore we are not getting valid output. Hence the result is unacceptable for #3 delay. If we want to have
valid result than we should change the simulation delay between inputs from #15 to #33 time units or more.
In order to have valid results, I have changed simulation delay to #35 time units.
Conclusion:
In this lab I have learned how to model circuit using Verilog HDL in modalism software. I have also learned
how can we instantiate existing code module to reduce over coding. I have understood the effect of gate
delay in digital circuit.