Testbench and Pattern

NCTU-EE IC LAB Spring-2022

Lecturer: Yu-Wei Lu
ICLAB NCTU Institute of Electronics 1
 Outline

Section 1- Introduction to Verification

Section 2- Pattern

Section 3- Testbench

Section 4- Environment

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 Outline

Section 1- Introduction to Verification

Section 2- Pattern

Section 3- Testbench

Section 4- Environment

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 What is Verification?
Verification == Bug Hunting
A process in which a design is verified against a given design specification
before tape out
Verification include:
Functionality (Main goal !!)
Performance
Power
Security
Safety

How to perform the verification?

Simulation of RTL design model (Lab03)
Formal verification (Bonus Lab @ 2022/5/11)
Power-aware simulations (Lab08)
Emulation/FPGA prototyping
Static and dynamic timing checks

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 Introduction to Verification
Stages of verification
Preliminary verification -> Specification (ex. Output = 0 after rst)
Broad-spectrum verification -> Test pattern (ex. Random test)
Corner-case verification -> Special test pattern (ex. Boundary)

Steps of verification
Generate stimulus
Apply stimulus to DUT (Design Under Test)
Capture the response
Check for correctness
Measure progress against overall verification goal

Stimulus DUT Checker

Data flow

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 The Verilog Design Environment
TESTBED.v (./00_TESTBED)
Connecting testbench and design modules
Dump waveform

DESIGN.v (./01_RTL)
Design under test (DUT)

PATTERN.v (./00_TESTBED)
Pattern TESTBED.v
Test program

DESIGN.v PATTERN.v
(module) (module)

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 Outline

Section 1- Introduction to Verification

Section 2- Pattern

Section 3- Testbench

Section 4- Environment

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 Pattern
Two kinds of strategies Feature
Directed Testing -> Check what you know Bug
Random Testing -
New area
Test

Directed Testing Random Testing

C C

C C C C

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 Pattern
Time consuming v.s. coverage

100%
Random
Coverage

test
Directed
test

Time

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 Pattern
Which one to use?

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 Pattern
Elements of pattern file
Generate stimulus PATTERN.v
File I/O
Procedural Blocks Port declaration
Display information
Control flow
for, while, repeat, if, case, forever Data type declaration
Task and Function

Generate stimulus

Check result

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 Generate Stimulus
Using Verilog random system task
$random(seed);
Return 32-bit signed value
Seed is optional
$urandom(seed);
Return 32-bit unsigned value
Seed is optional
$urandom_range(int unsigned MAX, int unsigned MIN=0);
Return value inside range

Using high level language with file IO

Generate random stimulus from MATLAB or Python etc. and output
the stimulus into files.
Read the files in pattern.v

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 Generate Stimulus
A simple example

integer SEED,number; integer SEED,number;

SEED = 123; SEED = 123;
number = $random(SEED) % 7; number = $urandom(SEED) % 7;

integer SEED; integer SEED;

reg[3:0] number; reg[3:0] number;
SEED = 123; SEED = 123;
number = $random(SEED); number = $random(SEED) % 7;
number = number % 7;

integer SEED;
reg[3:0] number;
SEED = 123; Same ?
number = $random(SEED) % ;

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 Generate Stimulus
A simple example
Produce random number in 0~6
May be negative Correct
integer SEED,number; integer SEED,number;
1 SEED = 123; SEED = 123; 2
number = $random(SEED) % 7; number = $urandom(SEED) % 7;

signed signed signed signed unsigned signed

(signed operation) (unsigned operation)

Correct The value may not in range 0~6

integer SEED;
reg[3:0] number; integer SEED;
3 SEED = 123; reg[3:0] number;
4
unsigned number = $random(SEED); SEED = 123;
number = number % 7; number = $random(SEED) % 7;

unsigned unsigned signed unsigned signed signed

(unsigned operation) (signed operation)

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 Generate Stimulus
A simple example
Produce random number in 0~6

Correct
5

integer SEED;
reg[3:0] number;
SEED = 123;
number = $random(SEED) % ;

unsigned signed unsigned

(unsigned operation)

The key point is to use unsigned operation!

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 File I/O
Open file
$fopen opens the specified file and returns a 32-bit descriptor.
file_descriptor = $fopen file_name
file_descriptor: bit 32 always be set (=1), remaining bits hold a small
number indicating what file is opened.

file = $fopen("
file2 = $fopen
file3 = $fopen

multi_channel_descriptor = $fopen file_name

Multi_channel_descriptor: bit 32 always be clear (=0), bit 0 represent
standard output, each remaining bit represents a single output channel.

file = $fopen
file2 = $fopen
file3 = $fopen

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 File I/O
Close file
$fclose system task closes the channels specified in the
multichannel descriptor
$fclose(<multichannel_descriptor>);
The $fopen task will reuse channels that have been closed

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 File Input
Read data from specific file
$fgetc reading a byte at a time
c = $fgetc(<descriptor>);
$fgets reading a line at a time
i = $fgets(string, <descriptor>);
$fscanf reading formatted data
i = $fscanf signal,signal

$readmemb, $readmemh
$readmemb("file_name", memory_name [ , start_address [ , end_address ]] );
$readmemh("file_name", memory_name [ , start_address [ , end_address ]] );

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 File Input
A simple example for readmemb
@002 @002
11111111 01010101 11111111_01010101
00000000 10101010 00000000_10101010
@006 @006
1111zzzz 00001111 1111zzzz_00001111

reg [7:0] meme[0:7]; reg [15:0] meme[0:7];

$readmemb ); $readmemb );

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 File Output
Display tasks that writes to specific files
$fdisplay, $fwrite, $fstrobe, $fmonitor
$fdisplay format_specifiers argument_list>);
$fwrite format_specifiers argument_list>);
$fstrobe format_specifiers argument_list>);
$fmonitor format_specifiers argument_list>);

All these four output system tasks support multiple bases

$fdisplay /$fdisplayh /$fdisplayb /$fdisplayo
$fwrite /$fwriteh /$fwriteb /$fwriteo
$fstrobe /$fstrobeh /$fstrobeb /$fstrobeo
$fmonitor /$fmonitorh /$fmonitorb /$fmonitoro

Appendix

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 Appendix-Stratified Event Queue
Stratified Event Queue of Verilog

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 Display Information
There are mainly four kinds of instruction to display
information.
$display: automatically prints a new line to the end of its output
format_specifiers argument_list>);

$write: identical to $display, except that it does not print a newline

character
format_specifiers argument_list>);

$strobe: identical to $display, except that the argument evaluation is

delayed just prior to the advance of simulation time
format_specifiers argument_list>);

$monitor: continuously monitors the variables in the parameter list

format_specifiers argument_list>);

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 Display Information (cont.)
The following escape sequences are used for display
special characters
\n New line character \

\t Tab character \o A character specified in 1-3 octal digits

\\ \ character %% Percent character

The following table shows the escape sequences used for

format specifications
specifier Display format specifier Display format
%h or %H Hexadecimal %m or %M Hierarchical name
%d or %D Decimal %s or %S String
%o or %O Octal %t or %T Current time
%b or %B Binary %e or %E real number in exponential
%c or %C ASCII character %f or %F Real number in decimal
%v or %V Net signal strength %p or %P Array <only for System Verilog>

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 Display Information
More detail
http://verilog.renerta.com/source/vrg00013.htm
http://www.cnblogs.com/oomusou/archive/2011/06/25/verilog_stro
be.html

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 File I/O
Example

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 Procedural Blocks
All procedural blocks will be executed concurrently.
Initial Blocks
Only be executed once

initial
begin

end

Always Blocks
Will be executed if the condition is met

always@(condition_expression)
begin

end

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 Procedural Blocks
A simple example
module Test (OUT, A, B, SEL);
output A,B,SEL;
input OUT; Port declaration
A
initial OUT
begin B
A=0;B=0;SEL=0;
Delay and timing #10 A=0;B=1;SEL=1;
#10 A=1;B=0;
#10 SEL=0; SEL
#10 $finish; End simulation!
end
endmodule
A

If simulation never stop, check B

1.
2. Have combinational loop in design SEL
3. Have loop in pattern
10 10 10

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 Task and Function

To break up a task into smaller, more manageable ones, and

encapsulate reusable code, you can either divide your code into
modules, or you can use tasks and functions.

Task
A task is typically used to perform debugging operations, or to
behaviorally describe hardware.

Function
A function is typically used to perform a computation, or to represent
combinational logics.

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 Tasks and Functions
Task
Tasks may execute in non-zero simulation time
Can have timing controls (#delay, @, wait).
Can have port arguments (input, output, and inout) or none.
Can enable task or function.
Does not return a value.
Not synthesizable

Function
always execute in 0 simulation time

Has only input arguments and no output port

Returns a single value through the function name.

Can call it from a procedural block

Synthesizable

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 Tasks

Simplified Syntax

task identifier;
parameter_declaration;
input_decleration;
output_decleration;
inout_declaration;
register_declaration;

begin
statement;

end
endtask

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 Tasks

An example of using a task

Task can take, drive and source global variables, when no local
variables are used.

temp_in = 30; temp_in = 30;

convert(temp_in, temp_out); convert;
temp_in,temp_out); $display("%d,%d",temp_in,temp_out);

task convert; task convert;

input [7:0] temp_in; begin
output [7:0] temp_out; temp_in = 20;
begin temp_out = (9/5)*(temp_in+32);
temp_in = 20; end
temp_out = (9/5)*(temp_in+32); endtask
end
endtask

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 Tasks
How to use task in Pattern

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 Functions

Simplified Syntax

function type_or_range identifier;

parameter_declaration;
input_decleration;
register_declaration;

begin
statement;

end
endfunction

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 Functions

An example of using a function

Although the function cannot contain timing, you can call it from a
procedural block that does.

always@(posedge CLK)
sum = add(a,b);

function [7:0] add;

input [7:0] a;
input [7:0] b;
begin
add = a + b;
end
endfunction

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 Coding Note
Some note about coding
Input delay
Asynchronous reset and clock
Check output data

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 Input Delay
Consider the input interface
Input signals should be synchronous to either positive clock edge or
negative clock edge with specified input delays to avoid timing violation
Assign input delays by absolute delay value
Example: `timescale 1ns/10ps
4ns
parameter INDLY = 1;
bit IN1; CLK
initial begin
@(posedge CLK) #INDLY IN1 = 1;
@(posedge CLK) #INDLY IN1 = 0; IN1
end

Assign input delays by relative delay value (relative to clock period)

Example: `timescale 1ns/10ps
parameter CYCLE = 4.0; 4ns
bit IN1;
initial begin CLK
@(negedge CLK) IN1 = 1;
@(negedge CLK) IN1 = 0;
end IN1

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 Asynchronous Reset and Clock
Asynchronous reset:
Reset signal will reset all registers on the falling edge of reset signal.

Clock signal
Clock signal should be forced to 0 before reset signal is given.
Using always procedure to produce a duty cycle 50% clock signal
Example:
reg clk, rst_n;
real CYCLE = 2.5;
initial clk = 0;
always #(CYCLE/2.0) clk = ~clk;
initial begin
rst_n
force clk =0;
#(0.5); rst_n
#(10); rst_n
#(3); release clk;
end

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 Check output data
When to check the output data of design
Check output data when out_valid is high
Example

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 Outline

Section 1- Introduction to Verification

Section 2- Pattern

Section 3- Testbench

Section 4- Environment

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 Testbench
Encapsulate DESIGN.v and PATTERN.v to be a top
verification file
Key element
Timescale
Dump Waveform
Port Connection

TESTBED.v

DESIGN.v PATTERN.v
(module) (module)

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 Timescale

A compiler directive
Specifies the unit of measurement for time and the degree of
precision of the time
Syntax:

`timescale <time_unit> / <time_precision>

time_unit specifies the unit of measurement for times and delays

time_precision specifies the degree of precision
The time_precision must be at least as precise as the time_unit
Valid integers are 1, 10, and 100
Valid character strings are s, ms, us, ns, ps, and fs

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 Timescale
A simple example:
`timescale 1ns/100ps
module TEST; CYCLE/2.0 = 1.25 ns
parameter CYCLE = 2.5; Precision requirement: 0.01ns < 100ps
reg CLK; Precision loss !! The CYCLE/2.0 will
initial CLK = 1; become 1.3ns
always #(CYCLE/2.0) CLK = ~CLK;
endmodule

Unit/Precision Delay Time Delay

10ns/1ns #5 50ns
10ns/1ns #5.738 57ns
10ns/10ns #5.5 60ns
10ns/100ps #5.738 57.4ns

Note: if you use memory in your design, you should set timescale according to the
timescale specified by memory file

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 Dump Waveform
There are many different waveform file formats.
Value Change Dump (.VCD)
Included in Verilog HDL IEEE Standard
Wave Log File (.wlf)
Mentor Graphics Modelsim
SHM (.shm)
Cadence NC Verilog / Simvision
VPD (.vpd)
Synopsys - VCS
Fast Signal DataBase (.fsdb)
Spring Soft (Merged with Synopsys) - Debussy/Verdi

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 Dump Waveform
Command often used
$fsdbDumpfile(fsdb_name[,limit_size])
fsdb_name: assign waveform file name
(Optional) limit_size: assign the limitation of file size

$fsdbDumpvars
depth: level of waveform to be dumped
instance: module to be dumped
mda

$sdf_annotate sdf_file config_file][,log_file][,mtm_spec][,s

cale_factors][,scale_type])

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 Dump Waveform
Parameters of $fsdbDumpvars()
Depth
0: all signals in all scopes
1: all signals in current scope (scope of TESTBED.v)
2: all signals in the current scope and all scopes one level below
n: all signals in the current scope and all scopes n-1 levels below

Option
IO_only port signals will be dumped.
Reg_only only reg type signals will be dumped.

union and packed structure signals in all scopes specified in $fsdbDumpvars.

mda
scopes specified in $fsdbDumpvars.
For further information, please refer
http://www.eetop.cn/blog/html/55/1518355-433686.html

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 Dump Waveform
A simple example:
Used in RTL simulation or gate-level simulation
Dump wave form in fsdb format for viewing in nWave
Include timing information in the simulation

initial begin
`ifdef RTL
$fsdbDumpfile Design.fsdb");
$fsdbDumpvars(0,"+mda");
`endif
`ifdef GATE
$fsdbDumpfile Design_SYN.fsdb");
$fsdbDumpvars(0,"+mda");
$sdf_annotate("CORE_SYN.sdf",dut);
`endif
end

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 Port Connection
The input and output is reverse between design.v and
pattern.v.
A simple example:
TESTBED.v
//input signals
wire clk, rst_n, in;
//output signals
wire out; clk
rst_n
DESIGN U_DESIGN( DESIGN.v PATTERN.v
.in(in)
(module) in (module)
.rst_n(rst_n)
.clk(clk) out
.out(out)
)
PATTERN U_PATTERN(
.in(in)
.rst_n(rst_n)
.clk(clk)
.out(out)
)
endmodule

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 Outline

Section 1- Introduction to Verification

Section 2- Pattern

Section 3- Testbench

Section 4- Environment

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 Simulation environment
00_TESTBED
Pattern and testbench location.

01_RTL
RTL code functionality simulation

02_SYN
Circuit synthesize

03_GATE
Gate level simulation

04_MEM
05_APR
06_POST
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 00_TESTBED & 01_RTL
00_TESTBED:
TESTBED.v
PATTERN.v

01_RTL:
DESIGN.v
01_run: irun TESTBED.v -define RTL -debug
Link:
PATTERN.v & TESTBED.v

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 02_SYN & 03_GATE
02_SYN:
syn.tcl
01_run_dc: dc_shell
Generate file:
DESIGN_SYN.v & DESIGN_SYN.sdf

03_GATE:
01_run:
Link:
DESIGN_SYN.v & DESIGN_SYN.sdf

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After receiving Exercise PDF
Spend some time understanding the problem
Write some input/output by hand
To make sure you fully understand the problem

Before writing the design

Write high level language random stimulus generator
Think how to write the design when writing stimulus generator
Finish PATTERN & TESTBED
Reference Lab01/Lab02 PATTERN & TESTBED

When writing the design

Make sure your algorithm is correct before coding
Keep track of every hardware and its area and timing overhead
Use directed test to help writing the design

When writing the design

Random test & corner case test & optimization

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 Appendix-Stratified Event Queue

Result

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