Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-1

LECTURE 09 – LARGE SIGNAL MOSFET MODEL

LECTURE ORGANIZATION
Outline
• Introduction to modeling
• Operation of the MOS transistor
• Simple large signal model (SAH model)
• Subthreshold model
• Short channel, strong inversion model
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
Pages 68-76 and 96-98

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-2

INTRODUCTION TO MODELING
Models Suitable for Understanding Analog Design
The model required for analog design with CMOS technology is one that leads to
understanding and insight as distinguished from accuracy.
Technology
Understanding
and Usage

Updating Model Thinking Model Updating Technology

Simple,
±10% to ±50% accuracy

Comparison of Design Decisions- Extraction of Simple

simulation with "What can I change to Model Parameters
expectations accomplish ....?" from Computer Models
Expectations
"Ballpark"
Computer Simulation

Refined and
optimized
design Fig.3.0-02

This lecture is devoted to the simple model suitable for design not using simulation.

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-3

Categorization of Electrical Models

Time Dependence
Time Independent Time Dependent

Linear Small-signal, midband Small-signal frequency

Rin, Av, Rout response-poles and zeros
Linearity (.AC)
(.TF)

Nonlinear DC operating point Large-signal transient

iD = f(vD,vG,vS,vB) response - Slew rate
(.OP) (.TRAN)

Based on the simulation capabilities of SPICE.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-4

OPERATION OF THE MOS TRANSISTOR

Formation of the Channel for an Enhancement MOS Transistor
Subthreshold (VG<VT)
VB = 0 VS = 0 VG < VT VD = 0

Polysilicon

p+ n+ n+

p- substrate Depletion Region

Threshold (VG=VT)
VB = 0 VS = 0 VG =VT VD = 0

Polysilicon

p+ n+ n+

p- substrate Inverted Region

Strong Threshold (VG>VT)

VB = 0 VS = 0 VG >VT VD = 0

Polysilicon

p+ n+ n+

p- substrate Inverted Region

Fig.3.1-02

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-5

Transconductance Characteristics of an Enhancement NMOS when VDS = 0.1V

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-6

Output Characteristics of an Enhancement NMOS Transistor for VGS = 2VT

VDS=0:
VB = 0 VS = 0 vG =2VT VD = 0V iD
iD
Polysilicon VGS = 2VT

p+ n+ n+

p- substrate Inverted Region

0 vDS
VDS=0.5VT:
0 0.5VT VT
VB = 0 VS = 0 VG = 2VT VD = 0.5VT iD
iD
Polysilicon VGS = 2VT

p+ n+ n+

p- substrate Channel current

0 vDS
0 0.5VT VT
VDS=VT:
VB = 0 VS = 0 VG = 2VT VD =VT iD
iD VGS = 2VT
Polysilicon

p+ n+ n+
A depletion region
p- substrate
forms between the drain and channel 0 vDS
0 0.5VT VT Fig.3.1-04

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-7

Output Characteristics of an Enhancement NMOS when vDS = 2VT

VGS=VT:
VB = 0 VS = 0 vG =VT VD = 2VT iD
iD
Polysilicon

p+ n+ n+

p- substrate VGS =VT

0 vDS
0 VT 2VT 3VT
VGS=2VT:
VB = 0 VS = 0 VG = 2VT VD = 2VT iD
iD
Polysilicon
VGS =2VT
p+ n+ n+

p- substrate
0 vDS
0 VT 2VT 3VT
VGS=3VT:
VB = 0 VS = 0 VG = 3VT VD = 2VT iD
VGS =3VT
iD
Polysilicon

p+ n+ n+
Further increase in
p- substrate
VG will cause the FET to become active 0 vDS
0 VT 2VT 3VT
Fig.3.1-05

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-8

Output Characteristics of an Enhancement NMOS Transistor

2000
VGS = 3.0

1500

VGS = 2.5

iD(mA) 1000

VGS = 2.0
500
VGS = 1.5

VGS = 1.0
0
0 1 2 3 4 5
vDS (Volts)
SPICE Input File: Fig. 3.1-6
Output Characteristics for NMOS M5 6 5 0 0 MOS1 w=5u l=1.0u
M1 6 1 0 0 MOS1 w=5u l=1.0u VGS5 5 0 3.0
VGS1 1 0 1.0 VDS 6 0 5
M2 6 2 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VGS2 2 0 1.5 +gamma=0.4 lambda=.04 phi=.7)
M3 6 3 0 0 MOS1 w=5u l=1.0u .dc vds 0 5 .2
VGS3 3 0 2.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 6 4 0 0 MOS1 w=5u l=1.0u ID(M5)
VGS4 4 0 2.5 .end

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-9

Transconductance Characteristics of an Enhancement NMOS Transistor

6000
VDS = 5V
5000
VDS = 4V
VDS = 3V
4000
iD(mA)
3000
VDS = 2V
2000
VDS = 1V
1000

0
0 1 2 3 4 5
vGS (Volts) Fig. 3.1-7
SPICE Input File:
Transconductance Characteristics for NMOS M5 5 6 0 0 MOS1 w=5u l=1.0u
M1 1 6 0 0 MOS1 w=5u l=1.0u VDS5 5 0 5.0
VDS1 1 0 1.0 VGS 6 0 5
M2 2 6 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VDS2 2 0 2.0 +gamma=0.4 lambda=.04 phi=.7)
M3 3 6 0 0 MOS1 w=5u l=1.0u .dc vgs 0 5 .2
VDS3 3 0 3.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 4 6 0 0 MOS1 w=5u l=1.0u ID(M5)
VDS4 4 0 4.0 .probe
.end

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-10

SIMPLE LARGE SIGNAL MODEL (SAH MODEL)

Large Signal Model Derivation +
vGS +
1.) Let the charge per unit area in the channel -
iD - vDS
inversion layer be
n+ n+
QI(y) = -Cox[vGS-v(y)-VT] (coul./cm2) v(y)
Source dy Drain
p- y
2.) Define sheet conductivity of the inversion 0 y y+dy L
layer per square as Fig.110-03
cm2coulombs amps 1
S = µoQI(y)  v·s  cm2  = volt =
  
   /sq.
3.) Ohm's Law for current in a sheet is
iD dv -iD -iDdy
JS = W = -SEy = -S dy → dv = dy = µ Q (y)W → iD dy = -WµoQI(y)dv
SW o I

4.) Integrating along the channel for 0 to L gives

L vDS vDS
 iDdy = - WµoQI(y)dv = WµoCox[vGS-v(y)-VT] dv

0 0 0
5.) Evaluating the limits gives
WµoCox  v2(y)vDS WµoCox  vDS2
2  0 →
iD = (vGS-VT)v(y) - iD = (vGS-VT)vDS -
L  L  2 
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-11

Saturation Voltage - VDS(sat) iD

vDS = vGS-VT
Interpretation of the large signal model:
Active Region Saturation Region

Increasing
values of vGS

vDS
Fig. 110-04
The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of
the inverted parabolas. vDS
diD µoCoxW
dvDS = [(vGS-VT) - vDS] = 0
L Cutoff Saturation Active
T
-V
vDS(sat) = vGS - VT S
vG
=
S
Useful definitions: vD
0 vGS
µoCoxW K’W 0 VT Fig. 3.2-4
= L =
L
Note that newest editions of Analysis and Design of Analog ICs, P.R. Gray et.al,
switches the definition for the active and saturation regions.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-12

The Simple Large Signal MOSFET Model

Regions of Operation of the MOS Transistor:
1.) Cutoff Region:
vGS - VT < 0
iD = 0
(Ignores subthreshold currents)
2.) Active Region Output Characteristics of the MOSFET:
0 < vDS < vGS - VT iD/ID0
vDS = vGS-VT
µoCoxW vGS-VT
1.0 = 1.0
iD = 2(v - V ) - v  v Active VGS0-VT
2L  GS T DS  DS Region Saturation Region
vGS-VT
0.75 = 0.867
VGS0-VT
Channel modulation effects
3.) Saturation Region vGS-VT
= 0.707
0.5 VGS0-VT
0 < vGS - VT < vDS vGS-VT
= 0.5
VGS0-VT
µoCoxW 0.25 vGS-VT
iD = v - V 2 Cutoff Region VGS0-VT
=0
2L  GS T
vDS
0
0 0.5 1.0 1.5 2.0 2.5 VGS0-VT
Fig. 110-05

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-13

Performance Limitations of the Simple Sah

25µA
It turns out, that if we compare
the Sah model to a more precise K’ = 44.8µA/V 2,
k = 0,
model (SPICE level 2) that the 20µA
VDS(sat) = 1.0V K’ = 44.8µA/V 2,
Sah model has issues with the k = 0.5,
“knee” area as shown. VDS(sat) = 1.0V
15µA
iD
SPICE Level 2 Model
10µA

K’ = 29.6µA/V 2,
5µA
k = 0,
VDS(sat) = 1.0V

0µA
0 0.2 0.4 0.6 0.8 1.0
vDS (volts) 140825-01

VGS = 2.0V, W/L = 100µm/100µm

This discrepancy is due to the fact that we assumed that the threshold, VT, was constant
over the channel.
If we let VT (y) = VT + kv(y) then the Sah model is exactly the same as the SPICE model.

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-14

Modification of the Previous Model to Include the Effects of vDS on VT

From the previous derivation:
L vDS vDS
  
i dy = - WµoQI(y)dv = WµoCox[vGS - v(y) -VT]dv
 D  
0 0 0
Assume that the threshold voltage varies across the channel in the following way:
VT(y) = VT + kv(y)
where VT is the value of VT the at the source end of the channel and k is a constant.
Integrating the above gives,
v
WµoCox  v(y)2 DS WµoCox  vDS2
iD = L (vGS-VT)v(y) - (1+k) 2  → iD = L (vGS-VT)vDS - (1+k) 2 
  0  

To find vDS(sat), set the diD/dvDS equal to zero and solve for vDS = vDS(sat),
vGS - VT
vDS(sat) =
1+k
Therefore, in the saturation region, the drain current is
WµoCox
iD = 2(1+k)L (vGS - VT)2
For k = 0.5 and K’ = 44.8µA/V2, excellent correlation is achieved with SPICE 2 as seen
on the previous slide.

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-15

Influence of vDS on the Output Characteristics

Channel modulation effect: VG > V T VD > VDS(sat)
As the value of vDS increases, the
B S
effective L decreases causing the
Depletion
current to increase. Polysilicon Region

p+ n+ n+
Illustration:
Leff

Note that Leff = L - Xd p- substrate Xd

Fig110-06
Therefore the model in saturation
becomes,
K’W diD K’W dLeff iD dXd
iD = 2L (vGS-VT) → dv = -
2
2
2
(vGS - VT) dv = L dv  iD
eff DS 2Leff DS eff DS
Therefore, a good approximation to the influence of vDS on iD is
diD K’W
iD  iD( = 0) + vDS = iD( = 0)(1 + vDS) = (vGS-VT)2(1+vDS)
dvDS 2L

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-16

Channel Length Modulation Parameter, 

Assume the MOS is transistor is saturated-
µCoxW
 iD = 2L (vGS - VT)2(1 + vDS)
Define iD(0) = iD when vDS = 0V.
µCoxW
 iD(0) = 2L (vGS- VT)2
Now,
iD = iD(0)[1 + vDS] = iD(0) + iD(0) vDS
Matching with y = mx + b gives the value of 

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-17

Influence of Channel Length on 

Note that the value of  varies with channel length, L. The data below is from a 0.25µm
CMOS technology.

Channel Length Modulation (V-1)

0.6
0.5

0.4
PMOS
0.3

0.2
NMOS
0.1
0
0 0.5 1 1.5 2 2.5
Channel Length (microns) Fig.130-6

Most analog designers stay away from minimum channel length to get better gains and
matching at the sacrifice of speed.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 09 – Large Signal MOSFET Model (5/14/18) VBS0 = 0V PageV09-18
GS

Influence of the Bulk Voltage on the Large Signal MOSFET Model Polysilic

The components of the threshold voltage VSB0 = 0: p+ n+

are: p- substrate
VT = Gate-bulk work function (MS) VBS1 > 0V VGS
+ voltage to change the surface
potential (-2F)
Polysilic

p+ n+
+ voltage to offset the channel-bulk VSB1 > 0:
VD > 0
depletion charge (-Qb/Cox) p- substrate

+ voltage to compensate the VSB2 >VSB1: VGS

undesired interface charge

(-Qss/Cox)
VSB2 >VSB1: n+
We know that
Qb =  2|F| - vBS
Therefore, as the bulk becomes more
reverse biased with respect to the
source, the threshold voltage must p+
060613-02
increase to offset the increased channel- p- substrate
bulk depletion charge.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-19

Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued
Bulk-Source (vBS) influence on the transconductance characteristics-

iD
Decreasing values
of bulk-source voltage

VBS = 0

ID
vDS > vGS-VT

VGS
vGS
VT0 VT1 VT2 VT3
060612-02

In general, the simple model incorporates the bulk effect into VT by the previously
developed relationship:

VT(vBS) = VT0 +  2|f| - vBS -  2|f|

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-20

Summary of the Simple Large Signal MOSFET Model D

N-channel reference convention: +
iD
G B
Non-saturation- v
+ + DS
WµoCox  vDS2 vGS vBS
iD =  
(v - VT)vDS - 2 (1 + vDS)
L  GS  - -
S Fig. 110-10
Saturation-
WµoCox vDS(sat)2 WµoCox
iD = (vGS-VT)vDS(sat)- (1+vDS)= (vGS-VT)2(1+vDS)
L  2  2L
where:
µo = zero field mobility (cm2/volt·sec)
Cox = gate oxide capacitance per unit area (F/cm2)
 = channel-length modulation parameter (volts-1) Terms in red are
VT = VT0 +  2|f| - vBS - 2|f| model parameters
VT0 = zero bias threshold voltage
 = bulk threshold parameter (volts0.5)
2|f| = strong inversion surface potential (volts)
For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert
the current.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-21

Silicon Constants

Constant Constant Description Value Units

Symbol
VG Silicon bandgap (27C) 1.205 V
k Boltzmann’s constant 1.381x10-23 J/K
ni Intrinsic carrier concentration (27C) 1.45x1010 cm-3
o Permittivity of free space 8.854x10-14 F/cm
si Permittivity of silicon 11.7 o F/cm
ox Permittivity of SiO2 3.9 o F/cm

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-22

MOSFET Parameters
Model Parameters for a Typical CMOS Bulk Process (0.25µm CMOS n-well):

Parameter Typical Parameter Value Units

Parameter Description
Symbol N-Channel P-Channel
VT0 Threshold Voltage 0.5± 0.15 -0.5 ± 0.15 V
(VBS = 0)
K' Transconductance Para- 120.0 ± 10% 25.0 ± 10% µA/V2
meter (in saturation)
 Bulk threshold 0.4 0.6 (V)1/2
parameter
 Channel length 0.32 (L=Lmin) 0.56 (L=Lmin) (V)-1
modulation parameter 0.06 (L ≥2Lmin) 0.08 (L ≥2Lmin)
2|F| Surface potential at 0.7 0.8 V
strong inversion

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-23

SUBTHRESHOLD MODEL
Large-Signal Model for Weak Inversion
The electrons in the substrate at the source side can be expressed as,
s 
np(0) = npoexpV 
 t
The electrons in the substrate at the drain side can be expressed as,
s-vDS
np(L) = npoexp V 
 t 
Therefore, the drain current due to diffusion is,
np(L)- np(0) W s    vDS
iD = qADn   = qXDnnpoexp  1 - exp- 
 L  L Vt   Vt  
where X is the thickness of the region in which iD flows.
In weak inversion, the changes in the surface potential, s are controlled by changes in
the gate-source voltage, vGS, through a voltage divider consisting of Cox and Cjs, the
depletion region capacitance. Poly
ds Cox 1 vGS vGS-VT Oxide Cox vGS
 dv = C + C = n → s = n + k1 = n + k2 Channel
GS ox js Dep. Cjs fs
where VT
k2 = k1 + n Substrate
060405-04
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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-24

Large-Signal Model for Weak Inversion – Continued

Substituting the above relationships back into the expression for iD gives,
W k2 vGS-VT  vDS
iD = L qXDnnpo expV exp nV 1 - exp- V 
 t  t   t 
Define It as
k2
It = qXDnnpo expV 
 t
to get,
W vGS-VT  vDS
iD = L It exp nV 1 - exp- V 
 t   t 
where n  1.5 – 3 iD
VGS=VT
If vDS > 0, then 1mA
W vGS-VT vDS
iD = It exp 1 + 
L  nV t  V A
VGS<VT
The boundary between nonsaturated and
saturated is found as,
Vov = VDS(sat) = VON = VGS -VT = 2nVt 0 vDS
0 1V
Fig. 140-03

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-25

SHORT CHANNEL, STRONG INVERSION MODEL

What is Velocity Saturation?

Electron Drift Velocity (m/s)

The most important short-channel 105
effect in MOSFETs is the velocity
saturation of carriers in the channel. 5x104
A plot of electron drift velocity
2x104
versus electric field is shown below.
104

5x103
An expression for the electron drift 105 106 107
velocity as a function of the electric Electric Field (V/m) Fig130-1
field is,
µnE
vd  1 + E/E
c
where
vd = electron drift velocity (m/s)
µn = low-field mobility ( 0.07m2/V·s)
Ec = critical electrical field at which velocity saturation occurs

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-26

Short-Channel Model Derivation

As before,
iD WQI(y)µnE  E
JD = JS = W = QI(y)vd(y) → iD = WQI(y)vd(y) = 1 + E/E → iD 1+ E  = WQI(y)µnE
c  c
Replacing E by dv/dy gives,
 1 dv dv
iD 1 + E dy= WQI(y)µndy
 c 
Integrating along the channel gives,
L
vDS
  1 dv
iD1 + E dydy = WQI(y)µndv
  c 
0
0
The result of this integration is,
µnCox W µnCox W
iD = 2
[2(vGS-VT)vDS-vDS ] =  2
 L [2(vGS-VT)vDS-vDS ]
 1 DSv  L 21 +  vDS

21 + E L 
 c 
where  = 1/(EcL) with dimensions of V-1.

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Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-27

Saturation Voltage
Differentiating iD with respect to vDS and setting equal to zero gives,
1 
  (VGS-VT) 
V’DS(sat) =  1 + 2(VGS-VT -1  (VGS-VT)1 -
 + ···
  
 2 
if
 (VGS-VT)
<1
2
Therefore,
  (VGS-VT) 

V’DS(sat)  VDS(sat) 1 - + ··· 
 2 
Note that the transistor will enter the saturation region for vDS < vGS - VT in the
presence of velocity saturation.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-28

Large Signal Model for the Saturation Region

To develop the large signal model, we will assume that
 (VGS-VT)
<1
2
so that we can substitute the less complex expression of
V’DS(sat)  (VGS-VT)
into the active region version of the model to get,
K’ W 2]
iD =  [2(v -V )(v -V )- (v -V )
21 +  (vGS - VT) L
 GS T GS T GS T

K’ W
= [ v - V ]2
2[1 + (vGS-VT)] L GS T
However, we continue to use the following to define when the MOSFET is in the
saturation region,
  (VGS-VT) 

vDS ≥ (VGS-VT) 1 - + ··· 
 2 

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-29

The Influence of Velocity Saturation on the Transconductance Characteristics

The following plot was made for K’ = 110µA/V2 and W/L = 1:

Note as the velocity saturation effect becomes stronger, that the drain current-gate
voltage relationship becomes linear.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-30

Circuit Model for Velocity Saturation

A simple circuit model to include the influence of velocity saturation is is shown:
We know that
K’W
iD = 2L (vGS’ -VT)2 and vGS = vGS’ + iD RSX
or
vGS’ = vGS - iDRXS
Substituting vGS’ into the current relationship gives,
K’W
iD = 2L (vGS - iDRSX -VT)2
Solving for iD results in,
K’ W 2
iD =   (v GS - V T)
W L
21 + K’ L RSX(vGS-VT)
 
Comparing with the previous result, we see that
W L 
 = K’ L RSX → RSX = K’W = E K’W
c
Therefore for K’ = 110µA/V2, W = 1µm and Ec = 1.5x106V/m, we get RSX = 6.06k.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-31

SUMMARY
• The modeling of this lecture is devoted to understanding how the circuit works
• The two primary current-voltage characteristics of the MOSFET are the
transconductance characteristic and the output characteristic
• The simple Sah large signal model is good enough for most applications and
technology
• The Sah model can be improved in the region of the knee and for the weak dependence
of drain current on drain-source voltage in the saturation region
• Most designers do not work at minimum channel length because of the channel length
modulation effect and because worse matching occurs for small areas
• The threshold voltage is increased as the bulk-source is reverse biased
• The subthreshold model accounts for very small currents that flow in the channel when
the gate-source voltage is smaller than the threshold voltage
• The subthreshold current is exponentially related to the gate-source voltage
• Velocity saturation occurs at minimum channel length and can be modeled by
including a source degeneration resistor with the simple large signal model

CMOS Analog Circuit Design © P.E. Allen - 2016