UNIT 3

THE PROGRAMMING MODEL

8086
➢ General Purpose Registers
➢ Segment Registers
➢ Flag Register
➢ Pointer and index Registers SP

BP
AX AH AL CS

SI
BX BH BL DS

CX DI
CH CL ES

DX DH DL SS Flag IP

General Purpose Segment Registers Flag Register Pointer and Index Registers

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REGISTERS ORGANISATION
▪ 16-Bit General Purpose Registers
– can access all 16-bits at once
– can access just high (H) byte, or low (L) byte

only the General

Purpose registers
allow access as
8-bit High/Low
sub-registers

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REGISTERS ORGANISATION (CONTINUED)
▪ Register Set
16-Bit Segment Addressing Registers
CS Code Segment

DS Data Segment

SS Stack Segment

ES Extra Segment

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REGISTERS ORGANISATION (CONTINUED)
16-Bit Offset Addressing Registers

SP Stack Pointer

BP Base Pointer

SI Source Index

DI Destination Index

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 REGISTERS ORGANISATION (CONTINUED)
16-Bit Control/Status Registers
- IP Instruction Pointer (Program Counter for execution control)
- FLAGS 16-bit register
• It is not a 16-bit value but it is a collection of 9 bit-flags
(six are unused)
• Flag is set when it is equal to 1
• Flag is clear when it is equal to 0

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GENERAL PURPOSE REGISTERS
▪ AX
▪ Accumulator Register
▪ Preferred register to use in arithmetic, logic and data transfer
instructions because it generates the shortest Machine Language Code
▪ Must be used in multiplication and division operations
▪ Must also be used in I/O operations

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GENERAL PURPOSE REGISTERS (CONTI..)

▪ BX
▪ Base Register
▪ Also serves as an address register
▪ Used in array operations

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GENERAL PURPOSE REGISTERS (CONTI..)

▪ CX
▪ Count register
▪ Used as a loop counter
▪ Used in shift and rotate operations

▪ DX
▪ Data register
▪ Used in multiplication and division
▪ Also used in I/O operations

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POINTER & INDEX REGISTERS
▪ Contain the offset addresses of memory locations
▪ Can also be used in arithmetic and other operations
▪ SP: Stack pointer
▪ Used with SS to access the stack segment

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 POINTER & INDEX REGISTERS (CONTINUED)

▪ BP: Base Pointer

▪ Primarily used to access data on the stack
▪ Can be used to access data in other segments

▪ SI: Source Index register

▪ is required for some string operations
▪ When string operations are performed, the SI register points to memory locations in
the data segment which is addressed by the DS register. Thus, SI is associated with
the DS in string operations.

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 POINTER & INDEX REGISTERS (CONTINUED)
▪ DI: Destination Index register
▪ is also required for some string operations.
▪ When string operations are performed, the DI register points to memory locations in
the data segment which is addressed by the ES register. Thus, DI is associated with
the ES in string operations.
▪ The SI and the DI registers may also be used to access data stored in arrays

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 SEGMENT REGISTERS
▪ Are Address registers
▪ Store the memory addresses of instructions and data
▪ Memory Organization
▪ Each byte in memory has a 20 bit address starting with 0 to 220-1 of addressable
memory

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SEGMENT REGISTERS (CONTINUED)
▪ Segment numbers range from 0000 to FFFF

▪ Within a segment, a particular memory location is

specified with an offset

▪ An offset also ranges from 0000 to FFFF

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 SEGMENT REGISTERS (CONTINUED)
▪ If the segment address is for example, 2915, then the addresses in this segment
start at 2915:0000 and go up to 2915:FFFF, which is the highest address in this
particular segment.

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MEMORY SEGMENTATION

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MEMORY ADDRESS GENERATION
Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

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ADDRESS CALCULATION
MEMORY ADDRESS GENERATION

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 FLAG REGISTER

Carry flag
Overflow

Direction Parity flag

Interrupt enable Auxiliary flag

Trap Zero

Sign
6 are status flags
3 are control flag

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STATUS FLAGS
▪ There are 6 flag registers in 8086 microprocessor which become set(1) or reset(0)
depending upon condition after either 8-bit or 16-bit operation.
▪ These flags are conditional/status flags.
▪ Sign Flag (S)
▪ Zero Flag (Z)
▪ Auxiliary Flag (AC) :
▪ When some arithmetic operations generates carry after the lower half and sends it to
upper half, the AC will be 1
▪ Parity Flag (P):
▪ This is even parity flag. When result has even number of 1, it will be set to 1, otherwise 0 for
odd number of 1s
▪ Carry Flag (CY)
▪ Overflow (O):
▪ The overflow flag is set to 1 when the result of a signed operation is too large to fit.
 CONTROL FLAGS
▪ Directional Flag (D) – This flag is specifically used in string instructions.
▪ If directional flag is set (1), then access the string data from higher memory location towards
lower memory location.
▪ If directional flag is reset (0), then access the string data from lower memory location
towards higher memory location.

▪ Interrupt Flag (I) – This flag is for interrupts.

▪ If interrupt flag is set (1), the microprocessor will recognize interrupt requests from the
peripherals.
▪ If interrupt flag is reset (0), the microprocessor will not recognize any interrupt requests and
will ignore them.

▪ Trap Flag (T) – This flag is used for on-chip debugging. Setting trap flag puts the
microprocessor into single step mode for debugging. In single stepping, the microprocessor
executes a instruction and enters into single step ISR.
▪ If trap flag is set (1), the CPU automatically generates an internal interrupt after each
instruction, allowing a program to be inspected as it executes instruction by instruction.
▪ If trap flag is reset (0), no function is performed.
80386

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▪ INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986 (mit.edu)
WHAT IS 80386?
• A 32 bit micro processor
• Chip has 132 pins
• Total of 129 instructions
• 32 bit data bus and 32 bit address bus
• Executions in highly pipelined
• S/w written for 8086, 80186,80286 will run on 386.
• Available in 2 versions; DX and SX.
WHAT IS 80386?
▪ Makes use of 80387 co-processor.
▪ Features like –
▪ Virtual memory
▪ Paging
▪ 4 levels of protection

▪ Can operate in 3 modes:

▪ Real
▪ Virtual
▪ Protected Virtual mode
BIU
▪ The Bus Interface Unit provides the interface between the 80386 and its
environment.
▪ It accepts internal requests for code fetches (from the Code Prefetch Unit) and data
transfers (from the Execution Unit), and prioritizes the requests.
▪ At the same time, it generates or processes the signals to perform the current bus
cycle.
▪ These signals include the address, data, and control outputs for accessing external
memory and I/O.
▪ The Bus Interface Unit also controls the interface to external bus masters and
coprocessors.
CODE PREFETCH UNIT
▪ The Code Prefetch Unit performs the program look ahead function of the 80386.
▪ When the Bus Interface Unit is not performing bus cycles to execute an instruction,
the Code Prefetch Unit uses the Bus Interface Unit to fetch sequentially along the
instruction byte stream.
▪ These prefetched instructions are stored in the 16-byte Code Queue to await
processing by the Instruction Decode Unit.
▪ Code prefetches are given a lower priority than data transfers; assuming zero wait
state memory access, prefetch activity never delays execution.
▪ On the other hand, if there is no data transfer requested, prefetching uses bus
cycles that would otherwise be idle.
▪ Instruction pre fetching reduces to practically zero the time that the processor
spends waiting for the next instruction.
INSTRUCTION DECODE UNIT
▪ The Instruction Decode Unit takes instruction stream bytes from the Prefetch
Queue and translates them into microcode.
▪ The decoded instructions are then stored in a three-deep Instruction Queue (FIFO)
to await processing by the Execution Unit.
▪ Immediate data and opcode offsets are also taken from the Prefetch Queue.
EXECUTION UNIT
▪ The Execution Unit executes the instructions from the Instruction Queue and
therefore communicates with all other units required to complete the instruction.
▪ The functions of its three subunits are as follows:
▪ The Control Unit contains microcode and special parallel hardware that speeds multiply,
divide, and effective address calculation.
▪ The Data Unit contains the ALU, a file of eight 32-bit general-purpose registers, and a 64-
bit barrel shifter (which performs multiple bit shifts in one clock). The Data Unit performs
data operations requested by the Control Unit.
▪ The Protection Test Unit checks for segmentation violations under the control of the
microcode.

▪ To speed up the execution of memory reference instructions, the Execution Unit partially
overlaps the execution of any memory reference instruction with the previous instruction.
SEGMENTATION UNIT
▪ The Segmentation Unit translates logical addresses into linear addresses at the
request of the Execution Unit.
▪ The on-chip Segment Descriptor Cache stores the currently used segment
descriptors to speed this translation.
▪ At the same time it performs the translation, the Segmentation Unit checks for bus-
cycle segmentation violations.
▪ The translated linear address is forwarded to the Paging Unit.
PAGING UNIT
▪ When the 80386 paging mechanism is enabled, the Paging Unit translates linear
addresses generated by the Segmentation Unit or the Code Prefetch Unit into
physical addresses.
▪ (If paging is not enabled, the physical address is the same as the linear address,
and no translation is necessary.)
▪ The Page Descriptor Cache stores recently used Page Directory and Page Table
entries in its Translation Lookaside Buffer (TLB) to speed this translation. The
Paging Unit forwards physical addresses to the Bus Interface Unit to perform
memory and I/O accesses.
REGISTERS
GENERAL PURPOSE REGISTERS
▪ The general registers of the 80386 are the 32-bit registers EAX, EBX, ECX, EDX,
EBP, ESP, ESI, and EDI.
▪ These registers are used interchangeably to contain the operands of logical and
arithmetic operations.
▪ They may also be used interchangeably for operands of address computations
▪ Except that ESP cannot be used as an index operand.
SEGMENT REGISTERS
▪ At any given instant, six segments of memory may be immediately accessible to an
executing 80386 program.
▪ The segment registers CS, DS, SS, ES, FS, and GS are used to identify these six
current segments.
▪ The CS and SS are the code and the stack segment registers respectively,
▪ The DS, ES, FS, and GS registers allow the specification of four data segments, each
addressable by the currently executing program
CODE SEGMENT REGISTER
▪ The segment containing the currently executing sequence of instructions is known
as the current code segment; it is specified by means of the CS register.
▪ The 80386 fetches all instructions from this code segment, using as an offset the
contents of the instruction pointer.
▪ CS is changed implicitly as the result of intersegment control-transfer instructions
(for example, CALL and JMP), interrupts, and exceptions
STACK SEGMENT REGISTER
▪ Subroutine calls, parameters, and procedure activation records usually require that
a region of memory be allocated for a stack.
▪ All stack operations use the SS register to locate the stack.
▪ Unlike CS, the SS register can be loaded explicitly, thereby permitting
programmers to define stacks dynamically.
MORE REGISTERS…IP
▪ A 16 bit instruction pointer IP is available along with 32 bit counterpart EIP.
FLAG ERGISTER
▪ Flag Register of 80386: The Flag register of 80386 is a 32 bit register.
▪ Out of the 32 bits, Intel has reserved bits D18 to D31, D5 and D3, while D1 is always
set at 1.
▪ Two extra new flags are added to the 80286 flag to derive the flag register of 80386.
They are VM and RF flags.
▪ The arithmetic instructions use OF, SF, ZF, AF, PF, and CF. The SCAS (Scan String),
CMPS (Compare String), and LOOP instructions use ZF to signal that their
operations are complete.
▪ There are instructions to set, clear, and complement CF before execution of an
arithmetic instruction.
▪ Setting DF causes string instructions to auto-decrement; that is, to process strings
from high addresses to low addresses.
▪ Clearing DF causes string instructions to auto-increment, or to process strings from
low addresses to high addresses.
ADDRESSING MODES
▪ Determine the way of locating data or operands.
▪ The way in which we can access them – addressing mode.
REGISTER ADDRESSING
▪ The most common form of data addressing.
▪ Once register names are known, easiest to apply.
▪ The microprocessor contains these 8-bit register names used with register
addressing: AH, AL, BH, BL, CH, CL, DH, and DL.
▪ 16-bit register names: AX, BX, CX, DX, SP, BP, SI, and DI.
▪ In 80386 & above, extended 32-bit register names are: EAX, EBX, ECX, EDX, ESP,
EBP, EDI, and ESI.
▪ 64-bit mode register names are: RAX, RBX, RCX, RDX, RSP, RBP, RDI, RSI, and R8
through R15.
▪ Important for instructions to use registers that are the same size.
▪ never mix an 8-bit with a 16-bit register, an 8 or a 16-bit register with a 32-bit
register
▪ this is not allowed by the microprocessor and results in an error when assembled
▪ The effect of executing the MOV BX, CX instruction at the point just before the BX register
changes. Note that only the rightmost 16 bits of register EBX change.

The source register’s contents do not change. The destination register’s contents do change .
The contents of the destination register or destination memory location change for all
instructions except the CMP and TEST instructions.
The MOV BX, CX instruction does not affect the leftmost 16 bits of register EBX.
IMMEDIATE ADDRESSING
▪ Term immediate implies that data immediately follow the hexadecimal opcode in
the memory.
▪ Immediate data are constant data
▪ Data transferred from a register or memory location are variable data
▪ Immediate addressing operates upon a byte or word of data.
▪ The operation of the MOV EAX,3456H instruction.
▪ This instruction copies the immediate data (3456H) into EAX.
▪ The source data overrides the destination.
▪ In symbolic assembly language, the symbol # precedes immediate data in some
assemblers.
▪ MOV AX,#3456H instruction is an example

▪ Most assemblers do not use the # symbol, but represent immediate data as in the
MOV AX,3456H instruction.
▪ If hexadecimal data begin with a letter, the assembler requires the data start with a
0.
▪ to represent a hexadecimal F2, 0F2H is used in assembly language
▪ Decimal data are represented as is and require no special codes or adjustments.
▪ an example is the 100 decimal in the MOV AL,100 instruction
 DIRECT DATA ADDRESSING
▪ Applied to many instructions in a typical program.
▪ Similar to immediate addressing in that information coded directly into the
instruction
• Immediate information is the effective address—called the direct address
▪ Direct addressing with a MOV instruction transfers data between a memory
location, located within the data segment, and the AL (8-bit), AX (16-bit), or EAX
(32-bit) register.
▪ MOV AL,DATA loads AL from the data segment memory location DATA (1234H).
▪ DATA is a symbolic memory location, while 1234H is the actual hexadecimal
location
▪ The operation of the MOV AL,[1234H] instruction when DS=1000H

• This instruction transfers a copy contents of memory location 11234H into

AL.
− the address is formed by adding 1234H (the offset address) and 10000H
REGISTER INDIRECT ADDRESSING
▪ Allows data to be addressed at any memory location through an offset address held
in any of the following registers: BP, BX, DI, and SI.
▪ In addition, 80386 and above allow register indirect addressing with any extended
register except ESP.
▪ The operation of the MOV AX,[BX] instruction when BX = 1000H and DS = 0100H. Note
that this instruction is shown after the contents of memory are transferred to AX.
▪ The data segment is used by default with register indirect addressing or any other
mode that uses BX, DI, or SI to address memory.
▪ If the BP register addresses memory, the stack segment is used by default.
▪ these settings are considered the default for
these four index and base registers
▪ For the 80386 and above, EBP addresses memory in the stack segment by default.
▪ EAX, EBX, ECX, EDX, EDI, and ESI address memory in the data segment by fault.
▪ Indirect addressing often allows a program to refer to tabular data located in memory.

▪ Figure shows the table and the BX register used to sequentially address each location in
the table.

▪ To accomplish this task, load the starting location of the table into the BX register with a
MOV immediate instruction.

▪ After initializing the starting address of the table, use register indirect addressing to store
the 50 samples sequentially.
BASE + INDEX ADDRESSING
▪ Similar to indirect addressing because it indirectly addresses memory data.
▪ The base register often holds the beginning location of a memory array.
▪ the index register holds the relative position of an element in the array
▪ An example showing how the base-plus-index addressing mode functions for the MOV
DX,[BX ][DI] instruction. Notice that memory address 02010H is accessed because
DS=0100H, BX=100H and DI=0010H.
▪ A major use is to address elements in a memory array.
▪ To accomplish this, load the BX register (base) with the beginning address of the
array and the DI register (index) with the element number to be accessed.
▪ Figure shows the use of BX and DI to access an element in an array of data.
REGISTER RELATIVE ADDRESSING
OR BASE/INDEX + OFFSET
▪ Similar to base-plus-index addressing and displacement addressing.
▪ Data in a segment of memory are addressed by adding the displacement to the
contents of a base or an index register (BP, BX, DI, or SI)
▪ Figure shows the operation of the MOV AX,[BX]+1000H instruction.
▪ operation of the MOV AX, [BX]+1000H instruction, when BX=0100H and DS=0200H .
BASE RELATIVE-PLUS-INDEX ADDRESSING
▪ Similar to base-plus-index addressing.
▪ Adds a displacement
▪ uses a base register and an index register to form the memory address
▪ This type of addressing mode often addresses a two-dimensional array of memory
data.
▪ An example of base relative-plus-index addressing using a MOV AX,[BX][SI]+1000H
instruction. Note: DS=1000H
INDEX * SCALE + OFFSET
▪ MOV EAS, [ESI*4]+ 911
▪ A scaling factor is multiplied with index register and an offset is added.
BASE + INDEX * SCALE
▪ MOV EAX, [EDX][ESI*4]
▪ Base register + index * scale factor
BASE + (INDEX * SCALE) + OFFSET
▪ MOV EAX, [EBX][EDI*2] + 111