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Dicd Notes 1

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221 views33 pages

Dicd Notes 1

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ONIT=1 Untroctuctlon to VHDL { integvated veut Stewed: for Noy hgh _> VHDL Daeiption dar Handuwore Sy & one of the progra 1 TE 1d used te model a Z digital behavioral gy atyuctural sgt of Coupe is a case Ttensive Jan strongly type: qd 2 Strongly type Mea. aesign components hey should Pt ehther bik Ape, pooleaY + gtd —togée typt ete damental subon ob a base Yupr codes dibrarys syntax t olibvary Hborowg —name s eg: Hibrory fees, hinat ts dibrary ? dibrary fe the toliectron nt rey contyy archt that the “IP @ oe of the of the same type veal, integey, Ailierdl ns should be vot design ° of tommpile Hteebuve, con ttquvertion Use statement ean’ acetrs atétfeyen? Components Qniiden, tne Wbvary: Syntax OF US slotemenr > Use Itbrary— name: package — eqs Use fees std fogte— wey all; Duserbing a Aeign oe > for learning VubL, clument 0b the lanquege: —_ Name-tkem — name 5 we will Start yh foarte yn vib! fule ye ree ’ } ft nore iy bah be described —uting 5 An. ently c : 4 iiiy _ dectavation a Package declarattyr, he ; | ft 5 Porkage buoctey . a Architecture Conflguvation d 1 Entity davation Tt definite the a hayolwave module mamer, TP of signals and. meg. entily entily—name ti Port declaration ; end ent'ty—name ; 2 Tt auscvibe tne Pobevface of tne destan to. tty | Mternal environment: th can be use og a Component € Wp othey entity after bein Compil ibravy work 7 Pile imtoo defautt > forts oe intev face through whith en ee. ° eee con communtcater. with Ft chutyonments - > Por declorati q % clavation define te ace Yee ) Are cbt and possible defaults vatu Cor te Banal « * ‘ x A > ach pore has a type fe Bk ~ NPE Sh bogie type - DE pore WAL ae livection teDN COT ,DNOUT BUFFER = “5 aN= Thu eee re npurs Ge Thdicakes the Fp port aohose Ma Naluess can ead bu sho : aE cannot assign ary yale te Oe = oe Bee pee Gk 2 810 out Oulpurs THA SNE output port yohieh watit” Can only be asstan but nok ver bee Sphe es a re Meath DINOUT= TF indicate bitter tonal pore anode Value aan be Yead and altO acsfan = BUPERS I Tt an olf pst with veo ‘capablithy Fb is mot @& Bieltvertional pert ste. pork cam i mn be rad and writes Th hie only one Souivce Astiqn, deo bl at > for ee Fly AND gate dibravy teres, des ‘ 5 ute Veeen tty —togit UGH oly enHhy mda ik, POE Cogbtin std logic 5 21 ouk shi logte ce End ands 2) Pyehfhect ures. ane E “ay PmuMtecture body tontadns tre Sntemal detip Hoo Ls sa ‘ponent | gt toe to! op Hructue ob-tne | t tray dine Functioning & Thre sty! pu => Tr dumbs q . _ Gite vihian eat cleus! fuses peient 7 4 5 BS prs yecture ee. ak ee possible | * pvt | ect 3 viihou® oer have muttple bennett) 5 ay 6 Gane candy to ees deuaaiatel Oo > Areitteckure 0" ; Frortion tke Hype regerent level OF Alb strach ’ o r , daign ot ov pidoatowmbilubth Ries ke level, R et only Lonturrear statement | Breet, OO ‘ ree e ee? : toneuryyeor totemnint Vat yaleu | Pegust Us only ® Aaymiee Mend tena -grquentiol cletement hed \ doit “Plove rerouted pe mad ashy pitfee™ types ave / é 1 meodleling modeling o enentrore* spate Flow modeling actural strtvedt Style Behavioral style : No structure > Gomelime (allel hey > ktrot assignment statement consists of tre pyecey stakemint: Foy Gui NAND Gtake~ Hbvavy Fete 5 use Tree Std logte -ney- all, Entity anand 2% porbCabrin std logic, ys out S41 ena nand-2) prtmnteckuve behavioval of Begun proce 6 C4) b) hertin : Tt Ca Wg matt) Reh SNe J end iE; end end prot f beha’ high level dese phon ty vepvesent ov behavi sequential fhatement oF VDL, under std. logic) Nander ts pate Flows shyt tonttol Sanat flow ayeli teetur ee ak hing Con Ue ‘Har 3 CCenbeagteo st aternint skabenrent 5 tly 1 ancowsy Hatt acleter ov tibrary eee est logic 164 alts ve Skt Logics Tp pe= Data flow] ead logics erectuve BF OF HA Ko boty Pees ond bis cx end DES armckural Shuler agrierconmetion ef -alstady desTgned compe pore steeeure ic component declavation @ e Sen pones = > gyeuctural ave (ike ee using Lorewryent statement A pakallame nt yaner Ts pore map! 6 4 é t Angerconmertion withy wotley warrene ° wo qe is Wed In fort Map pork & com ponunt ghuchwrat modecing style fue hypes of port mop « Name pert Map + map actual detteranan Prt thee ave 1) pettonal pot map) PosiHonal fort map> Jn posiHonal pov povamefers ave agsodated Sequemttally « Nome port mapie cin this, we have % gach patr of foveal Paranal spect) attual avtoctacbion bl i gree! ‘ye siete fue bv ot Aiclov, a = tf vey net shunt ah f pile ' bath ie 4 peor ueamp te LOA ai ae ye ee aA ss ameglnnyi ee ; Sect soporte. Rye ane A) Ce att cant collection Of Vecturt eo A tomperite type Vp™ ayers Sate ove, types TY Be Hy Recorel Type peway Type 7h) yp | . ae fy toniaint many clementr OF ghee b ‘ : pat are type 4 mest ae 4 tontatns many. element of a aifferenle type ' ‘ F L | SS AUray ale jurttux aAivicled jyrld) a type chr ane climensional & wal dimeviionel a dy mult! limensional + 4% ont dimantional (on uni dimenvionad a mano anay—type iG Chadum hype | element new: gyaten- ctype auatay mame te array (inde Yoange) ef = etemarst name | types pod Ot ype byte th array etaden veerdqe a Avtar ‘py; ee dotontbo) bf cha ark tamuttidementionnl ! : d Hy aay atta ctype fj Clade, induate, odin seit Syren * hype aehiaye naire tt aunay Cindea yange, Findlet tounge) : oF alement type 5 For oF Ype mama IS ostay C3 down 0, 4 down 100) * , Std — logics 3) Atkty Access belonging to a fa > Value ctong ing tu 1a poiplot dynamic altocated obj RNa f Ag! e Oth tips Sunkaw:- type phy is St4 Normally We Wee ee ponte ie “utuy Beat care mit verona Sye tye. hit computer yonteh ute a powerful: pvotelsor witty Aig speet iets ale dont tare about the merory kage ome: to VHDL @ Siig htly tg mpitrated pode gut wh it bent 8 » kringe the memory, @ othe nak. Mind oe pincers at Itmfttd fo a, FPGA phic th why iF te atttfadt 7 Genplemeot frage prousding alyorittmne poe than ante in eo apelin yarviouc axehThectuvel boties | modeling tyes a, wept uctth estan ples” . o Modeling styler fn AEDES 0 u sae. ee Ko NADL modeling, Hye ove. 9 Behan fore QD) Pata tloo 4) actual! modeling » Behavioral modeling: ee ye * Soe iu alo cated on nigh tl dascyphon - a oe hts seated RAAT? > Set of ax ign statement vo ree ~ enous” > Tt comity of gequential gtotemunt of WHOL under the procem gkatement, : : boy x: NAND Gude: <1 \ forng feces Use eee Std ~ logic _ 1164-5 pee. sey Tee Os ; ee aes avn 3e * Ae il x beh of nanhd-o 15 i oe begin ae Protea (a,b) belgie petar giao! ele y end procet end Beh) 2) Data tow styles All data tM % ata paths chowe plus all control a all. > Data +lot orchitecttive ig) entecubed user gtatement Necther than procett °@ ete feng For eu- halt adder- Shoat brary feats use Sere. Be tere ral, entity He fe 3 pork Cat bt tin» Std = Lo Se tout std—logie ) 5 ‘ tnd HAY y ad h arth SF of HA iy a v cor e a begin’ $4 = at MOR, bis, 22> at and bt} end pA} 3) Structural Style te For ev PULL adder fap ae “type * «They ote iy eal sia 5083 tae YP oy geatee TH sige ploatury [Haat GO Phytteas wo envneaatio? iy frumusatton 44Pe {c gyntem : es t ‘ jae NT ; a om i Seatld ame ae — Fa cred, greens hu) Std togie; covour pret, f11h.18310) Std logic: gas ype ype tact table i ( (avis Ploatung: fatal hype: Bs, 0) 8 (-) : 4 gyateos'= ype ape naton a vange 5 eu type faregey te nto -8tz “ype wealvealuu (s o:oo\ “ts 2Aa-t3; uM ae type . Ty wipwen prysical ates er type cuument ts 0-0! Lh amp ‘ie (OAL AP ype Ose D c& pol my to Love a) Composite Type? - i > ae vepauent epneebian tf vata sthayyy ote a typur Thay ats: dD punay type thy Rectal" typic ty Ansay Typer E peter lr. ‘s =F aralna Manley Age og eae fle . elements oF Same hype. Wi) Revord ty pet srr i’ i * ; Say wontmins maay elenents oe different typer - Awray ate 4th alividid nto g ty pur - iy ont atimunaianal chovant diennsional ay iat Sihuaienl ba is ie YY One Sathen orton ASS unt iemnslnes s yj. OLY anno 4 hy Condon Z «i YR ype) clement aannie - exaunpl Lenyedahen ¢= "oe" else 103) cohen $= * 10" else 4 ncteeeeO ral’: with ~ Selec * - Syotns with exptevion select out = styrat Z= Expresion 1 voher choice T, exprentor a when chores, cupresion ~ when others + Example: [ibresy eee 5 use Babe. sta logie- Wouralls enbty mv7 4-1 % port (1s Std logic - tide state logic vector C1 Vector Ca lowe TO os down to Vy1', Zr gut std -logeds end mod “Yet; anette behavioural of myn uy (4 pein with — selteé % <= tCo) whes “oo, 4 when wow outpr puacest (8) oo 2 = 9) ): ese ff (ont < elte TF C3! boro <= ae e C2 bet =< = % slic 1F(A\oa00~ = .Y 25-405) ): ele TF €3) bioy cise te CSMEHO < qed): ieee yal): alee BZ ib end VF 5 end pow: end modett; Case Statement i- thatemeak case co Fs Tn oe procs oo” plau oF modu mut exilys(arod ,S* fnput qtarod: input s[rrod: output 25 case C8) Vs : y tor, 000 1 EA 3) yeplaud the po.od =

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