ACPM-5040

3 x 3 mm Power Amplifier Module

LTE Band-40 (2300-2400 MHz)

Data Sheet

Description Features
The ACPM-5040 is a fully matched 10-pin surface mount x Thin Package (0.9 mm typ.)
Power Amplifier Module developed (PAM) for TD-LTE x Excellent Linearity
Band-40 applications. This power amplifier module ope-
rates in the 2300-2400 MHz bandwidth. The ACPM-5040 x 3-mode power control with Vbp and Vmode
meets stringent LTE (MPR = 0 dB) linearity requirements Bypass / Mid Power Mode / High Power Mode
up to 27.7 dBm output power. The 3 x 3 mm form factor x High Efficiency at max output power
package is self contained, incorporating 50 ohm input x 10-pin surface mounting package
and output matching networks.
x Internal 50 ohm matching networks for both RF input
The ACPM-5040 features the 5th generation of CoolPAM and output
(CoolPAM5) circuit technology, which supports 3 power
x Integrated coupler
modes (active bypass, mid power and high power modes)
Coupler and Isolation ports for daisy chain
with 2-bit digital control. The CoolPAM is a stage bypass
PA technology enhancing PAE (power added efficiency) x Green – Lead-free and RoHS compliant
in the low and medium power ranges. The active bypass
feature is added to CoolPAM-5 to enhance the PAE further Applications
in the low output power range and it enables to have ex- x TD-LTE Band-40
ceptionally low quiescent current. It dramatically saves
the average power consumption and accordingly extends Ordering Information
the talk time of handsets with a given battery capacity.
Number of
Part Number Container
A high performance directional coupler is integrated into Devices
the module and both coupling and isolation ports are ACPM-5040-TR1 1000 178 mm (7”) Tape/Reel
available to support daisy chain connection for multi- ACPM-5040-BLK 100 Bulk
band applications. The integrated coupler has excellent
coupler directivity, which minimizes the coupled output
power variation or delivered power variation caused by
Description (Cont.)
the load mismatch from the antenna. The coupler direc- on and off from the digital control logic input from a
tivity, or the output power variation into the mismatched baseband chip. All of the digital control input pins such
load, is critical to the TRP and SAR performance of the as the Ven, Vmode and Vbp are fully CMOS logic compat-
mobile phones in real field operations as well as compli- ible and “Hi” logic state can operate down to 1.35 V. The
ance tests for the system certifications. current consumption by digital control pins is negligible.
Vref and a bias switch are integrated in the ACPM-5040, This power amplifier is fabricated with an advanced InGaP
so an external LDO regulator and a bias switch transis- HBT (hetero-junction Bipolar Transistor) MMIC (microwave
tor are not required. It also makes the PA fully digital- monolithic integrated circuit) process, offering state-of-
controllable by the Ven pin that simply turns the PA the-art reliability, temperature stability and ruggedness.
Absolute Maximum Ratings
No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value
Operation of any single parameter outside these conditions with the remaining parameters set at or below nominal
values may result in permanent damage.
Description Min. Typ. Max. Unit
RF Input Power (Pin) 0 10.0 dBm
DC Supply Voltage (Vcc1, Vcc2) 0 3.4 5.0 V
Enable Voltage (Ven) 0 2.6 3.3 V
Mode Control Voltage (Vmode) 0 2.6 3.3 V
Bypass Control (Vbp) 0 2.6 3.3 V
Storage Temperature (Tstg) -55 25 +125 °C

Recommended Operating Condition

Description Min. Typ. Max. Unit
DC Supply Voltage (Vcc1, Vcc2) 3.2 3.4 4.2 V
Enable Voltage (Ven) Low 0 0 0.5 V
High 1.35 2.6 3.1 V
Mode Control Voltage (Vmode) Low 0 0 0.5 V
High 1.35 2.6 3.1 V
Bypass Control Voltage (Vbp) Low 0 0 0.5 V
High 1.35 2.6 3.1 V
Operating Frequency (fo) 2300 2400 MHz
Ambient Temperature (Ta) -20 25 90 °C

Operating Logic Table

Power Mode Ven Vmode Vbp Pout (LTE MPR = 0 dB)
High Power Mode High Low Low ~ 27.7 dBm
Mid Power Mode High High Low ~ 16.5 dBm
Bypass Mode High High High ~ 7 dBm
Shut Down Mode Low Low Low –

2
Electrical Characteristics for LTE
– Conditions: Vcc = 3.4 V, Ven = 2.6 V, T = 25 :, Zin/Zout = 50 ohm
– Signal Configuration: 3GPP 10 MHz 12RB QPSK Up-Link unless specified otherwise.
Characteristics Condition Min. Typ. Max. Unit
Operating Frequency Range 2300 – 2400 MHz
Maximum Output Power LTE, MPR = 0 dB (High Power Mode) 27.7 dBm
(High Power Mode) LTE, MPR = 0 dB (Mid Power Mode) 16.5 dBm
LTE, MPR = 0 dB (Bypass Mode) 7 dBm
Gain High Power Mode, Pout = 27.7 dBm 25 27.7 dB
Mid Power Mode, Pout = 16.5 dBm 17 21.5 24 dB
Bypass Mode, Pout = 7 dBm 8 12.5 16 dB
Power Added Efficiency High Power Mode, Pout = 27.7 dBm 32.6 36.4 %
Mid Power Mode, Pout = 16.5 dBm 14.5 20.1 %
Mid Power Mode, Pout = 13.5 dBm 14.5 %
Bypass Mode, Pout = 7 dBm 6.1 9.3 %
Bypass Mode, Pout = 3.5 dBm 6.4 %
Total Supply Current High Power Mode, Pout = 27.7 dBm 475 530 mA
Mid Power Mode, Pout = 16.5 dBm 65 90 mA
Mid Power Mode, Pout = 13.5 dBm 45.3 mA
Bypass Mode, Pout = 7 dBm 15 23 mA
Bypass Mode, Pout = 3.5 dBm 9.6 mA
Quiescent Current High Power Mode 75 106 135 mA
Mid Power Mode 12 19 26 mA
Bypass Mode 2 4 6 mA
Enable Current High Power Mode 4 100 PA
Mid Power Mode 4 100 PA
Bypass Mode 4 100 PA
Mode Control Current Mid Power Mode 4 100 PA
Bypass Mode 4 100 PA
Bypass Control Current Bypass 4 100 PA
Total Current in Power-down mode Ven = 0 V, Vmode = 0 V, Vbp = 0 V 10 PA
LTE E-UTRAACLR Pout < (maximum power -MPR) -37 -33 dBc
Adjacent Channel UTRAACLR1 Pout < (maximum power -MPR) -38.5 -36 dBc
Leakage Ratio
UTRAACLR2 Pout < (maximum power -MPR) -60 -39 dBc
Harmonics Second High Power Mode, Pout = 27.7 dBm -37 -35 dBc/1 MHz
Suppression Third -51 -42 dBc/1 MHz
RMS EVM Pout < (maximum power -MPR) 5 %
Pout < (maximum power -MPR -3 dB) 3 %
Input VSWR 2:1
Stability (Spurious Output) VSWR 5:1, All phase -60 dBc
GPS Band Noise Power (Vcc = 4.2 V) High Power Mode, Pout = 27.7 dBm -143 -140 dBm/Hz
ISM Band Noise Power (Vcc = 3.2 V) High Power Mode, 20 MHz 100RB QPSK, -87 -80 dBm/Hz
fc = 2390 MHz, Pout = 26.7 dBm
2420 ~ 2440 MHz
High Power Mode, 20 MHz 100RB QPSK, -102 -94 dBm/Hz
fc = 2390 MHz, Pout = 26.7 dBm
2440 ~ 2460 MHz
High Power Mode, 20 MHz 100RB QPSK, -111 -108 dBm/Hz
fc = 2390 MHz, Pout = 26.7 dBm
2460 ~ 2480 MHz
Phase Discontinuity low power mode lmid power mode, 31 deg
at Pout = 7 dBm
mid power mode lhigh power mode, 5 deg
at Pout = 16 dBm
Ruggedness Pout < 27.7 dBm, Pin < 10 dBm, 10:1 VSWR
All phase High Power Mode
Coupling factor RF Out to CPL port 20 dB
Delivered Power Variation by Load Load VSWR = 2.5:1 All Phase, Constant Pcpl ±0.3 ±1.0 dB
Mismatch with Constant Coupled Power
Daisy Chain Insertion Loss ISO port to CPL port, Ven = Low 0.25 dB

At below 3.3 V operation, 0.5 dB backoff is allowed for maximum power output.
3
Electrical Characteristics for TD-SCDMA
– Conditions: Vcc = 3.4 V, Ven = 2.6 V, T = 25° C, Zin/Zout = 50 ohm
Characteristics Condition Min. Typ. Max. Unit
Operating Frequency Range 2300 – 2400 MHz
Gain High Power Mode, Pout = 27.7 dBm 25 27.7 dB
Mid Power Mode, Pout = 16 dBm 17 21.5 dB
Bypass Mode, Pout = 6 dBm 8 12.5 16 dB
Power Added Efficiency High Power Mode, Pout = 27.7 dBm 31.7 35.3 %
Mid Power Mode, Pout = 16 dBm 12.9 19.5 %
Bypass Mode, Pout = 6 dBm 5.5 8.5 %
Total Supply Current High Power Mode, Pout = 27.7 dBm 490 545 mA
Mid Power Mode, Pout = 16 dBm 60 90 mA
Bypass Mode, Pout = 6 dBm 13 20 mA
Adjacent Channel 1.6 MHz offset High Power Mode, Pout = 27.7 dBm -42 -36 dBc
Leakage Ratio 3.2 MHz offset -54 -46 dBc
1.6 MHz offset Mid Power Mode, Pout = 16 dBm -54 -36 dBc
3.2 MHz offset -67 -46 dBc
1.6 MHz offset Bypass Mode, Pout = 6 dBm -45 -36 dBc
3.2 MHz offset -60 -46 dBc
Harmonics Second High Power Mode, Pout = 27.7 dBm -32 dBc
Suppression Third -54 dBc

At below 3.3 V operation, 0.5 dB backoff is allowed for maximum power output.

4
Footprint
All dimensions are in millimeter

0.10 1.50
0.125

Pin 1

0.60

0.35

0.25 0.35

0.3 0.10

X-RAY TOP VIEW

Pin Description
Pin # Name Description Pin # Name Description
1 Vcc1 DC Supply Voltage 6 CPL Coupling port of Coupler
2 RFin RF Input 7 GND Ground
3 Vbp Bypass Control 8 ISO Isolation port of Coupler
4 Vmode Mode Control 9 RFOut RF Out
5 Ven PA Enable 10 Vcc2 DC Supply Voltage

Package Dimensions
All dimensions are in millimeter

Pin 1 Mark 0.6

1 10

2 9

3 8 3 ± 0.1

4 7

5 6

3 ± 0.1 1.0 ± 0.1

5
Marking Specification
Pin 1 Mark

A5040 Manufacturing Part Number

PYYWW Lot Number

P Manufacturing Info
YY Manufacturing Year
AAAAA WW Work Week
AAAAA Assemby Lot Number

Metallization Solder Paste Stencil Aperture

on 0.5 mm pitch 0.55 0.45
Ø 0.3 mm
0.45 0.35
0.30
1.10
0.60

0.60
0.475

0.35 0.475 1.10

0.55 connected to a inner layer

through a via hole for a
better isolation between PCB Design Guidelines
CPL_IN(ISO) and RFout
The recommended PCB land pattern is shown in figures
on the left side. The substrate is coated with solder mask
between the I/O and conductive paddle to protect the
gold pads from short circuit that is caused by solder
Solder Mask Opening
bleeding/bridging.
0.65 0.50
Stencil Design Guidelines
0.45
A properly designed solder screen or stencil is required
1.30 to ensure optimum amount of solder paste is deposited
onto the PCB pads.
The recommended stencil layout is shown here. Reducing
the stencil opening can potentially generate more voids.
0.60 On the other hand, stencil openings larger than 100% will
0.525 lead to excessive solder paste smear or bridging across the
I/O pads or conductive paddle to adjacent I/O pads. Con-
1.50 sidering the fact that solder paste thickness will directly
affect the quality of the solder joint, a good choice is to
use laser cut stencil composed of 0.100 mm (4 mils) or
0.127 mm (5 mils) thick stainless steel which is capable of
producing the required fine stencil outline.
6
Evaluation Board Schematic
Vcc1 Vcc2
1 Vcc1 Vcc2 10
C5 C4 C6 C7
RF In 2.2 PF 1000 pF 1000 pF 2.2 PF RF Out
2 RF In RF Out 9

Vbp Isolation
3 Vbp ISO 8
C3 50 ohm
Vmode 100 pF
4 Vmode GND 7
C2
Ven 100 pF Coupler
5 Ven CPL 6
C1
100 pF

Evaluation Board Description

C5 C7

C4 C6

A5040
PYYWW
AAAAA

C3
C2 C1

7
Tape and Reel Information

AAAAA
PYYWW
A5040
Dimension List
Annote Millimeter Annote Millimeter
A0 3.40±0.10 P2 2.00±0.05
B0 3.40±0.10 P10 40.00±0.20
K0 1.35±0.10 E 1.75±0.10
D0 1.55±0.05 F 5.50±0.05
D1 1.60±0.10 W 12.00±0.30
P0 4.00±0.10 T 0.30±0.05
P1 8.00±0.10

Tape and Reel Format – 3 mm x 3 mm

8
Reel Drawing
BACK VIEW
Shading indicates
18.4 max.
thru slots

178 +0.4
-0.2 50 min.

25
min wide (ref)

Slot for carrier tape

insertion for attachment
to reel hub (2 places 180° apart)
12.4 +2.0
-0.0

FRONT VIEW

NOTES:
1. Reel shall be labeled with the following
information (as a minimum).
a. manufacturers name or symbol
b. Avago Technologies part number
c. purchase order number
d. date code
e. quantity of units
2. A certificate of compliance (c of c) shall
1.5 min. be issued and accompany each shipment
of product.
13.0 ± 0.2 3. Reel must not be made with or contain
ozone depleting materials.
21.0 ± 0.8 4. All dimensions in millimeters (mm)

Plastic Reel Format (all dimensions are in millimeters)

9
Handling and Storage
ESD (Electrostatic Discharge)
Electrostatic discharge occurs naturally in the environ- various temperatures and relative humidity, and times.
ment. With the increase in voltage potential, the outlet of After soak, the components are subjected to three con-
neutralization or discharge will be sought. If the acquired secutive simulated reflows.
discharge route is through a semiconductor device,
The out of bag exposure time maximum limits are deter-
destructive damage will result.
mined by the classification test describe below which cor-
ESD countermeasure methods should be developed and responds to a MSL classification level 6 to 1 according to
used to control potential ESD damage during handling in the JEDEC standard IPC/JEDEC J-STD-020B and J-STD-033.
a factory environment at each manufacturing site.
ACPM-5040 is MSL3. Thus, according to the J-STD-033
MSL (Moisture Sensitivity Level) p.11 the maximum Manufacturers Exposure Time (MET)
for this part is 168 hours. After this time period, the part
Plastic encapsulated surface mount package is sensitive to
would need to be removed from the reel, de-taped and
damage induced by absorbed moisture and temperature.
then re-baked. MSL classification reflow temperature for
Avago Technologies follows JEDEC Standard J-STD 020B. the ACPM-5040 is targeted at 260° C +0/-5° C. Figure and
Each component and package type is classified for table on next page show typical SMT profile for maximum
moisture sensitivity by soaking a known dry package at temperature of 260 +0/-5° C.

Moisture Classification Level and Floor Life

MSL Level Floor Life (out of bag) at factory ambient = < 30° C/60% RH or as stated
1 Unlimited at = < 30° C/85% RH
2 1 year
2a 4 weeks
3 168 hours
4 72 hours
5 48 hours
5a 24 hours
6 Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label
Note:
1. The MSL Level is marked on the MSL Label on each shipping bag.

10
Reflow Profile Recommendations

tp
Tp Critical Zone
TL to Tp
Ramp-up

TL
Temperature

Tsmax tL

Tsmin

ts Ramp-down
Preheat

25
t 25° C to Peak
Time

Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5° C

Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5° C

Profile Feature Sn-Pb Solder Pb-Free Solder
Average ramp-up rate (TL to TP) 3° C/sec max 3° C/sec max
Preheat
– Temperature Min (Tsmin) 100° C 150° C
– Temperature Max (Tsmax) 150° C 200° C
– Time (min to max) (ts) 60-120 sec 60-180 sec
Tsmax to TL
– Ramp-up Rate 3° C/sec max
Time maintained above:
– Temperature (TL) 183° C 217° C
– Time (TL) 60-150 sec 60-150 sec
Peak temperature (TP) 240 +0/-5° C 260 +0/-5° C
Time within 5° C of actual Peak Temperature (TP) 10-30 sec 20-40 sec
Ramp-down Rate 6° C/sec max 6° C/sec max
Time 25° C to Peak Temperature 6 min max 8 min max

11
Storage Condition Removal for Failure Analysis
Packages described in this document must be stored Not following the above requirements may cause moisture/
in sealed moisture barrier, antistatic bags. Shelf life in a reflow damage that could hinder or completely prevent
sealed moisture barrier bag is 12 months at < 40° C and the determination of the original failure mechanism.
90% relative humidity (RH) J-STD-033 p.7.
Baking of Populated Boards
Out-of-Bag Time Duration Some SMD packages and board materials are not able to
After unpacking the device must be soldered to the PCB withstand long duration bakes at 125° C. Examples of this
within 168 hours as listed in the J-STD-020B p.11 with are some FR-4 materials, which cannot withstand a 24 hr
factory conditions < 30° C and 60% RH. bake at 125° C. Batteries and electrolytic capacitors are
also temperature sensitive. With component and board
Baking temperature restrictions in mind, choose a bake tem-
It is not necessary to re-bake the part if both conditions perature from Table 4-1 in J-STD 033; then determine the
(storage conditions and out-of bag conditions) have been appropriate bake duration based on the component to be
satisfied. Baking must be done if at least one of the con- removed. For additional considerations see IPC-7711 and
ditions above have not been satisfied. The baking condi- IPC-7721.
tions are 125° C for 12 hours J-STD-033 p.8.
Derating due to Factory Environmental Conditions
CAUTION Factory floor life exposures for SMD packages removed
Tape and reel materials typically cannot be baked at the from the dry bags will be a function of the ambient envi-
temperature described above. If out-of-bag exposure ronmental conditions. A safe, yet conservative, handling
time is exceeded, parts must be baked for a longer time approach is to expose the SMD packages only up to the
at low temperatures, or the parts must be de-reeled, maximum time limits for each moisture sensitivity level
de-taped, re-baked and then put back on tape and reel. as shown in next table. This approach, however, does not
(See moisture sensitive warning label on each shipping work if the factory humidity or temperature is greater
bag for information of baking). than the testing conditions of 30° C/60% RH. A solution
for addressing this problem is to derate the exposure
Board Rework times based on the knowledge of moisture diffusion in
the component package materials ref. JESD22-A120).
Component Removal, Rework and Remount Recommended equivalent total floor life exposures can
If a component is to be removed from the board, it is be estimated for a range of humidities and temperatures
recommended that localized heating be used and the based on the nominal plastic thickness for each device.
maximum body temperatures of any surface mount Table on next page lists equivalent derated floor lives for
component on the board not exceed 200° C. This method humidities ranging from 20-90% RH for three tempera-
will minimize moisture related component damage. If any ture, 20° C, 25° C, and 30° C.
component temperature exceeds 200° C, the board must
be baked dry per 4-2 prior to rework and/or component Table on next page is applicable to SMDs molded
removal. Component temperatures shall be measured at with novolac, biphenyl or multifunctional epoxy mold
the top center of the package body. Any SMD packages compounds. The following assumptions were used in
that have not exceeded their floor life can be exposed to calculating this table:
a maximum body temperature as high as their specified 1. Activation Energy for diffusion = 0.35eV (smallest
maximum reflow temperature. known value).
2. For ≤ 60% RH, use Diffusivity = 0.121exp (-0.35eV/kT)
mm2/s (this used smallest known Diffusivity @ 30° C).
3. For > 60% RH, use Diffusivity = 1.320exp (-0.35eV/kT)
mm2/s (this used largest known Diffusivity @ 30° C).

12
Recommended Equivalent Total Floor Life (days) @ 20° C, 25° C & 30° C, 35° C
For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was
classified) Maximum Percent Relative Humidity
Maximum Percent Relative Humidity
Moisture
Package Type and Body Thickness Sensitivity Level 5% 10% 20% 30% 40% 50% 60% 70% 80% 90%
Body Thickness ≥3.1 mm Level 2a ∞ ∞ 94 44 32 26 16 7 5 4 35° C
Including ∞ ∞ 124 60 41 33 28 10 7 6 30° C
PQFPs >84 pin, ∞ ∞ 167 78 53 42 36 14 10 8 25° C
PLCCs (square) ∞ ∞ 231 103 69 57 47 19 13 10 20° C
All MQFPs Level 3 ∞ ∞ 8 7 6 6 6 4 3 3 35° C
or ∞ ∞ 10 9 8 7 7 5 4 4 30° C
All BGAs ≥1 mm ∞ ∞ 13 11 10 9 9 7 6 5 25° C
∞ ∞ 17 14 13 12 12 10 8 7 20° C
Level 4 ∞ 3 3 3 2 2 2 2 1 1 35° C
∞ 5 4 4 4 3 3 3 2 2 30° C
∞ 6 5 5 5 5 4 3 3 3 25° C
∞ 8 7 7 7 7 6 5 4 4 20° C
Level 5 ∞ 2 2 2 2 1 1 1 1 1 35° C
∞ 4 3 3 2 2 2 2 1 1 30° C
∞ 5 5 4 4 3 3 2 2 2 25° C
∞ 7 7 6 5 5 4 3 3 3 20° C
Level 5a ∞ 1 1 1 1 1 1 1 1 1 35° C
∞ 2 1 1 1 1 1 1 1 1 30° C
∞ 3 2 2 2 2 2 1 1 1 25° C
∞ 5 4 3 3 3 2 2 2 2 20° C
Body 2.1 mm Level 2a ∞ ∞ ∞ ∞ 58 30 22 3 2 1 35° C
≤ Thickness ∞ ∞ ∞ ∞ 86 39 28 4 3 2 30° C
<3.1 mm including ∞ ∞ ∞ ∞ 148 51 37 6 4 3 25° C
PLCCs (rectangular) ∞ ∞ ∞ ∞ ∞ 69 49 8 5 4 20° C
18-32 pin Level 3 ∞ ∞ 12 9 7 6 5 2 2 1 35° C
SOICs (wide body) ∞ ∞ 19 12 9 8 7 3 2 2 30° C
SOICs ≥20 pins, ∞ ∞ 25 15 12 10 9 5 3 3 25° C
PQFPs ≤80 pins ∞ ∞ 32 19 15 13 12 7 5 4 20° C
Level 4 ∞ 5 4 3 3 2 2 1 1 1 35° C
∞ 7 5 4 4 3 3 2 2 1 30° C
∞ 9 7 5 5 4 4 3 2 2 25° C
∞ 11 9 7 6 6 5 4 3 3 20° C
Level 5 ∞ 3 2 2 2 2 1 1 1 1 35° C
∞ 4 3 3 2 2 2 1 1 1 30° C
∞ 5 4 3 3 3 3 2 1 1 25° C
∞ 6 5 5 4 4 4 3 3 2 20° C
Level 5a ∞ 1 1 1 1 1 1 1 0.5 0.5 35° C
∞ 2 1 1 1 1 1 1 0.5 0.5 30° C
∞ 2 2 2 2 2 2 1 1 1 25° C
∞ 3 2 2 2 2 2 2 2 1 20° C
Body Thickness <2.1 mm Level 2a ∞ ∞ ∞ ∞ ∞ ∞ 17 1 0.5 0.5 35° C
including ∞ ∞ ∞ ∞ ∞ ∞ 28 1 1 1 30° C
SOICs <18 pin ∞ ∞ ∞ ∞ ∞ ∞ ∞ 2 1 1 25° C
All TQFPs, TSOPs ∞ ∞ ∞ ∞ ∞ ∞ ∞ 2 2 1 20° C
or Level 3 ∞ ∞ ∞ ∞ ∞ 8 5 1 0.5 0.5 35° C
All BGAs <1 mm body ∞ ∞ ∞ ∞ ∞ 11 7 1 1 1 30° C
thickness ∞ ∞ ∞ ∞ ∞ 14 10 2 1 1 25° C
∞ ∞ ∞ ∞ ∞ 20 13 2 2 1 20° C
Level 4 ∞ ∞ ∞ 7 4 3 2 1 0.5 0.5 35° C
∞ ∞ ∞ 9 5 4 3 1 1 1 30° C
∞ ∞ ∞ 12 7 5 4 2 1 1 25° C
∞ ∞ ∞ 17 9 7 6 2 2 1 20° C
Level 5 ∞ ∞ 7 3 2 2 1 1 0.5 0.5 35° C
∞ ∞ 13 5 3 2 2 1 1 1 30° C
∞ ∞ 18 6 4 3 3 2 1 1 25° C
∞ ∞ 26 8 6 5 4 2 2 1 20° C
Level 5a ∞ 7 2 1 1 1 1 1 0.5 0.5 35° C
∞ 10 3 2 1 1 1 1 1 0.5 30° C
∞ 13 5 3 2 2 2 1 1 1 25° C
∞ 18 6 4 3 2 2 2 2 1 20° C

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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-3281EN - December 13, 2011