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Digital Logic Design Lab Manual Experiment 6

The document discusses the implementation of half adders and full adders using integrated circuits. It describes the components, procedures, truth tables, and circuit diagrams for building half adders and full adders on a breadboard. The goal is to understand how half adders and full adders work and verify their operations.

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nabilxr5
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0% found this document useful (0 votes)
18 views

Digital Logic Design Lab Manual Experiment 6

The document discusses the implementation of half adders and full adders using integrated circuits. It describes the components, procedures, truth tables, and circuit diagrams for building half adders and full adders on a breadboard. The goal is to understand how half adders and full adders work and verify their operations.

Uploaded by

nabilxr5
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Department of

Computer Science and Engineering

Title: Construct Half Adder and Full Adder using


Half Adder and Verify the Truth Table.

Digital Logic Design Lab


CSE 204

Green University of Bangladesh


1 Objective(s)
• To attain knowledge on the Half Adder & Full Adder and how they work.
• To implement Half Adder and Full Adder using integrated circuits (IC’s) and verify the truth tables.

2 Problem Analysis
Digital computers perform a variety of information processing tasks. Among the basic tasks encountered are
the various arithmetic operations. The most basic arithmetic operation is the addition of two binary digits.
An adder is a digital logic circuit in electronics that is extensively used for the addition of numbers. Simple
addition consist of 4 possible operations, they are 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, 1 + 1 = 1 and 1 + 1 = 10.
So, coming to the scenario of half adder, it adds two binary digits where the input bits are termed as augend
and addend and the result will be two outputs one is the sum and the other is carry. To perform the sum
operation, XOR is applied to both the inputs, and AND gate is applied to both inputs to produce carry. The
block diagram of Half Adder is shown in the following figure 1. The Truth table of Half Adder is shown in table
1.

2.1 Block Diagram of Half Adder

Figure 1: Block Diagram of Half Adder

2.2 Truth Table of Half Adder


Truth table of 4x1 Multiplexer is shown in 1.

Table 1: Truth Table of Half Adder

From Truth table 1, we can directly write the Boolean functions for each output,
SU M = A0 .B + A.B 0
CARRY = A.B

© Dept. of Computer Science and Engineering, GUB


The pin diagram of IC 7486 a two input XOR gate as shown in figure 2.

Figure 2: Pin Diagram of IC 7486

2.3 Circuit Diagram of Half Adder

Figure 3: Circuit Diagram of Half Adder

3 Required Components & Equipment


1. IC 7408 2. IC 7432 3. IC 7486 4. Resistors: 1 kΩ – 2 nos. 5. LED’s – 2 no’s 6. Connecting Wire. 7. Power
Supply 8. Bread Board.

4 Procedure
Setup the circuits shown as figure 3 following given steps to analyze the operation of the Half Adder.

1. Construct the circuit on breadboard for each Gate as shown in figure 3 by inserting the appropriate IC.
2. Give power supply to pin no. 14 of each IC.
3. Ground the pin no 7 of each IC.

4. Connect LED’s as an out put for SUM and CARRY.


5. Connect a 1kΩ resistor in series with each LED.

© Dept. of Computer Science and Engineering, GUB


6. Check the truth table for all combinations.
7. When output is high the LED will glow, indicates logic 1.
8. When output is low the LED will not glow, indicates logic 0.

5 Implementation On Tinkercad
Figure 4 shows the output of Half Adder using IC 7486 a XOR and IC 7408 a AND gate.

Figure 4: Implementation of Half Adder using IC 7486 a XOR and IC 7408 a AND gate.

6 Input/Output
Verify the following truth table 2 using implemented Half Adder in figure 4.

Table 2: Truth Table of Half Adder

7 Discussion & Conclusion


Based on the focused objective(s) to understand about the Half Adder operations, the additional lab exercise
made me more confident towards the fulfilment of the objectives(s).

© Dept. of Computer Science and Engineering, GUB


8 Lab Task (Please implement yourself and show the output to the
instructor)
1. Implement Full Adder using integrated circuits (IC’s) and verify the truth tables.

8.1 Problem analysis


A full adder is a digital circuit that performs addition. Full adders are implemented with logic gates in hardware.
A full adder adds three one-bit binary numbers, two operands and a carry bit. The adder outputs two numbers,
a sum and a carry bit. The term is contrasted with a half adder, which adds two binary digits. The figure 5
below shows the block diagram of a full adder.
The truth table of a full adder is shown in table 3.

8.1.1 Block Diagram of Full Adder

Figure 5: Block Diagram of Full Adder

8.1.2 Truth Table of Full Adder


Truth table of Full Adder is shown in 3.

Table 3: Truth Table of Full Adder

From Truth table 3, we can directly write the Boolean functions for each output,
SU M = (A ⊕ B) ⊕ C
CARRY = A.B + (A ⊕ B).C

© Dept. of Computer Science and Engineering, GUB


8.1.3 Circuit Diagram of Full Adder
Circuit Diagram of Full Adder is shown in 6.

Figure 6: Circuit Diagram of Full Adder

8.2 Procedure
Setup the circuits shown as figure 6 following given steps to analyze the operation of the Full Adder.

1. Construct the circuit on breadboard for each Gate as shown in figure 6 by inserting the appropriate IC.
2. Give power supply to pin no. 14 of each IC.

3. Ground the pin no 7 of each IC.


4. Connect LED’s as an out put for SUM and CARRY.
5. Connect a 1kΩ resistor in series with each LED.

6. Check the truth table for all combinations.


7. When output is high the LED will glow, indicates logic 1.
8. When output is low the LED will not glow, indicates logic 0.
9. Check the combinations of various inputs as shown in truth table 3.

9 Lab Exercise (Submit as a report)


Design and implement Full Adder using Half Adder and verify the truth table 3.

10 Policy
Copying from internet, classmate, seniors, or from any other source is strongly prohibited. 100% marks will be
deducted if any such copying is detected.

© Dept. of Computer Science and Engineering, GUB

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