Charles Lawrence S.

Tenorio
BSCPE 3.1 A

07 Laboratory Exercise
Procedures:

1. Open the CPU Simulator. On the Program Name, type “Cache Test” and set the Base Address to zero
“0”.Then, click the ADD button.

2. Enter the following codes below, click the SHOW PROGRAM DATA MEMORY button on the PROGRAM
LIST frame, and tick the STAY ON TOP check box on the lower left corner of the DATA MEMORY window.
Afterward, toggle the speed on the PROGRAM CONTROL frame to FAST and click RUN to execute the
instruction. (Note: An error will appear when adding instruction “JEQ 31” since the instruction in P Add
0031 is not yet added. Just continue adding the necessary code.) Wait for the instruction to halt or until
Ladd = 0056. Write your observations and the “CPU 0 time” in the box below.

MOV #0, R01

STB R01, @R01
CMP #63, R01
JEQ 31
ADD #1, R01
JMP 6
HLT

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 3. Click on the SHOW CACHE button in the Cache-Pipeline Tab under CPU Simulator window to display the
data cache window. Make sure the Stay on top check box is checked.

4. Now, flush the cache by clicking on the FLUSH button. Configure the cache with the following settings:
Block Size = 4
Cache Type = Direct Mapped
Cache Size = 16

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 5. Now insert the following code below the instruction JMP 6 in the above code:
LDB 0, R00
LDB 1, R00
LDB 2, R00
LDB 3, R00

6. To execute the above LDB instructions, double click on each of the LDB instructions above. Write down what
you observe in the DATA CACHE WINDOW:

Addr Data Hits Block

0000 00 0 0
0001 01 1 0
0002 02 1 0
0003 03 1 0

7. Insert the following instruction after the last instruction in Step 5 and execute by double clicking on it:
LDB 4, R00

8. Write down the additional contents (i.e., in addition to the above data) of the cache below:

Addr Data Block

0004 04 1
0005 05 1
0006 06 1
0007 07 1

9. Now configure the cache with the following settings:

Block Size = 4
Cache Type = Set Associative
Cache Size = 16
Set Blocks = 2‐way

10. Insert the following new LDB instructions after the LDB 4, R00 instruction:

LDB 8, R00
LDB 12, R00

11. Execute the following set of LDB instructions one after the other in the order listed below. Then, write down
your observations on the table:

LDB 0, R00
LDB 4, R00
LDB 8, R00
LDB 12, R00

Addr Set Block

0000 0 0
0004 1 0
0008 0 1
0012 1 1

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 12. Next, re‐configure the cache so that the Set Blocks is set to 4‐way.

13. Execute the following set of LDB instructions one after the other in the order listed below. Write down your
observations on the table:

LDB 0, R00
LDB 4, R00
LDB 8, R00
LDB 12, R00

Addr Set Block

0000 0 0
0004 0 1
0008 0 2
0012 0 3

14. Clear the cache by clicking on the FLUSH button. Next, execute only the following two (2) LDB instructions
in the above program. Repeat the LDB instruction execution three (3) times. Make note of what you observe
on the table below.

LDB 0, R00
LDB 16, R00

Addr Data Block

0000 00 0
0016 10 1

Conclusion:

Guide Questions:
1. How important is a cache memory in computers?
Cache memory is important because it improves the efficiency of data retrieval. It stores
program instructions and data that are used repeatedly in the operation of programs or
information that the CPU is likely to need next.
Cache memory is used to reduce the average time to access data from the Main memory.
The cache is a smaller and faster memory which stores copies of the data from frequently
used main memory locations. There are various different independent caches in a CPU,
which store instructions and data.

2.Do you think that cache hit and miss entails to degradation of computer performance?
Why?
When the CPU needs data, it immediately checks in cache memory whether it has data or
not. If data is present it results in CACHE HITS, else CACHE MISS data is not in cache
memory so it retrieves data from main memory and inserts a block of data into the cache layer
a cache miss occurs when data is requested from the cache, and it's not found.
A cache miss is an event in which a system or application makes a request to retrieve data
from a cache, but that specific data is not currently in cache memory. Contrast this to a cache
hit, in which the requested data is successfully retrieved from the cache.

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 GRADING RUBRIC
Criteria/Scoring Indicator Score
Content Provided supporting details and factual scenarios. 5
Organization of Ideas Expressed clear points and arranged ideas. 5
Total 10

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