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FPGA Basics 1704320928

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Hassan Khaled
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31 views

FPGA Basics 1704320928

Uploaded by

Hassan Khaled
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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FPGA Basics

FPGA Basics
• Field Programmable Gate Array
• Long history
• PROM, PAL, CPLD
• Gate Array, Standard Cells

• Why FPGAs
• Rapid prototyping
• In field test / modification
• Rapidly changing technology / standard
• Low / mid volume production
• High volume  ASIC or ASSP

2
FPGA Basics
• Advantages
• Flexibility
• Speed to market
• Well characterized

• Disadvantages
• COST
• Maximum clock frequency
• Power

3
FPGA Basics
• Basic Concept
• Many small fixed circuits
+
• Multiple levels of interconnect
+
• Programmable connections

• Enhancements
• Fixed IP blocks
• Memory
• Processors
• Interfaces

4
FPGA Basics
• FPGA – programmable
• 3 primary programming methods
• RAM
• Volatile
• Must be loaded on power-up
• Most common
• Electrically erasable (flash)
• Non-volatile
• Expensive
• Fuse / Anti-fuse
• Non-volatile

5
FPGA Basics
• FPGA – programmable
• JTAG Programming Configurations
• On power-up, the contents of the Configuration Flash Memory
(default program) are loaded into the Configuration RAM
• Flashing lights and numbers we see on power up
• Load programming information (xx.sof file) directly into the
Configuration RAM via the JTAG interface (Programmer)
• Our configuration is loaded

xx.sof file Configuration


SRAM Object File RAM

6
FPGA Basics
• FPGA – programmable
• SRAM based

Switches

Src: Altera - PLDBasics_FPGA_Architecture

7
FPGA Basics
• FPGA – programmable
• Switches are programmed (On or Off) by connecting their
control inputs to C-RAM bit cells
• Switch configurations

CTL from CRAM

8
FPGA Basics
• FPGA – programmable
• Switches connect a series of horizontal and vertical wires
• Connect wires to logic block inputs/outputs
• Allow connections to span across the chip

• Switches connect VDD and Gnd to the inputs of gates to


force 1/0 inputs
VDD Wire Gnd Wire

• Switches connect external pins to block inputs/outputs


Input Pin Wire Wire Output Pin

9
FPGA Basics
• Intel/Altera Max 10

10 Src: MAX 10 Device Handbook


FPGA Basics
• Xilinx Versal

11
FPGA Basics
• Xilinx Zynq

12
FPGA Basics
• Intel/Altera Stratix 10

13

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