666 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 30, NO.

5, MAY 2022

A Self-Calibration Method of a Pipeline ADC Based

on Dynamic Capacitance Allotment
Shatadal Chatterjee and Sounak Roy
Abstract— This manuscript introduces a low-power mixed-signal TABLE I
foreground calibration algorithm of a pipeline analog-to-digital con- L ITERATURE S URVEY
verter (ADC) using a digitally controlled reconfigurable switched-
capacitor multiplying digital-to-analog converter (MDAC) gain controller.
The proposed calibration technique forces the front-end stage MDAC gain
toward its ideal value to achieve the ideal ADC output linearity. In this
brief, a feedback mechanism has been employed to nullify the effect of
change in MDAC gain from its ideal value by sensing a digital back-end
unit response. The proposed method has been simulated using a 0.18-µm
CMOS process. An 11-bit pipeline ADC with a 1.5-bit stage followed by
a ten bit linear back-end ADC (BE-ADC) has been used to calibrate the
non-linearity of the said 1.5-bit stage. Using a low amplifier gain value
of 28 dB, the signal-to-noise-and-distortion ratio (SNDR) of the ADC
improves from 46.21-dB pre-calibration to 65.13-dB post-calibration.

Index Terms— Adaptive gain tuning, foreground calibration,

mixed signal, multiplying digital-to-analog converter (MDAC)
gain, pipelined analog-to-digital converter (ADC). Fig. 1. Block diagram of a pipeline ADC.

mechanism does the job of calibrating the ADC output, without the
I. I NTRODUCTION need of an iteration and update method. Furthermore, this method
Pipelined analog-to-digital converters (ADCs) [1] and [2] are calibrates a pipeline stage within a very few clock cycles, in the
very useful for wireless communication applications because of order of 10. A summary of few existing works is given in Table I.
high speed, high resolution, and low power consumption at the In this brief, an 11-bit pipeline ADC, as shown in Fig. 1, has
same time. As the process technology nodes are shrinking every been considered for illustration. In this ADC, the first stage is under
year, reduction of power consumption becomes one of the critical calibration. The rest of the stages, forming a 10-bit linear back-
design concerns [3]. Modern pipeline ADC incorporates low-power end ADC (BE-ADC), helps in the calibration process. As shown
amplifiers producing non-linearity of the ADC output [4]. In order in [7]–[12] and [17]–[18], BE-ADC outputs are used as data for the
to counter the effect of non-linearity at the ADC outputs, cali- postprocessing in order to carry out objectives such as extraction of
bration has become a popular choice [3], [5]–[16] to meet the radices of the target stages. It may be noted here that using an N-bit
growing specification demand. In this brief, a low-power mixed- BE-ADC for postprocessing is a fairly standard practice for algo-
signal foreground calibration technique has been proposed based on rithms using radix extraction. The proposed method, although does
a digitally assisted dynamic capacitance allocation method. Unlike not use radix extraction, uses the linearity of the BE-ADC to accu-
the radix extraction-based foreground calibration technique (see [7] rately calibrate a pipeline stage. This brief is organized as follows.
and [10]–[12]), the proposed method forces the multiplying digital- Section II explains the proposed technique. Section III discusses the
to-analog converter (MDAC) gain value of a pipeline stage to its ideal circuit implementation of the calibration block. The simulation results
value by deliberately skewing the ideal passive component ratio and are given in Section IV followed by conclusions in Section V.
proper choice of amplifier open-loop gain. The advantage of using
the proposed calibration algorithm over the radix extraction-based II. P ROPOSED C ALIBRATION T ECHNIQUE
calibration algorithm is twofold. First, in case of the radix extraction- Fig. 2 shows the block diagram of the first 1.5-bit stage of an
based calibration algorithm, the ADC output bitstreams are not 11-bit pipeline ADC, along with a BE-ADC of 10-bit linearity.
calibrated; instead, it calibrates an ADC output code that is of the The BE-ADC consists of eight 1.5-bit stages followed by a 2-bit
form Dout = r a1 D1 + DBE , by accurately extracting the value of r a1 . flash stage. The concept of the algorithm is explained considering
The proposed calibration algorithm, on the other hand, calibrates a generalized block diagram of a switched-capacitor pipeline stage.
the ADC output bitstream itself. In doing so, the proposed method In the latter sections, a detailed analysis on two different types
calibrates the relevant stage gain to its ideal value, rather than of pipeline stage topologies, i.e., capacitor flip-over and capacitor
extracting its actual value. Second, typical radix extraction-based nonflip-over types, will be discussed in detail. As gain of pipeline
algorithms often require complex back-end postprocessing to generate stage for both these topologies that depend upon the ratio of the
the correct radices (see [5], [7], and [10]–[12]), e.g., an iteration and two constituent capacitors, they have been indicated as C S and C F
update algorithm. In the proposed method, a fairly simple feedback in Fig. 2. The basic idea behind the calibration algorithm is to use
a dc signal at the ADC input, which has a defined digital output,
Manuscript received November 13, 2021; revised January 20, 2022;
accepted February 10, 2022. Date of publication March 1, 2022; date of DBE, ideal . The corresponding BE-ADC output of that signal is DBE .
current version April 26, 2022. (Corresponding author: Shatadal Chatterjee.) Due to the nonideal nature of the first pipeline stage, DBE is different
The authors are with the Department of Electronics and Communication from DBE,ideal . These two digital outputs are then compared by a
Engineering, Indian Institute of Information Technology Guwahati, Guwahati 10-bit digital comparator, which activates a control logic, associated
781015, India (e-mail: [email protected]).
Color versions of one or more figures in this article are available at
with the stage capacitors C S and C F . Magnitude of the capacitor
https://doi.org/10.1109/TVLSI.2022.3151479. ratio C S /C F is controlled using a unit capacitor bank. In order to
Digital Object Identifier 10.1109/TVLSI.2022.3151479 achieve the appropriate MDAC gain, both C S and C F are adjusted
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