Semester: VI (Regular)

Sub & Code: COA, CS-2006

Branch : CSE,IT,CS&SE,CS&CE,ECS

SPRING MID SEMESTER EXAMINATION-2018

COMPUTERTION ORGANIZATION & ARCHITECTURE(COA)
[ CS-2006]
EVALUATION SCHEME
Full Marks: 25 Time: 1.5 Hours
1. Write short answers [1X5]
a) What is Von Neumman Concept? How does it differ from Havard concept?
Ans: According to Von Neumann concept, before execution of the program, the program along
with data is kept in a single physical memory. But in Havard concept,Two physical memory are
used to keep program and data separately.
b) A 32-bit word processor is connected with a 128G×32 memory module and each
instruction occupies a single word in memory. Then find out the width of PC,MAR,MDR and IR.
Ans:
Memory size=128G32= 2 7 ×2 30× 32= 2 37×32
Width of PC and MAR= 37 Bits
Each instruction occupies a single word in memory ,i.e; 32 bits.
So width of MDR and IR= 32 Bits
c) How many memory references are required by the processor to execute the following
instructions
(i)ADD R1,R2,R3; (ii) PUSH X;
Ans:
(i)ADD R1,R2,R3;  1 memory reference
(ii)PUSH X;  3memory references
d) Write down any one advantage of base register addressing mode
Ans:
One important advantage of base register addressing mode is to facilitate the relocation of
programs in memory.
Or
If total no of base register is n , then a single instruction has the flexibility to access n different
segments of memory. If the offset is k, then that instruction can refer any of n segments of 2k
words each
e) Differentiate between computer organization and computer architecture.
Ans:
Computer Organization Computer Architecture
It refers to the operational / functional units It refers to those attributes of a computer
and their interconnections that realize the system visible to the programmer, that have a
architectural specifications. direct impact on the execution of a program.

2. Write down the functionality of PC,MAR,MDR,IR, GPR(R0 to R n-1). Also explain how an
instruction SUB R0, LocA (meaning [R0]-[LocA]=[LocA] ) is executed by the processor with
neat diagram. [2+3]
Ans:
Functionality of PC,MAR,MDR,IR, GPR(R0 to R n-1) [2 Marks]
PC It is a counter.
It contains the address of the instruction which is being currently executed.
It keeps track of the execution of the program
MAR and MDR are two special registers to communicate with the memory.
MAR It holds the address of memory to or from which data has to be transferred.
MDRIt contains the data that is written into or read from memory.
IR The instruction is decoded here. So the processor comes to know what type operation required and
where from it gets the operand for the operation.
R0 to R(n-1) They are general purpose registers which are used to keep temporary results or used for
special purpose.
How an instruction SUB R0, LocA (meaning [R0]-[LocA]=[LocA] ) is executed by the processor
with neat diagram.[3 Marks]
Diagram:[1 Mark]

Memory

Processor

MDR
MAR CONTROL UNIT

R0
PC ALU
R1

IR
R n-1

Description(Can be point wise / Descriptive )[2 Marks]

SUB R0, LocA
1. [PC]Address of instruction
2.[PC][MAR]
Read control signal is sent from control unit to memory
PC is incremented to point to the next instruction or reset.
3.[MDR][IR]
Decoded Subtraction instruction
Operands are one in memory location LocA and another is in R0.
4.[MAR]LocA
Read control signal is sent from control unit to memory
5.Content of [MDR] and [R0] are forwarded to ALU for Subtraction. Subtraction is carried out.
The result is stored in a temporary register.
6.Result/ Result from temporary register[MDR]
LocA[MAR] // OPTIONAL(It is already there.)
Write control signal is sent from control unit to memory
3. Discuss different types of instructions depending upon the addresses specified in an
instruction. Write a program to evaluate an expression X=((A+B)*C)/(D-E*F+G*H) using 3-
Address and also write another program to evaluate the same expression using 0-Addess
instructions only. In the expression X,A,B,C,D,E,F,G and H are memory addresses. [1+2+2]
Ans:
Types of instructions[1 Mark]
There are 4 types of instructions generally used by the processor whose classification is based
on the no of address field specified. They are as follows
(1) 3 address instruction
(2) 2 address instruction
(3) 1 address instruction
(4) 0 address instruction
Using 3 Address Instructions[2 Marks]
X=((A+B)*C)/(D-E*F+G*H)
ADD A,B,R1;
MUL R1,C,R2;
MUL E,F,R3;
MUL G,H,R4;
SUB D,R3,R5;
ADD R5,R4,R6;
DIV R2,R6,X;
Using 0 Address Instructions[2 Marks]
PUSH E;
PUSH F;
MUL;
PUSH G;
PUSH H;
MUL;
PUSH D;
SUB;
ADD;
PUSH A;
PUSH B;
ADD;
PUSH C;
MUL;
DIV;
POP X;

4. An instruction is kept in memory at an address 300 and the memory address 301 occupies
the address field of the instruction which is shown below. The Opcode is used to add the
content of accumulator with an operand. The content of accumulator is 100 and the content
register R 500 is 400. Find out the content of accumulator and Effective address of operand if
the addressing mode is
(i) immediate (ii) direct (iii) register direct (iv) indirect (v) register indirect [5]

Address Instruction
300 Opcode Mode
301 500

400 700

500 600

600 800
Ans: [each mode carries 1 mark]
Given [Acc]=100
[R 500 ]=400
(i) Immediate mode
E.A= Not Required(Data is part of the instruction)
[Acc]= 100+500=600
(ii) Direct mode
E.A= 500
[Acc]= 100+600=700
(iii) Register direct mode
E.A= R 500
[Acc]= 100+400=500
(iv) Indirect mode
E.A= [500]=600
[Acc]= 100+800=900
(v) Register indirect mode
E.A= [R 500]=400
[Acc]= 100+700=800
5. Discuss the functionality of various parts of digital computer with neat diagram. [5]
Ans: [diagram with explanation carries 5 marks ]
A digital computer consists of five basic functional units. They are
(1)Input Unit
(2)Output Unit
(3)Memory
(4)ALU
(5) Control Unit I/O ALU+ Control
Block diagram Memory
6. Discuss the factors that affect the performance of the computer. If a 8GHz computer takes
7 clock cycles for ALU instructions, 11 clock cycles for branch instructions and 6 clock cycles
for data transfer instructions. Then Find the total time taken by the computer to execute the
program that consists of 10 ALU instructions, 5 branch instructions and 5 data transfer
instructions. [5]
Ans: [Factors must contain explanation]
The factors that affect the performance of the computer are as follows
a) Design of compiler which generates the object code
b) Design of instruction set of processor
c) Design of hardware like processor, disk, I/O devices
Processor frequency= 8GHz
Clock cycle time = 1/8GHz=1/8×10 9 = 0.125 nano second
program consists of 10 ALU instructions, 5 branch instructions and 5 branch
instructions.
For ALU instructions= 10 ×7= 70 clock cycles
For branch instructions=5×11=55 clock cycles
For data transfer instructions=5×6=30 clock cycles
Total cycles needed =70+55+30=155 clock cycles
Total Time= 155×0.125 nano second=19.375 nano second

7. Write short notes on any two of the following [2.5X2]

a) Bus Structure Types
Ans:
The bus structure is of two types.
(1) single bus structure
(2)multiple bus structure
1.Single bus structure
Block diagram with explanation

Input Output Memory Processor

2. Multiple Bus structure

Block diagram

Input

Memory Processor

Output
b) Big Endian v/s Little Endian Scheme[2.5 Marks]
Ans:
Big Endian (Student must give example)
The most significant byte is stored in the lowest byte address
Little Endian(Student must give example)
The least significant byte is stored in the lowest byte address

c) Stack/ Implied addressing mode [2.5 Marks]

Ans: (Student must give example)
In stack addressing mode, the address is not specified in an instruction. The effective
address is available in a special register called stack pointer. The 0-address instruction is
based on stack addressing mode. While executing the instruction, the processor refers
the stack pointer implicitly to fetch the operands.

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