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FPGA for 5G: Re-configurable Hardware for Next Generation Communication

Article in IEEE Wireless Communications · March 2020

DOI: 10.1109/MWC.001.1900359

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 1

FPGA for 5G: Re-configurable Hardware for Next Generation

Communication
Vinay Chamola, Sambit Patra, Neeraj Kumar, Senior Member, IEEE and Mohsen Guizani, Fellow, IEEE

Abstract—Next generation communication relies on standard- to latency sensitive devices used in applications such as
ized protocols, heterogeneous architectures and advanced tech- industrial automation, autonomous driving, remote surgery,
nologies that are envisioned to bring ubiquitous and seamless and remote management. mMTC aims to meet the demands
connectivity. This evolution of communication will not only
improve the performance of the existing networks, but will also of the digital society where the connection density is high
enables various applications in other fields while integrating such as that for a smart city [2].
different heterogeneous systems. This massive scaling of mo- As shown in Fig.1(b), 5G is about distributed network
bile communication requires higher bandwidth to operate. 5G architecture in which data from the core network is transmitted
promises a robust solution by offering ultra-low latency and to the macro base stations through radio network controllers
high bandwidth for data transmission. To provide individuals
and companies with a real-time, social, and all connected ex- (RNC). 5G macro cells use “massive MIMO” (multiple inputs
perience, an end-to-end coordinated architecture which is agile multiple outputs) antennas which benefit a number of users to
and intelligent has to be designed at each stage. As FPGA has connect simultaneously to the base network and provide higher
the potential to be resource/power efficient, it can be used for throughput. As compared to the macro network, which has a
building up constituents of 5G infrastructure. It can accelerate wide coverage area, small cells can be used for shorter range
network performance without making a large investment in new
hardware. Dynamic reconfigurability and in-field programming operating in dense environments. Small cells operate in mm-
features of FPGAs compared to fixed function ASICs help in Wave frequencies range and provide increased data capacity
developing better wireless systems. This article presents various which improves the performance to the connected devices.
applications areas of FPGAs for the upcoming 5G network
planning.
A. Technical Challenges in 5G infrastructure
Developing new type of communication systems depends on
I. I NTRODUCTION globally accepted standards which ensures interoperability and
The next generation of communications is beyond present- affordable cost for deployment of the system. Some technical
day Internet and is moving towards the Internet of Everything challenges for meeting the demands of a 5G network are as
(IoE). 5G , a key pioneer in this will unleash an ecosystem for follows:
connecting billions of devices with optimal trade-off latency, 1) Medium Access Control: In the case of dense deploy-
cost and greater capacity. Fig.1(a) highlights certain salient ment of access points and user terminals, throughput of the
features of 5G. It is estimated that, around 50 billion devices system will reduce and latency would be high. So, there must
will be connected to the 5G network by 2020. So the network be a proper protocol / algorithm for handling massive number
must be able to cope up with the diversified demands. Com- of connected devices without affecting their performance.
pared to today’s 4G and 4.5G (LTE advanced), which is about 2) Data-traffic management: Moving from traditional com-
speed improvement, the evolution of 5G focuses on connecting munication towards deploying machine-to-machine (M2M)
new IoT and critical communication use cases which require communication will not only overload and congest the net-
several performance enhancements [1]. IoT connections are work, but will also pose a threat to the Radio access network
characterized based on the volume of connection, data traffic, (RAN).
and energy consumption. For certain applications, such as self- 3) Multi-Service network: 5G has to offer diversified ser-
driving cars, health services etc.. ultra-low latency communi- vices to heterogeneous networks and devices operating in
cations is a requirement and while for some other applications, different geographies. These devices may be having varied
devices operating on low power mode is an indeed requirement specification (i.e few might demand low latency, some may
helping them to operate for longer duration without regular demand high bandwidth). So the transport network has to be
maintenance. On the other hand, there are several cloud-based intelligent enough to provide dynamic, user-centric and data-
applications for data analytics that require higher bandwidth rich wireless services to various end devices satisfying to their
and speed enhancement. specific need.
According to the International Telecommunication 4) Power consumption: Reducing energy consumption for
Union(ITU), 5G network services can be categorized the services provided is specific to help end-user equipment
as Enhanced Mobile Broadband (eMBB), Ultra-reliable have better battery life.
and Low-latency Communications (uRLLC), and Massive 5) Communication, Navigation and Sensing: These ser-
Machine Type Communications (mMTC). eMBB focuses on vices are highly dependent upon the radio spectrum allocated,
services which require high bandwidth, such as high definition as the transmission capacity depends on that.
(HD) videos streaming, virtual reality (VR), augmented reality The vision of 5G is strongly relying upon the hardware
(AR) and web browsing. uRLLC aims at providing services infrastructure. Hardware designs should be re-configurable
 2

4G
Macrocell
5G
Smallcell

10 to 100x improvement over 4G 99.99% availability 5G

and 4.5G Macrocell Local
Server
4G
5G Macrocell
Smallcell 4G
1 milli-second latency 100% coverage Macrocell

5G Local
TECHNOLOGY Server
90% reduction in Local
1000x bandwidth per unit Server 5G
network energy
Macrocell
Central
Cloud Server
5G
Smallcell
100x more connected upto 10-year battery life fot 5G
devices than 4G IoT devices Smallcell

5G
Macrocell
(a)
(b)

Fig. 1: a) Specification of 5G technology. b) 5G Network Architecture.

to support multiple services, and to be easily upgradeable communication technologies on the top of newer network in-
with new functionalitiesalong with efficient energy manage- frastructure such as cloud-based radio access network (RAN),
ment and cost optimization. FPGAs (Field Programmable software-defined network (SDN) and network function virtual-
Gate Arrays) with the characteristics of Dynamic Partial Re- ization (NFV) etc.. Apart from Captial Expenditure (CAPEX),
reconfigurability (DPR) and the ability to perform at higher incurred during building preliminary infrastructure for 5G
frequencies make it convenient for designing various building and annual maintenance, the Operational capital Expenditure
blocks of the 5G architecture. Also, FPGAs have excellent (OPEX) has to be reduced so that the services can be provided
advantages like hard real-time processing which helps in radio at reduced rates. As the growth of users will substantially
signal processing, parallelism which helps multiple kernel increase the number of base stations, this will lead to more
computation in the same FPGA and energy efficiency in case power consumption and will put more burden on operational
of fixed precision computations than GPUs . However there costs. Thus telecom operators are focusing towards minimizing
are a few challenges associated with the use of FPGA like operational costs and improving hardware and transmission
they being costlier and having higher power consumption as efficiency. Also, issue of load imbalance in different regions
compared to DSP and microcontrollers. Moreover they are at different times leads to the network resources being under-
difficult to program, and being less efficient in floating point utilized.
computations. Also, ASICs (Application Specific Integrated The flexibility of FPGAs enables us to program various
Circuits) are more power efficient and perform better than applications on on top it in different instances. The ability
FPGAs. FPGAs are only preferred when required volume of of the FPGA to re-configure itself dynamically enables us
production is less, and time criticality to market is more. Note to change data transmission capacity along with switching
that various leading FPGA vendors like Xilinx and Altera are between services as per the current requirement. All these
working hard to overcome these challenges and to improve abilities of FPGA are pushing leading FPGA manufacturers to
FPGA design and performance. This work proposes different invest more to make their hardware more capable of dealing
methods to solve the challenges in building the 5G communi- with growing communication technologies. As FPGAs are
cation infrastructure using FPGAs. The main contributions of performing well in signal processing, giving faster output and
this article are as follows higher throughput, they can be used for signal filtering in
1) We summarize different areas of 5G where FPGAs can telecommunication.
play a key role. Xilinx is providing support for solving performance, capac-
2) The application of FPGA in realizing and improvising ity and connectivity challenges. It is providing FPGAs which
state of the art 5G technologies like Network slicing, are embedded with software programmability, multi-band, and
MIMO, C-RAN virtualization etc. is discussed. multi-standard hardware optimization along with hardware
3) For each application, we describe technical details of how level security. Xilinx has developed Zynq MPSoC, RFSoC,
FPGA can be used in them, and also about current leading Ultrascale+ FPGAs and software platforms such as Vivado
research efforts in those directions. High-level synthesis, SDSoC and SDAccel for customers to
Please note that this is not a fully encompassing overview build their applications [3]. Similarly, Intel has designed FPGA
but focuses on certain crucial components of the future 5G based accelerators for handling high-speed data transmission
systems. and greater bandwidth for virtualized workloads. There are
various building blocks of 5G architecture which can be
designed with the help of FPGAs for better performance. In
II. A PPLICATIONS OF FPGA IN 5G this paper we discuss four such major applications namely,
5G is on the horizon of integrating IoT, machine-to-machine FPGA based accelerator for C-RAN, Netwrok slicing using
and machine-to-human communication along with the current Network function Virtualization (NFV), Characterization of
 3

BBU Pool
There are various challenges in deploying C-RAN
architecture, some of those with possible solutions are listed
below:

Backhaul Links

Fronthaul Links A. Cooperation in BBUs

CORE Network
The BBUs in the same pool should cooperate with each
other to share the computing data and should schedule them
RRU Netwok RRU Netwok as per user requirement. But such cooperation is not defined
RRU Netwok
and that introduces challenges in ensuring low latency, high
bandwidth communication among the BBUs and also affects
Fig. 2: Centralized RAN Architecture. the user privacy.
FPGA based Solution: High performance logic in FPGA
Massive MIMO and Cognitive radio framework. can be used to reduce latency of interfacing among the base
band units. At high-capacity base stations, integrated block
III. FPGA BASED SYSTEM DESIGN FOR C-RAN ram can be used for switching among the BBUs.
Radio Access Network is designed to communicate between
base stations and end users. C-RAN (Cloud Radio Access B. Virtualization
Network) is a novel architecture meant for centralized and Virtualization techniques promote the BBUs to share the
cloud-based processing, where the Base Band Unit (BBU) are resources autonomously and increase the lifecycle of RAN
relocated to a centralized pool termed as BBU pool. It enables functions. But the dynamic change of loads and real-time
collaborative radio network, real-time workload virtualization processing requires a robust virtualization technique which
and large scale deployment. These BBU pools are connected is different from current IT virtualization techniques such as
to the network stations through the high-speed optical fibre virtual multimedia IP subsystem, virtual customer premise
and maximize the distance between macro to small cells. The equipment etc. where multiple operating systems and appli-
C-RAN architecture can be perceived as a cloud-computing cations run on the same server at same time in a single
environment where the baseband and channel processing is physical machine which includes network, storage, and com-
virtualized and shared among the operators in the baseband puting resources. In the context of C-RAN, virtualization is
pool, which leads to better traffic handling and maximum done at the BBU pool level, where each BBU acts as a
utilization of resources. It is built on interfacing cards and virtual node which is implemented on the virtual machine
hardware which creates links between base stations and optical and communicates through virtual links. C-RAN virtualization
fibre network. requires sophisticated switches and routers, which are aimed to
Apart from easier deployability and scalability, the cost- replace the software implementation on high volume servers,
effectiveness and manageable solution towards a huge user and storage units in case of IT clouds, to reduce overall cost
base will make it a reliable infrastructure component for 5G. and power. Hence, meeting low latency and higher bandwidth
Fig.2 highlights that C-RAN architecture is built upon three requirements for centralization of RAN functions is raising a
key components: The Base-band Unit (BBU) Pool, Remote critical challenge for realizing virtualization in current C-RAN
Radio Unit (RRU) network and Transport network [4]. practice [5].
The BBU pool: The BBU pool is located at a centralized FPGA based solution: The ability of FPGA to modify its
site, functioning as a data centre. It holds a number of operation at run-time with partition safe mode, enables it as a
baseband nodes which are capable of performing complex shared compute resource in C-RAN. FPGAs can run multiple
computations and storing huge data. It has the ability to applications by virtualizing compute resources and also offers
dynamically interconnect within the nodes or work individ- protection through isolation of applications from each other.
ually as per the network needs. The communication among
the units happens on a larger bandwidth, and lower latency.
After processing, it allocates resources to the RRUs as per the C. Multi-Connectivity
network demand. As dual connectivity feature in LTE helps devices access
RRU network: It is a traditional wireless network which base stations on different frequencies (e.g. macro and small
connects wireless devices to the access points. cells). Similarly multinetwork connectivity in 5G over multi-
Transport network: It is also termed as Fronthaul network. mode base stations such as GSM, LTE, UMTS and WiFi
It is a communication layer between the BBU and the RRUs enhances peak throughput of the devices. But deploying a
which provides a high bandwidth channel for handling multi- multi-mode base station increases the capital cost.
ple RRU networks. It can be optical fibre based linking capable FPGA based solution: Multi-connectivity can be realized
of transferring high bandwidth and with a faster rate, but it by using Software Defined Network (SDN) and Software De-
adds on more cost. On the other hand, we can have cellular fined Radio(SDR), as they offer cheaper approach than a multi-
communication at an mm-wave level which is much cheaper mode base station. SDN’s and SDR’s are designed with an
than optical fibre. approach of integrating software and hardware infrastructure,
 4

where software can perform controlling and hardware as a architecture can be implemented on FPGA using Verilog
compute resource. The ability of partial reconfiguration in Hardware defined language and some predefined IP cores on
FPGAs, enable it to handle multiple operations and acts as a the Xilinx synthesis tool. The host OS will consist backend
hardware accelerator for complex computation. This solution driver for PCIe and Xen environment and the Guest Os will
is discussed in detail as follows. hold the frontend drivers which will be used for transmitting
Software Defined Approach towards the multi-connectivity data between SDR base stations.
issue: As the implementation of the multi-mode base stations
for building a multi-network system is a costly approach, so The decoder can be implemented along with encoder to
we can realize the same using SDN’s and SDR’s. SDR’s improve the transmission efficiency of digital communication
can be used for allocation of radio (spectrum) resources over the noisy data channel. Turbo coding is a very powerful
to multi users, where as SDN’s can be used for dynamic error correction technique which can be implemented to detect
network re-configuration. Integrating both, SDR and SDN and correct the errors when the communication channel is
can adhere to changes in frequency and communication pro- noisy. The turbo decoder iterates many times to provide the
tocols through software reconfiguration at lower costs. But decoding result. To reduce the latency in decoding, FPGAs can
the challenge of handling high bandwidth and low latency be a better alternative over traditional CPUs.The high clocking
communication requirements puts limitation on software-based frequency and the parallel pool base processing can speed up
solutions. This is because the SDR base stations also need to the decoding process.
perform computation-intensive tasks at high speed. To deal As shown in Fig.3(b) Turbo decoder architecture consists
with such complex tasks, Hardware accelerators can be used of three layers: Top layer, Control layer and Decoder layer.
along with software technologies such as turbo decoders, FFT
etc. Hardware accelerators can improve performance and are Top Layer consists of the data and signal transmission
faster as compared to software-based processing. Through vir- drivers such as the PCIe hardware interface and DMA con-
tualization, the utilization of hardware resources such as FPGA troller. The data and control signal can be transmitted between
and GPUs can be improved by replacing the small physical the PCIe driver of FPGA and the server driver which is part
servers with larger ones. The SDR signal processing can be of the top layer.
performed using FPGA and Xen platform based hardware Control Layer acts as an intermediate layer which passes the
accelerator [6]. data and control parameters(such as Block size, reset signal
System has structure as in Fig.3(a), which includes a SDR etc) between the PCIe hardware driver and the decoder and
platform and a custom hardware accelerator. FPGAs are very vice-versa.
good accelerators as compared to GPUs because their latency Decoder Layer can be implemented using the IP core for
are far less than the GPUs. In FPGA, algorithms are embedded turbo decoder under 3GPP LTE decoder core. In this layer,
into the hardware and thus processing speed is far better data caching can be done using a FIFO and also asynchronous
than a software-based GPU process. This is because software clocks can be isolated from DMA and decoder. When data
processes have to share processing resource (OS etc.) which is and control signals are received in the decoder layer, it is
not the case with the hardware based solution. Xen hypervisor written into RX FIFO which also masks the invalid data. After
can be used which can enable multiple OS to run on a processing the data in the decoder core, it is sent to the TX
single computer and also provides a special API to access FIFO. Then the control layer reads the data from the TX FIFO
the hardware. It also supports para-virtualization which can after reading its status.
reduce performance loss. Some SDR platforms based on DSPs After designing and implementing the turbo-decoder on
and FPGAs can be used to minimize power consumption and FPGA it can be simulated using various synthesis tools such
improve the processing density of the baseband units. as Xilinx ISE, Vivado HLS and Modelsim etc. By designing
Multi-mode base stations need high bandwidth and a cost a scheduling algorithm and pushing it into accelerators, we
effective resource allocation technique to efficiently implement can achieve multitasking and resource sharing among the
multi-network communication. These base stations can be accelerators holding VMs, individually.
run on hardware accelerators for faster signal processing. A
Turbo decoder accelerator can perform better SDR signal
IV. N ETWORK S LICING USING N ETWORK F UNCTION
processing with high bandwidth, and also sort out timing
V IRTUALIZATION OVER FPGA
constraints.The Turbo decoder accelerator can be designed
using Xen para-virtualization environment and FPGA as an Network-slicing is a typical virtual architecture belongs to
accelerator which can enhance the performance of C-RAN the software-defined network (SDN) and Network function
based signal processing [7]. The SDR base stations can deploy virtualization (NFV) family which will be designed through
FPGAs to accelerate the decoding process which will reduce logical partitioning of physical resources. Slicing introduces
the overall signal processing time effectively. custom tailoring of the network which enables the operators to
Turbo-Decoder design and Operation over FPGA: The customize their services as per consumer demand [8]. Fig.4(a)
system consists of customized hardware as accelerator and highlights the assignment of individual slices for different ser-
a virtualization environment which can support multiple vices as per the users network requirements. Network slicing
guest OS to run simultaneously, individually corresponding will offer resource sharing ability to the service providers
to singular Virtualization Base station. The accelerator through which they can improve the quality of service. A
 5

Guest OS
Server (SDR Platform)
Signal Signal
Process Process

Front-End Driver

Top_Layer PCIe Interface DMA Controller

Host OS
SDR
Platform
Backend Driver

Control_layer
PCIe Driver High Frequency Clock

Decode_layer

RX TX
Decoder
FIFO FIFO

FPGA
Accelerator

(a) (b)

Fig. 3: a) System Design. b) Turbo-Decoder Architect.

Programmable Control-plane

5G Network Slicing SDN Control (Control plane)

High Bandwidth

3rd 3rd 3rd

Party NFV NFV
Wireless Broadband Party Party
HW1 IF IF
HW2 HW3

IF IF IF
NFV Controller
Real time Control
Ultra low Latency FPGA Based NFV
Cloud Programmable Data-Plane
Vendor A Vendor B
IoT/ Sensors
Hardware Hardware
Accelerator Accelerator
Low energy/Low bandwidth
Library Library

Video
Encryption Processing
Video Streaming

Pattern Intrusion
Ultra High Bandwidth
Matching detection

(a) (b)

Fig. 4: a) Network Slicing Architecture. b) FPGA based NFV.

single physical network can be sliced up logically through users need different slices varying with different class of
a software-based approach into multiple networks such as QoS. This is a complex task and needs ultra-low latency
Ultra bandwidth service for mobile broadband, Ultra-low synchronization between the mediums.
latency and high reliability for transportation, no reservation Assuring Services: If there are multiple services which have
for machine type communication etc. Also, the software-based the same sort of network requirement, then it becomes difficult
techniques can add up more slices dynamically and also share to prioritize the services and to schedule the slices according
the unused slices with others. As the services can configure to that. Network slicing creates challenges for each slice to
itself as on demand, so the overall operational expense can be meet its endpoint demand in the network.
reduced. Slicing Management: The operator needs to manage the
Challenges in Network-Slicing: As network slicing is a network slices so that each slice can adhere to the key
promising solution towards maximization of network resource performance metrics and service level agreements [9]. For
utilization, however various challenges are to be addressed for different heterogeneous systems, interoperability issue must be
building such infrastructure. The various challenges that are overcome if a single slice is being used by different vendors.
faced to deploy a software-defined network slicing environ- All the above issues can be addressed using Network Func-
ment are listed below tion Virtualization (NFV), and thus we discuss this solution in
Isolation of Service: This is a challenging factor in network detail and how FPGA can help in implementing the same.
slicing because the data packets for different services shared End to end Network slicing through Network Func-
within a single resource must be properly isolated so that tion Virtualization (NFV): Upcoming section briefly dis-
individual service performance is not affected. cuss about the benefits of Network Function Virtualization
RAN re-designing: This is required so that all the slices (NFV), in overcoming above mentioned challenges. 5G end-
can be accessed through various mediums such as macrocell, to-end network slicing provides extreme flexibility to provide
microcell and wifi. These mediums must work coherently in- various services over a single channel. Through software
order to share network slices. Even in some medium, different programmability, we can logically define the application of
 6

slices from user equipment level to cloud servers. Through

network virtualization software can provide us with more Data for User-1 User-1
programmable capability and flexibility in terms of creating
logical virtual networks. Furthermore, through virtualization Layer
Data for User-2 PreCoding User-2
we can effectively share resources among slices. A software- Mapping

defined controller can perform orchestration process which

can bring together and coordinate diverse services to work Data for User-3 User-3

coherently over slicing environment. By integrating virtualiza-

tion and orchestration in a system, isolation among the slices Fig. 5: Massive MIMO network architecture.
can be achieved effectively, as isolation plays an important
role in providing more privacy, performance enhancement and multiple antennas at the base stations and access points; both
managing the individual network more effectively. at the transmitting and receiving end by separating independent
Network function virtualization reduces the time to establish wireless channels to provide rich communication over a multi-
a new network by downloading the network function onto the path environment to serve multiple clients simultaneously. In
hardware and also increases the life cycle management of the massive MIMO the base stations are equipped with a large
network slices. Network function virtualization infrastructure number of antennas (e.g 100 or more). The architecture of
is built upon adjoining resources used to host and connect massive MIMO is shown in Fig. 5, which shows multi-user
the network functions. Network management and orchestration input and output through multiple transmitting(Tx) antennas
system can perform general networking tasks, coordinate and and Receiving (Rx) antennas while pre-processing the user
automate the tasks. FPGA as a customizable hardware, can be data at the single BS. MU-MIMO serves the application for
prototyped and introduced into the market within a short span all single antenna users and also through multiplexing, the
of time. So the network function virtualization over FPGA can gain can be shared among its users. Installing massive MIMO
reduce the expenditure of purchasing huge hardware resources. can enhance the channel capacity and provide better signal
An SDN controller can be introduced to centralize the control strength for individual users. The massive MIMO is made up
plane which will manage the connectivity among components. of an array of antennas which consume very low power and
Flexible service provisioning is one of the motives of also reduces the complexity of hardware which is a concerning
Virtualization of network function, which can be achieved factor for base stations. It also provides the flexibility of
by using FPGA as the main hardware. Faster deployment sharing the resources to other antennas when anyone antenna
time using FPGA reduces time to provide newer services fails.
efficiently. As as shown in Fig.4(b), FPGAs can be equipped Challenges in MIMO deployment: Apart from numerous
with various hardware components as per third party applica- benefits of a MIMO system, there are some issues in deploying
tion requirements. Each FPGA can have different capabilities such a large system and those needs to be addressed. The
as per the service demand from end application. This will following are some of those issues.
encourages the innovation and also opens market for vendors
in this emerging domain, which can work coherently within A. Wireless Propagation Environment
the same ecosystem. A competitive market will be built for Every node in MU-MIMO can serve multiple users si-
the FPGA vendors and IP block providers. Multiple vendors multaneously. So accurate measurement of the propagation
can provide hardware which can be used as accelerators for channel for each user needs to be done at real-time. Statistical
multiple application such as, Vendor A provides encryption analysis of the recent measurements of the channels with
module whereas Vendor B provides video compression module optimum accuracy is challenging and the performance impact
[10]. of inaccurate information can be severe.
In application areas where we need to satisfy a high degree FPGA based local processing of data: Serving multi-
of flexibility and performance, FPGA based NFV can be ple users in MU-MIMO requires accurate knowledge of the
a promising platform. It offers similar flexibility, but better communication channel. But collecting information about the
throughput than GPUs. channel in real-time is challenging and it also impacts the
performance of the system. To solve this issue, an integrated
device platform is being proposed by Mango communication
V. FPGA CHARACTERIZING M ASSIVE MIMO
and Rice University, which uses FPGA stack to process raw
Massive Multi Input Multi Output (MIMO) system can channel data between the antennas to characterize massive
improve the throughput, network capacity and reliability over MIMO. The data gathered by each antenna is condensed as
the traditional single input single output (SISO) system. per individual client channel characteristics.
MIMO has been introduced two decades back and has been The Wireless Open-Access Research Platform (WARP) is
used for 4G LTE service. As 5G will bring a revolution by a programmable wireless platform which combines high-
connecting large number devices together, a robust networking performance hardware along with open source repository of
system MIMO system has to be modified to accommodate the reference design [11]. WARP is designed for real-time
in this complex ecosystem. Massive MIMO such as Multi- prototyping of wireless designs. The FPGAs in WARP node
User MIMO (MU-MIMO) delivers significant performance in Argos array of FPGAs has huge processing capability which
improvement over the busy network traffic. MIMO includes can perform real-time processing of data locally and reduce the
 7

Spectrum band
burden on the upstream processor. This real-time processing
Unlicensed band Other cognitive
of channel data in the submillisecond range allows accurate CR user radio networks

characterization of the antenna and enhance the performance Spectrum Broker

per client. FPGA is capable of converting low-speed signal Licensed band I
processing to high speed, which helps in real-time processing
of data. Modern FPGAs feature 300-400 MHz parallel pro- Primary
Network
CR network
cessing ability. Acess
access
CR base station

Licensed band II
B. Standardization of Technology CR ad
hoc
access
For the next phase of development and verification, a proof- CR user

of-concept platform i.e testbed needs to be designed to operate

Primary User
Masssive MIMO under real life conditions. Testbeds can
be helpful in overall understanding of the system and can Primary Networks
Cognitive radio Cognitive radio
mature the technology for standardization [12]. But designing network (without
infrastructure)
network (with
infrastructure)
a testbed with complex computation capability and real time
operation has been challenging with the existing hardware Fig. 6: Cognitive Radio(CR) framework for 5G.
resources. resources from the primary system. Fig.6 highlights the cogni-
MIMO testbed over an FPGA: Finding out the channel tive radio framework that ensures network access among users
properties and the optimal transmission technology of the of licensed and unlicensed spectrum band. In CR network
MIMO system is a subject that is being researched by re- access, CR users communicate through the CR base-station.
searchers worldwide. One of the concerning areas is signal When there is a lack of CR network infrastructure, CR users
propagation scheme, which can be implemented over a testbed share resources through ad-hoc connections in both licensed
before actually putting into operation. Handling increased data and unlicensed spectrum bands. In CR network, the secondary
over multiple channels in multiple antenna system of MIMO system senses the white spaces in frequency spectrum, time
over the testbed poses a challenge in designing such processor. and potential geographic area that stay underutilized by the
Specific processor that can handle parallel processing at a primary system and CR allocates those white spaces to the
faster rate are preferred. FPGAs are capable of handling secondary system without interfering the performance of pri-
increased data transmitted through multiple antennas due to mary users. Through spectrum sensing and maintaining the
its parallel processing capability. FPGAs are advanced signal overall geographic database, the spectral white spaces can be
processing devices which can process the transmitted and found .
received data over the virtual parallel pool. The high-speed CR is a complex computational networking system which
analogue to digital (ADC) and Digital to analogue (DAC) performs various digital signal processing algorithm on various
converter ports can be used for faster delivery of data to the platforms. The general purpose processors provide us with
output circuitry. greater flexibility but don’t provide better performance. How-
ever the application specific integrated circuits provide great
VI. C OGNITIVE R ADIO FRAMEWORK FOR 5G performance but lack flexibility. FPGAs are the best option as
The potential increase in the number of users in a mobile they provide both flexibility and performance along with low
network and the requirement of high data rates pushes 5G power consumption.
to work within a mixed ecosystem of micro and macrocells. Cognitive Radio platform using FPGA: Various researchers
Further, the standalone base stations will be replaced by have worked on developing a cognitive wireless platform
a centralized system as per availability of high bandwidth using FPGA as hardware. A cognitive radio known as Agile
backhaul network. So adequate amount of spectrum allocation radio is developed by Kansas University researchers which
is required to be performed efficiently. embed Linux, FPGA, RF front-end and antennas to work
The radio-frequency spectrum is part of nature, so the on dynamic spectrum allocation [13]. WINLAB at Rutgers
licensing and regulation of the spectrum is handled by the gov- University has also developed a network-oriented cognitive
ernment. However, fixed spectrum allocation by government radio which focuses on multi-band frequency operation. It
bodies leads to underutilization of resource when a certain uses an embedded OS for controlling the operation along with
spectrum range is idle. So accessing this under-utilized spec- Xilinx FPGA for processing baseband signals [14].
trum is a challenging problem than the spectrum scarcity itself, At Trinity College, a cognitive radio platform is developed
since failing to utilize existing spectrum. Here, Cognitive on the basics of programmability of the software-defined
Radio (CR) has the ability to identify the under-utilization network. The Implementing Radio in Software(IRIS) provides
of spectrum and to allocate the under-utilized spectrum to the a highly reconfigurable software radio platform [15]. It is made
secondary users that are not being served. This can also reduce up of various digital signal processing components which
the burden on single network thus providing ubiquitous high- can perform various distinctive tasks. Linux has to be ported
speed communication channel. into the Xilinx FPGA to control the operations. The DSP
CR empowers progressively unique and adaptable spectrum operations can be implemented in the logic fabric of FPGA
access in which the secondary system can get the spectrum as the hardware level implementation is always faster than the
 8

software-defined operation. The static part of the FPGA i.e [14] Rutgers Winlab. (2007) Network centric cog-
the Programming Subsytem (PS) of the FPGA is used to run nitive radio platform. [Online]. Available:
http://www.winlab.rutgers.edu/pub/docs/focus/Cognitive-Hw.html
the Linux OS. A composer generates the bitstreams for FPGA [15] Lotze, J., et al. “An FPGA-Based Cognitive Radio Framework.” IET
to reconfigure and implement various radio component and Irish Signals and Systems Conference (ISSC 2008), 2008.
also directs some other radio component implementation on
the PowerPC processor [15].

VII. C ONCLUSION
This article gives an overview of 5G technology and integra-
tion of various hardware and software-defined technologies to
meet the requirement of future mobile communication. Also,
it explains how FPGA can be used to create various building
blocks of 5G infrastructure. The invention of hybrid computing
Vinay Chamola is an Assistant Professor at Birla Institute of Technology
platforms, such as the FPGA-based hardware acceleration & Science (BITS), Pilani, India. He received his B.E. (2010) and M.E.
approach, shows promise for the implementation of standalone (2013) degree from BITS, Pilani and PhD (2016) from National University
energy efficient NFV and C-RAN architectures. An efficient of Singpaore (NUS), Singapore. He has co-authored more than 30 papers in
reputed Journals and Magazines like IEEE TCOM, IEEE TVT, IEEE IoTJ,
real time signal processing architecture can be designed to IEEE TSE, IEEE JSAC, IEEE Communications Magazine etc, and serves
charecterize the massive MIMO. Cognitive Radio provides as a guest editor in Computer Communication and few other Journals. His
broad range of applications to run while supporting high data research interests include IoT security, Blockchain, 5G network management,
VANETs, UAV Nets and BCI.
traffic. It’s performance can be enhanced by using FPGAs to
orchestrate and combine the operations of small cells along
with micro and macro cells, so as to efficiently allocate the Sambit Patra is a Masters student in BITS-Pilani. Pilani, India. He did his
spectrum to avoid under-utilization of resources. B.Tech (2018)from Biju Patnayak University of Technology, Orissa, India.

VIII. ACKNOWLEDGEMENT
Neeraj Kumar is an Associate Professor in Computer Science & Department,
This work is supported by DST-SERB (Science and Engi- Thapar Institute of Engineering & Technology, Patiala. He received his Ph.D.
in CSE from SMVD University, Katra (J & K), India, and was a postdoctoral
neering Research Board (SERB)) funding under Project Grant research fellow in Coventry University, Coventry, UK. He is an internationally
File no. ECR/2018/001479. renowned researcher in the areas of VANET, CPS Smart Grid, IoT Mobile
Cloud computing, Big Data, and Cryptography.

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