Lecture 4

Status Register

• The STATUS register contains the arithmetic status of the ALU, the RESET status
and the bank select bit for data memory.
• As with any register, the STATUS register can be the destination for any
instruction. If the STATUS register is the destination for an instruction that affects
the Z, DC or C bits , then the write to these three bits is disabled. These bits are
set or cleared according to device arithmetic and logic results.
• Only the BCF, BSF, SWAPF and MOVWF instructions should be used to alter
the STATUS register because these instructions do not affect any status bit. The C
and DC bits operate as a borrow and digit borrow out bit, respectively, in
subtraction.

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Status Register

bit 0 C: Carry/borrow bit

(ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

bit 1 DC: Digit carry/borrow bit

(ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

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Status Register

bit 3 PD : Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

bit 4 TO : Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred

bit 5 RP0 : Register Bank Select bits (used for direct addressing)
1 = Bank 1 (80h - FFh)
0 = Bank 0 (00h - 7Fh)

bit 7-6 Unimplemented: Maintain as ‘0’

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Option Register

The OPTION_REG register is a readable and writable register which contains various control
bits to configure the
• Timer (TMR0)/ Watchdog (WDT) prescaler,
• the external INT interrupt, TMR0, and
• the weak pull-ups on PORTB.

bit 0:2 PS0:PS2: Prescaler Rate Select bits

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

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Option Register

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
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INDF and FSR Registers

The INDF register is not a physical register. Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit
STATUS<bit 7>), as shown in the figure below. However, IRP is not used in the PIC16F8X.

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INDF and FSR Registers

EXAMPLE : INDIRECT ADDRESSING

• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
• A read of the INDF register will return the value of 10h
• Increment the value of the FSR register by one (FSR = 06)
• A read of the INDF register now will return the value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register
indirectly results in a no-operation (although STATUS bits may be affected).

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INDF and FSR Registers

EXAMPLE: Write An assembly program to clear RAM locations 20h - 2Fh

using indirect addressing.

MOVLW 20h ;initialize pointer

MOVWF FSR ; to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR ;increase pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;NO, clear next
NOP ;YES, do nothing

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EEPROM Memory in PIC16F84
microcontroller

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2.1- Data EEPROM Memory
• PIC16F84 has 64 bytes of EEPROM memory
locations on addresses from 00h to 63h
• those can be written to or read from (read/write
memory).
• The most important characteristic of this memory is
that it does not lose its contents during power supply
turned off.

In practice, EEPROM memory is used for storing

important data or some process parameters.
EEPROM memory is placed in a special memory space and can be accessed through
special registers.
These registers are:
• EEDATA at address 08h, which holds read data or that to be written.
• EEADR at address 09h, which contains an address of EEPROM location being
accessed.
• EECON1 at address 88h, which contains control bits.
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EECON1 Register

EECON1 at address 88h, which contains control bits that control the read/write operation on
EEPROM memory.
• EECON1 is the control register with five low order bits physically implemented.
• The upper-three bits are nonexistent and read as '0's.
• Control bits RD and WR initiate read and write, respectively.
• The WREN bit, when set, will allow a write operation.
• The WRERR bit is set when a write operation is interrupted by a MCLR reset

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read
0 = Does not initiate an EEPROM read

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EECON1 Register
bit 1 WR: Write Control bit
1 = Initiates a write cycle.
0 = Write cycle to the EEPROM is complete

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles
0 = Inhibits write to the EEPROM

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated
0 = The write operation completed

bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started

bit 7-5 Unimplemented: Read as '0'

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 Reading the EEPROM Data Memory

Steps to read a data memory location,

• the user must write the address to the EEADR register
• and then set (= 1) control bit RD (EECON1<bit 0>).
• The data is available, in the very next cycle, in the EEDATA
register; therefore it can be read in the next instruction.
• EEDATA will hold this value until another read or until it is
written to by the user (during a write operation).

EXAMPLE : Read EEPROM memory location 24h and move it to the

W register

BCF STATUS, RP0 ; go to bank 0

MOVLW 24h ; Initiates the address
MOVWF EEADR ; Address to read
BSF STATUS, RP0 ; Bank 1
BSF EECON1, RD ; EE Read
BCF STATUS, RP0 ; Bank 0
MOVF EEDATA, W ; W = EEDATA

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 Lecture 2 page 14
Writing to the EEPROM Data Memory

To write an EEPROM data location, the user must

• first write the address to the EEADR register
• and the data to the EEDATA register.
• Enable Write WREN bit in (EECON1<bit 2>).
• Start writing WR bit in (EECON1<bit 1>).
• Disable the interrupt during the write operation (Recommended).

EXAMPLE : write AAh to EEPROM location 24h

Bank 0 Bank 1
BCF STATUS, RP0 ; Bank 0
BCF INTCON, GIE ; Disable INTs. Lecture 2 page 16
MOVLW AAh ; Move data (AAh) to W
MOWWF EEDATA ; Move W register to EEDATA register
MOVLW 24h ; Move data (24h) to W register
MOVWF EEADR ; Move W register to EEDATA register
BSF STATUS, RP0 ; Bank 1
BSF EECON1, WREN ; Enable Write .
BSF EECON1, WR ; start Write
BSF INTCON, GIE ; enable INTs. W Reg
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 Homework 1 (30/3/2020)

• Assume EEPROM memory location (00h) contain data (AA h),

Write a program to move the content of location (00h) to
location (63h), and write data (BBh) in location (00h).

EEPROM memory EEPROM memory

00h AAh 00h BBh

63h 63h AAh

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bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

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 Lecture 2 page 14
EEPROM Write Verify
Generally, the EEPROM write failure will be a bit
which was written as a ’0’, but reads back as a ’1’ or
vice versa.

EXAMPLE : write AAh to EEPROM location 24h and

check if the writing is
successfully complete.

start BCF STATUS, RP0

MOVLW 24h
MOVWF EEADR
MOVLW AAh
MOWWF EEDATA
BSF STATUS, RP0 Lecture 2 page 16
BSF EECON1, WREN
BSF EECON1, WR
EEDATA
BSF EECON1, RD
AAh
BCF STATUS, RP0
SUBWF EEDATA, W
BTFSS STATUS, Z W Reg
GOTO start
Continue the code 24h
EEADR
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Homework 2 (6/4/2020)
Can we use the EECON1 register to verify the write operation without
the need to the status register ?
If so, how?

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