Analog Design Journal Signal Chain

How to debug I2C through waveform analysis

By Duy “Bobby” Nguyen
I2C Applications Engineer
Introduction times, rise-time issues can typically be resolved by using a
2
There’s a reason why I C is one of the most common stronger pullup resistor (meaning one with a lower resis-
onboard communication protocols. Designers prefer I2C tance value). The I2C protocol dictates the maximum
because it only requires two wires: a data line (SDA) and allowed rise times based on the maximum clock frequency
a clock line (SCL). These lines allow multiple devices to used. In version 2.6 of the I2C specification, the maximum
communicate by sharing the connections. The simplicity rise time for standard mode and fast mode is 1,000 ns and
of I2C, however, does not mean that it is without its 300 ns, respectively.
challenges. Figure 1 shows an I2C SCL signal that has an issue with
I2C communication issues include slow rise times, cross- the rise time. The SCL never reaches 100% of VCC. The
talk (more importantly, false edges on the SCL line), slow rise time affects the valid time of a high period
higher-than-intended low-level output voltages (VOL), and because it takes longer for the signal to reach 70% of VCC
unintended contention and large undershoots. These (3.5 V in this case, where VCC is 5 V). In Figure 1, the rise
issues can lead to I2C communication failure and device time (for standard mode) is being violated because the
failure in some cases. maximum allowed is 1,000 ns, while the rise time is 2,500 ns.
Understanding the challenges and learning proper Some I2C devices are edge-rate triggered and require a
debugging procedures, such as I2C waveform analysis, can fast-enough slew rate to detect a rising pulse. In this case,
help pinpoint communication issues while working with an having a slow rise time could affect the detection of a
I2C bus. This article explores common I2C operational rising edge.
challenges and how to debug them through waveform In rare cases, extremely fast rise/fall times could falsely
analysis. trigger an electrostatic discharge (ESD) cell on the SDA/
SCL pin of edge-rate-triggered I2C devices and latch the
Slow rise times SDA/SCL lines low until the ESD cell recovers. This situa-
Rise times usually present problems when they are too tion usually occurs when an I2C slave rated for 400 kHz is
slow, potentially resulting in the signal never reaching the on an active I2C bus that is operating at 1 MHz or faster.
high-level input voltage (VIH) threshold in time. Since bus False triggers are a result of improper I2C slave placement/
capacitance and pullup resistors directly influence rise isolation; do not place 400-kHz slaves on I2C buses operat-
ing faster than 400 kHz.

Figure 1. A heavily capacitive-loaded bus with weak pullup resistors

B A
A 33.50 µs 3.500 V
B 31.00 µs 1.540 V
SDA Signal ∆2.500 µs ∆1.960 V
(1 V/div)
SCL Signal
(1 V/div)

24

Time (10 µs/div)

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Analog Design Journal Signal Chain

Crosstalk Figure 2. An example of minor crosstalk that only

Usually seen on the SDA data line marginally affects I2C signal integrity
(although it can occur on the SCL
line as well), crosstalk is a result of
fast rise/fall times on the SCL or SDA Signal
SDA line coupling onto the para- (1 V/div)

sitic capacitance between the SDA SCL

trace and the SCL trace. Signal
Figure 2 shows the SDA and (1 V/div)
2
SCL lines of an active I C-bus
communication where crosstalk is
visible during the rising and falling
VIL
edges. In Figure 2, the crosstalk
does not affect the overall signal
integrity because the data line
VIL
(SDA) stays above VIH or below
VIL during the middle of the clock’s
high period (when the data is actu-
ally sampled). Time (5 µs/div)
Crosstalk on SDA/SCL can be
problematic if there are buffers/
translators with rise-time accelerators on the bus. Devices lines as low. Figure 3b shows VOL higher than VIL but also
with rise-time accelerators can trigger on a rising edge lower than VIH. The SDA/SCL line in Figure 3b is in an
above the threshold of the low-level input voltage (VIL). In unknown state, which is not allowed in I2C. The signal
2 may be interpreted by the receiving device as a low or
version 2.6 of the I C specification, VIL is defined at 30%
of VCC. Thus, any crosstalk that results in a rising edge high, depending on the design of the device’s input stage.
above VIL will result in engaging the rise-time accelerators. To prevent this unknown-state situation, using a weaker
In some cases, the SDA line can recover, but the SCL line pullup resistor may help lower the VOL. However, if the
will end up generating a false rising edge to the slave and rise time is the limiting factor, then it will not be possible
may actually end up glitching the slave’s state machine, to modify the pullup resistor. In such cases, the easiest
which can result in incorrect data or even a stuck bus. solution would be to introduce an I2C buffer to the system.
Adding additional bus capacitance on the SDA/SCL line
can help, but the amount of capacitance that can be added
is limited because of the maximum capacitance listed in Figure 3. Examples of VOL for SDA and SCL lines
the I2C specification (400 pF for both standard mode and
fast mode in version 2.6 of the I2C specification). The best
approach to resolving crosstalk is to place small series VCC
resistors on the SDA/SCL lines and to minimize the para- VIH
sitic bus capacitance between the SDA and SCL traces.
VIL
VOL levels are higher than intended VOL
VOL < VIL
A high VOL can generate issues with a slave/master inter- Time
preting a signal as a logic low. Some I2C slaves (legacy
ones in particular) have weak pulldown field-effect tran- (a) Correct VOL signal
sistors (FETs) and generate a high VOL, which may not
meet the VIL standard (especially at low VCC, such as 1.8-V
VCC
or 1-V logic). Other times, choosing pullup resistors that
VIH
are too strong (i.e., values that are too small) can result in VOL > VIL
VOL
VOL levels higher than VIL, putting the line in an unknown VIL
state.
Figure 3 shows visual representations of VOL and VIL. In Time
Figure 3a, VOL is below the VIL threshold, so the device
receiving the data can properly interpret the data/clock (b) Incorrect VOL signal from a legacy device

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Analog Design Journal Signal Chain

Figure 4. Contention occurring in a push-pull design

SCL Signal
(1 V/div)

24
SDA Signal
(1 V/div)

Time (100 µs/div)

Unintended contention Other times, unintended contention occurs when the

Unintended contention occurs when a P-channel FET PFET of the rise-time accelerator and the NFET of a
(PFET) and N-channel FET (NFET) are both turned on master/slave are on at the same time.
at the same time, one pulling the line high while the other In Figure 5, the rise-time accelerator is engaged,
pulls low. This typically results in a very high VOL, which meaning that the PFET is actively driving the line high
usually falls between the gray zone of digital logic while the slave acknowledges (the NFET drives low),
(between VIL and VIH). In most systems, unintended which results in unintended contention between the rise-
contention is never a concern because the master is meant time accelerator’s PFET and the slave’s NFET. The
to be an open-drain and therefore cannot generate this contention ends when the accelerator disengages.
kind of contention state. However, some designers do not
design their I2C bus as an open-drain and use push-pull Figure 5. Buffer with a rise-time accelerator
output stages instead, which can result in unintended causes contention on an I2C bus
contention.
Unintended contention is usually easy to spot, as the
SDA and SCL lines on the oscilloscope will appear as
square waves due to the strong pullup of the PFET.
In Figure 4, a master uses a push-pull driver that SDA_OUT
(0.5 V/div)
produces SDA signals with fast rising edges. When the
slave goes to ACK, the active PFET of the master opposes
the active NFET of the slave, resulting in a contention
state that generates a high VOL and IOL. The high IOL can
SDA_IN
be enough to damage the PFET and NFET, as they are (0.5 V/div)
typically not designed to sink/source too much current. As
a result, push-pull architectures should not be connected Time (400 ns/div)
to bidirectional open-drain slaves without careful
consideration.

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Analog Design Journal Signal Chain

Figure 6. Undershoots occurring on the SCL line

SCL Signal (1 V/div)

Time (4 µs/div)

Large undershoots Conclusion

Large undershoots can occur when there is a large amount Problems that cause signal-integrity concerns, such as
of parasitic inductance on the line in addition to fast fall higher-than-intended VOL voltages, crosstalk and slow rise
times. This is more common with cable transmission, but times, are usually easy to spot and result in an I2C bus
is occasionally observed on printed circuit board (PCB) that typically won’t receive acknowledges (ACKs). The
transmissions. The problem with undershoots is that if serious problems are those that do not immediately result
large enough, they may violate the absolute maximum in failure. Such problems could be a result of unintended
voltage allowed on the pin (as specified in the device’s contention on the bus or large undershoots, which can
datasheet) and cause device failure. In many cases, the cause devices failure over time. It is important to be able
device does not fail immediately and could continue to to recognize these kinds of I2C issues before they end up
work even after thousands of undershoots. in the end application of a user.
In Figure 6, the undershoots swing to –0.5 V. This
voltage is beyond the absolute maximum allowed for the
device, which has an absolute maximum allowable thresh-
old of –0.3 V. Such large undershoots can cause damage to
the device over time and needs correction.
In the case of undershoots, if the fall time cannot be
slowed down enough to prevent an undershoot from
occurring (with a small series resistor) and if it is not
possible to further minimize the parasitic inductance, then
a clamping diode (such as a Schottky diode) is necessary
to minimize the undershoot to be within datasheet
specifications.

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Analog Design Journal

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