Design and Calibration of Integrated

PLL Frequency Synthesizers

Fredrik Jonsson

Doctoral Dissertation
KTH - Royal Institute of Technology
Stockholm, Sweden, April 2008
TRITA-ICT/ECS AVH 08:03
ISSN 1653-6363
ISRN KTH/ICT/ECS AVH-08/03--SE

Akademisk avhandling som med tillstånd av Kungliga Tekniska högskolan framlägges

till offentlig granskning för avläggande av Teknologie Doktorsexamen i Komponent
och Kretselektronik måndagen den 28 april 2008 kl 13.15 i sal D, Forum, Kungliga
Tekniska högskolan, Isafjordsgatan 39, Kista.

Fredrik Jonsson, April 2008

This document is created using PlainDoc markup language and typeset using LaTeX
Tryck: Universitetsservice US-AB, Kista
Abstract

Thanks to its ability to generate a stable yet programmable output frequency, Phase Locked
Loop (PLL) frequency synthesizers are found in most modern radio transceivers. All prac-
tical PLL implementations suffer from unwanted frequency components such as phase-
noise and spurious tones, and since these components affect system performance they
must be predicted and minimized.
This thesis discuss the design and implementation of fully integrated PLL circuits. Tech-
niques to predict system performance are investigated. The strongly non-linear opera-
tion of PLL building blocks are analyzed, using both analytical and numerical methods.
Techniques to reduce impact of interferer down-conversion and noise folding are sug-
gested. Methods to perform automatic calibration in order to make circuits less sensitive
to process variations are proposed. The techniques are verified through a number of PLL
implementations.
The design and implementation of a transceiver targeting a dual band IEEE 802.11 a/b/g
wireless LAN operation is discussed. The circuit use two PLL:s operating at 1310 to 1510
MHz and 3.84 GHz respectively. Noise contributions of various PLL building blocks and
their impact on over all system performance are analyzed. The combined integrated phase
noise is below -34 dBc, and measured transceiver Error Vector Magnitude (EVM) is better
than 2.5 dB in both the 2.4 and 5 GHz bands.
A low power frequency synthesizer targeting Frequency Shift Keying applications such
as ZigBee and BlueTooth is presented. The synthesizer use open-loop direct modulation
of the carrier, but unlike conventional implementations, the proposed synthesizer is open
both when transmitting and receiving data. This allows the use of a small area on-chip
loop filter without violating noise or spurious requirements. To handle the frequency
drift normally associated with open-loop implementations, a low-leakage charge-pump is
proposed. The synthesizer is implemented using a 0.18µm CMOS process. Total power
consumption is 9 mW and the circuit area including the VCO inductors and on-chip loop-
filter is 0.32mm2 . Measured leakage current is less than 2 fA.
A small area amplitude detector circuit is proposed. The wide-band operation and small
input capacitance make the circuit suitable for embedding in an RF system on-chip, al-
lowing measurement of on-chip signal levels and automatic calibration.

iii
iv

Finally an oscillator topology reducing the phase noise in voltage controlled oscillators
is suggested. By using on-chip decoupling and an amplitude control circuit to adjust
oscillator bias, the impact of current source noise is eliminated. The theoretical phase
noise is reduced 3.9 dB compared to a conventional LC oscillator using the same bias
current.
Acknowledgments

The road towards this PhD have been long and anything but straight, but nevertheless a
very interesting journey.
When I started, RF design using CMOS was still uncommon. Few commercial products
were available and only a handful measurement results had been published. Publications
had to be requested from the library by mail, since on-line databases were not yet com-
plete.
Today RF CMOS is used in products ranging from high performance communication
equipment to cheep toys, and a search for "VCO" on IEEE eXplore using my wireless
connected laptop return 3118 publications.
It has been interesting to be part of this development.
I will take this opportunity to thank my supervisor prof. Håkan Olsson for all support
during the years. Thanks for accepting me to the program in the first place, and also
for allowing me to come back and finish. Special thanks also goes to my co-supervisor
prof. Li-Rong Zheng. My former supervisor prof. Mohammed Ismail also deserves my
gratitude for his enthusiasm and encouragement, and also for giving me valuable insights
into the realities of busyness and academia.
I would also like to thank and express my appreciation to my friends and colleges at KTH
with whom I have had many interesting and fruitful discussions, and who have also made
my time at the department more enjoyable: Jian Chen, Martin Gustafsson, Jad Atallah,
Saúl Rodríguez Dueñas, Delia Rodríguez de Llera González, dr Ana Rusu, Liang Rong
and Wang Peng. It is a pleasure having you around. Thanks also to my former colleges
Håkan Magnusson, Andreas Kämpe, Dr. Hong-Sun Kim, Dr. Adiseno, Ernst Otto, Dr.
Yue Wu, Dr. Xiaopeng Li, Dr. Wim Michelson, Dr. Steffen Albrecht and Dr. Adam Strak.
Since my first research project was spun off in the startup company Spirea AB, I made
a detour into industry before finishing this work. Locking back I don’t regret this devel-
opment, since the lessons learned from taking a research project into a commercial prod-
uct gave many valuable experiences. I thank my former colleges at Spirea: Dr. Martin
Sandén, Anders Brolin, Daniel Wallner, Jenny Hanze, Daniel Björk, Jonas Jönsson, Peter
Olofsson, Yuxin Gou, Dr. Rami Ahola, Isto Hyyrylainen, Timo Hakala, Aki Friman, Tu-
ula Makiniemi, Timo Lagerstam, Dr. James Wilson, Dr. Kishore Rama Rao, Dr. Adem

v
vi

Aktas, Dr. Laurent Noguer, Karol Krol, Dr. Mona Hella and Ahmed Hassan. Thanks for
the fantastic work we did, and all the fun we had together. I would also like to thank the
venture capitalist who invested in Spirea, funding what can be characterized as the most
expensive course I have ever attended.
After Spirea I got the opportunity to join a few shorter projects. At DiBcom I finally got
to see one of my circuits go into production, and I will never forget the satisfaction of
being able to walk into a store and buy a product having my circuits inside. I also got the
opportunity to work abroad for Maxim integrated products. The experience from working
in a large multinational company was a good complements to lessons learned in academia
and startup companies. My warmest thanks goes to my former colleges.
A special thanks also to Magnus Lindström for hosting the CVS server where I store the
data for this thesis, and for always helping out when I have computer related problems.
Finally I would like to thank my family, my mother, my father and my sisters and my
girlfriend for your love and support, and for always encouraging me. Mom, I miss you
every day. Thanks also for sparking my interest in electronics by giving me the electron-
ics experiment box I received when I was 6 years old. I would also like to express my
appreciation to my aunts for allowing me to check the conductivity of the flowers using
one of said experiments. I hope you have been able to remove all wires by now.
Contents

Abstract iii

Acknowledgments v

List of appended papers xi

Related work not included xiii

Summary of appended papers xv

1 Introduction 1
1.1 PLL operation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Transceiver overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 PLL performance parameters 13

2.1 Frequency range and accuracy . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Spurious tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4 Phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5 Phase noise impact on system performance . . . . . . . . . . . . . . . . 25
2.6 Phase noise in OFDM system . . . . . . . . . . . . . . . . . . . . . . . . 27
2.7 Amplitude and phase matching . . . . . . . . . . . . . . . . . . . . . . . 32
2.8 Other PLL design considerations . . . . . . . . . . . . . . . . . . . . . . 33

vii
viii CONTENTS

3 PLL modeling and simulation 37

3.1 PLL type and order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2 Linear models of PLL building blocks . . . . . . . . . . . . . . . . . . . 40
3.3 Linear PLL model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4 Discrete time PLL model . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.5 Numerical PLL models . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.6 Mixed-signal PLL model . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.7 Simulating PLL performance . . . . . . . . . . . . . . . . . . . . . . . . 54

4 PLL noise analysis 59

4.1 Noise in digital circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2 Phase Frequency Detector . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.3 Folding of noise and interferers in Charge-Pump . . . . . . . . . . . . . . 64
4.4 Oscillator phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.5 Reference oscillator noise . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.6 Noise in ∆Σ noise shaper . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.7 Linear PLL noise model . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.8 Simulating PLL noise using circuit simulator . . . . . . . . . . . . . . . 76
4.9 Discrete time and numerical noise simulation . . . . . . . . . . . . . . . 80
4.10 PLL noise optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5 Oscillators 89
5.1 Oscillator principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.2 CMOS LC-VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.3 Pulse wave LC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.4 Comparison LC and pulse wave VCO . . . . . . . . . . . . . . . . . . . 118

6 Conclusion 121

References 123
CONTENTS ix

A Calculation of loop-filter components 133

A.1 Calculation of frequency of pole and zero . . . . . . . . . . . . . . . . . 135
A.2 Calculation of component values . . . . . . . . . . . . . . . . . . . . . . 136

B Behavioral models 139

B.1 VCO behavioral model . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
B.2 Divider behavioral model . . . . . . . . . . . . . . . . . . . . . . . . . . 140
x CONTENTS
List of appended papers

1. Fredrik Jonsson and Håkan Olsson, "A low leakage open loop frequency synthesizer
allowing small area on-chip loop-filter" Manuscript
2. Fredrik Jonsson and Håkan Olsson. "An RF detector for on-chip amplitude measure-
ments" Electron. Lett. 2004, 40, (20), pp. 1239-1240
3. Fredrik Jonsson and Håkan Olsson, "A Quadrature Oscillator using automatic phase
and amplitude tuning" Accpted ISCAS 2008
4. Rami Ahola, Adem Aktas, James Wilson, Kishore Rama Rao, Fredrik Jonsson, Isto
Hyyryläinen, Anders Brolin, Timo Hakala, Aki Friman, Tuula Mäkiniemi, Jenny Hanze,
Martin Sanden, Daniel Wallner, Yuxin Guo, Timo Lagerstam, Laurent Noguer, Timo
Knuuttila, Peter Olofsson and Mohammed Ismail "A single-chip CMOS transceiver
for 802.11a/b/g wireless LAN" IEEE J. Solid-State Circuits, vol 39, pp 2250- 2258,
Dec. 2004.

5. Fredrik Jonsson, Rami Ahola et. al. "A Single Chip 802.11 a/b/g WLAN Tranceiver".
Proc. 23rd IEEE Norchip Conference, 8-9 Nov. 2004, Oslo. pp. 233 - 236
6. Fredrik Jonsson and Håkan Olsson, "Folding of Noise and Interferers in PLL Charge-
Pumps" Manuscript
7. Fredrik Jonsson, Håkan Olsson, "Techniques to Reduce Folding of Noise and Interfer-
ers in PLL Charge-Pump" Manuscript
8. Fredrik Jonsson, Martin von Haartman, Martin Sanden, Mikael Ostling and Mohammed
Ismail "A Voltage Controlled Oscillator with Automatic Amplitude Control in SiGe
Technology" Proc. 19th Norchip Kista 12-13 November 2001, pp 28-33.

9. Jian Chen, Fredrik Jonsson, Håkan Olsson, Li-Rong Zheng, Dian Zhou, "A Current
Shaping Technique to Lower Phase Noise in LC Oscillators" Manuscript

xi
xii
Related work not included

Publications

1. F. Jonsson. 1,8GHz Low Voltage VCO in Silicon Bipolar Technology. Nordiskt Radio
Symposium, Saltsjobaden October 1998, pp 231-234.
2. Yue Wu, Hong-Sun Kim, Fredrik Jonsson, Mohammed Ismail, and Håkan Olsson
"Nonlinearity Analysis of a Short Channel CMOS Circuit for rf IC Applications" Pro-
ceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large
Scale Integration: Systems on a Chip Klüwer 1999, pp 61-68.
3. Yue Wu, Fredrik Jonsson, Hong-Sun Kim, Mohammed Ismail and Håkan Olsson
"Analysis of Non-linearities of CMOS Low Noise Amplifier" Norchip, Oslo Novem-
ber 1999, pp 189-196.
4. Chien-Hsiung Feng, Fredrik Jonsson, Mohammed Ismail and Håkan Olsson. "Analysis
of Non-linearities in rf CMOS Amplifiers ICECS’99" Proc. The 6th IEEE International
Conference on Electronics, Circuits and Systems, Pafos, Cyprus 5-8 sept. 1999, vol I,
pp137-140.
5. Xiaopeng Li, Fredrik Jonsson, H. Olsson and M. Ismail. "A High-Speed Low-Power
architecture for GHz CMOS Dual-Modulus Prescaler". International Analog VLSI
Workshop, IEEJ Stockholm 2000, pp 6-9
6. Martin Sanden, Fredrik Jonsson, M. Ostling, O. Marinov and M. J. Deen "Up-Conversion
of Device 1/f Noise to Phase Noise in Voltage Controlled Oscillators". Proc 16th
International Conference on Noise in Physical Systems and 1/f Fluctuations, ICNF
Gainesville FL 2001. pp 449-502
7. Fredrik Westman, Fredrik Jonsson, Tommy Oberg, Christer Hedqvist and Ahmed He-
mani "A Robust CMOS Bluetooth Radio/Modem System-on-Chip" IEEE Circuit and
Systems Magazine. Nov. 2002 pp 7-9, 16
8. Adem Aktas, Fredrik Jonsson, Rami Ahola and Mohammed Ismail. "A 4 Ghz 0.18um
CMOS PLL Frequency Synthesizer with Wide-Band VCO for Multi-Standard Wire-
less Applications". Norchip 2003, Riga November 2003. pp 248-251

xiii
 xiv

9. Rami Ahola, Adem Aktas, James Wilson, Kishore Rama Rao, Fredrik Jonsson, Isto
Hyyrylainen, Anders Brolin, Timo Hakala, Aki Friman, Tuula Makiniemi, Jenny Hanze,
Martin Sanden, Daniel Wallner, Yuxin Gou, Timo Lagerstam, Laurent Noguer, Timo
Knuuttila, Peter Olofsson and Mohammed Ismail. "A Single Chip CMOS Transceiver
for 802.11 a/b/g WLANs". IEEE International Solid-State Circuits Conference, ISSCC
Feb. 2004 pp 92,515
10. Jian Chen, Fredrik Jonsson, Li-Rong Zheng, Diand Zhou, "Device Sizing during Dif-
ferencial Pair LC Oscillator Design". IEEE Norchip 2007, Aalborg Nov. 2007. ISBN
1-4244-1517-9

Patents

1. Fredrik Jonsson, A frequency synthesizer and a method for synthesizing a frequency,

Patent WO0235705, AU1113902, SE518078.
2. Fredrik Jonsson, A prescaler comprising a pulse swallow circuit, Patent WO0235706,
AU9618801, SE519472.
3. Fredrik Jonsson, Voltage controlled oscillator, Patent WO0227937.
4. Fredrik Jonsson, Quadrature Phase Control Loop, Patent WO03088497, SE0201159
5. Fredrik Jonsson, Low Leakage Charge-Pump, Patent WO03088494, SE0201158
Summary of appended papers

Paper 1. The implementation of a A 2.4-2.5 GHz integer-N PLL targeting BlueTooth

applications is presented. The synthesizer use open-loop frequency modulation of the car-
rier. Unlike conventional implementations, the proposed synthesizer is open both when
transmitting and receiving data. Leakage paths in the oscillator control node are investi-
gated, and techniques to minimize the frequency drift is proposed. This allows the use of
a small on-chip PLL filter. The methods are covered by patent WO03088494, SE0201158
and WO0227937. A test circuit is designed and implemented. Measured frequency mod-
ulation and drift is presented.
The main author is responsible for all work related to this publication except measure-
ments.
Paper 2. A low current and small area amplitude detector circuit is presented. The flat
frequency response and small load capacitance makes the circuit suitable for embedding
in RF systems, allowing on-chip measurement of signal levels. A theoretical description
of the circuit, along with simulation and measurement results are presented.
The main author is responsible for all work related to this publication except measure-
ments.
Paper 3. A calibration technique to reduce the phase and amplitude imbalance in quadra-
ture oscillators is presented. By using the amplitude detectors presented in paper 2, ampli-
tude differences between the oscillator cores is detected and compensated. The technique
was used in the Spirea Bluetooth transceiver BlueTraC to reduce the impact of load and
layout mismatch. The technique is also covered by patent WO03088497 and SE0201159.
The author of this thesis is the inventor of the technique and did all theoretical work and
the circuit implementation.
Paper 4. The Wireless LAN circuit TripleTraC designed at Spirea AB was presented at
both ISSCC and later in JSSC in 2004. The work describes a dual band triple mode Wire-
less LAN transceiver fully compliant with the 802.11a, b and g standards implemented in
0.18 um CMOS. The transceiver includes transmit and receive paths in both the 2.4 and 5
GHz bands. The circuit also includes an automatic frequency calibration circuit.

xv
xvi

The author of this thesis was responsible for the frequency generation and phase noise
optimization of the two local oscillators in the transceiver, and was also responsible for
a complete redesign of the PLL circuit blocks including design of oscillators, prescalers,
charge-pump and loop-filters. Due to very stringent frequency stability requirement, a
through investigation and redesign of oscillator grounding and supply regulation was per-
formed. The author was also responsible for PLL behavioral simulations, system level
verifications, and phase noise measurements.
Paper 5. This publication describes the same transceiver as presented in Paper 4, but is
focusing more on the phase noise optimization and PLL implementations.
Paper 6. In this paper the impact of noise folding in the PLL charge-pump is investigated.
A charge-pump experience natural sampling, and due to the narrow pulse width, noise and
interferers at high frequency will be down-converted to a frequency within the PLL band-
width. The down-converted signal modulates the oscillator, creating sidebands around the
PLL output. The paper describes the theoretical derivation of noise down-conversion, and
also presents methods to reduce noise.
The author of this thesis is responsible for all calculations, simulations and measurements
in this publication.
Paper 7. This paper presents practical techniques to reduce noise in a PLL charge-pump.
The work is related to paper 6, but is elaborating more on the noise reduction techniques
and measurement results. The author performed all theoretical work and all measure-
ments.
Paper 8. This paper present a voltage controlled Colpitts oscillator operating at 1 GHz.
The oscillator is implemented using a SiGe Bipolar process and use integrated spiral in-
ductors. The oscillator use an on-chip automatic amplitude control (AAC) circuit, ensur-
ing the oscillator is biased for a constant output amplitude.
The author of this thesis performed calculations on circuit operation, performed inductor
geometry optimization and investigated the impact of the amplitude control circuit on
oscillator phase noise.
Paper 9. In this paper a new technique to reduce noise in CMOS oscillators is investi-
gated. By decoupling the oscillator core using a bypass capacitor, noise from the bias
current and supply voltage is reduced. In addition, device currents in the oscillator are
shaped using a similar technique as in Colpitts oscillators in order for active devices to
give minimum impact on oscillator phase-noise. The topology differs from a Colpitts os-
cillator since no capacitive divider is used and the circuit uses a different bias technique.
Since the oscillator would not start where the bias is optimal from a noise point of view,
an amplitude control circuit is used to ensure proper operation.
The author of this thesis proposed the circuit topology, and have supervised the calcula-
tions and simulations.
Chapter 1

Introduction

During the last decades there has been an exceptional growth in the use of wireless de-
vices. High speed wireless connections are now standard equipment in computers and
mobile devices, and the number of mobile phone subscriptions worldwide exceed 3.25
billion [1]. In Sweden and many other European countries, the number of mobile phones
even exceed the population [2].
Thanks to new design and manufacturing capabilities the performance of wireless devices
have improved at the same time as size and price have decreased. This development is the
result of an intensive research from both industry and academia.
Due to the frequency requirements, early Radio Frequency (RF) circuits had to be manu-
factured using special and expensive processes. Silicon devices have had acceptable per-
formance for radio design in the 1-10 GHz rage since early 1990s [3]. With advances in
processing technology, mainly driven by the digital design community, it became possible
to also realize RF circuits using Complementary Metal Oxide Semiconductors (CMOS)
technologies. The combination of low cost and the ability to integrate analog functions
together with complex digital circuits makes CMOS an attractive choice of technology.
Continuing advances in process technology are favorable also the analog performance,
and CMOS is believed to be an attractive choice for RF circuits also in the future [4].
Along with the use of silicon technology, the integration level of RF circuits have in-
creased. Up to mid 1990s, radio implementations were realized using multi-chip solutions
having different ICs for the RF, base-band, frequency synthesizer and oscillator circuits
[5]. The transceivers included external filters and numerous discrete components, often
requiring manual tuning and bulky shielding arrangements.
The feasibility of implementing radio front-end circuits [6][7] and later complete trans-
ceivers [8] in CMOS was demonstrated in the late 1990s. Todays CMOS RF transceivers
include complete systems on chip, where also data converters, demodulator and even
micro processor and memory is integrated [9].

1
2

The focus in this thesis is the design and analysis of fully integrated phase-locked loop
(PLL) frequency synthesizers targeting radio applications. In chapter 2 PLL performance
parameters and their impact on a radio transceiver are reviewed.
While the theory and operation of PLL circuits are well known [10][11][12][13], the in-
creased integration level puts new demands on design methodologies and implementa-
tions. Since new wireless standards aim for high performance and data-rates, the PLL
specifications are often stringent, requiring each PLL block to be optimized for best pos-
sible performance. Also, in highly integrated circuits traditional design methods are not
directly applicable since individual building blocks can not be directly measured and char-
acterized. In integrated solutions the designer instead have to rely on simulations. When a
large number of components are integrated in the same circuit, isolation and the coupling
between blocks also have to be predicted.
Due to the wide range of time constants and the strongly non-linear operation, simulation
of PLL building blocks is non trivial. In addition, practical synthesizer implementations
often include control logic and mixed signal circuits to perform calibration, complicating
simulation and verification further.
While direct simulation using a Spice type simulator is possible in special cases [14][15],
simulation times are often long and prone to numerical errors. The designer instead have
to use a combination of hand calculations, linear approximations, numerical methods and
mixed signal simulations. Models having appropriate level of accuracy have to be selected
in different steps of the design.
Chapter 3 discuss various PLL simulation and analysis techniques. Derivation of linear
models of PLL building blocks, as well as non-linear behavioral modeling of PLL perfor-
mance using hardware description languages is presented in detail.
In radio applications the PLL phase noise is of great importance. Methods to calculate
the combined effect of PLL phase-noise performance are well known [16] but also these
methods rely on that the noise properties of each PLL building block is known.
Due to the strongly non-linear operation, phase noise of PLL building blocks are difficult
to analyze, and was not understood until relatively late. While methods to calculate noise
of certain blocks such as the Voltage Contolled Oscillators (VCO) [17], and digital cir-
cuits [18] are now well established, little information regarding other blocks such as the
charge-pumps exist in open literature. Effects such as noise folding in ∆Σ fractional-N
PLL:s due to charge-pump miss-match have been investigated [19][20], the charge-pump
noise is approximated to be directly proportional to the duty cycle of the charge-pump.
This approximation does not take the frequency dependent effects of noise folding into ac-
count. In chapter 4 the effects of noise folding due to the operation of the phase-frequency
detector and charge-pump noise is investigated. Noise properties of other PLL building
blocks and their impact on total PLL noise performance is also discussed.
Chapter 5 discuss the design and implementation of voltage controlled oscillators. Since
recommendations regarding oscillator dimensioning sometimes show contradicting re-
sults, for example is the MOS device size recommended to be maximized in [21] and
1.1. PLL OPERATION PRINCIPLE 3

minimized in [22], the noise properties of oscillators are investigated in detail. A novel
oscillator topology showing improved phase noise performance is also presented.

1.1 PLL operation principle

Fig. 1.1 shows the block diagram of a typical charge-pump PLL circuit. This is the topol-
ogy that will be analyzed throughout this thesis. The PLL consists of a reference oscilla-
tor, Voltage Controlled Oscillator (VCO), programmable divider (1/N), Phase Frequency
Detector (PFD), charge-pump (CP) and a loop-filter.

Figure 1.1: Typical charge-pump PLL block diagram

The reference oscillator runs at a constant frequency, while the frequency of the VCO is
controlled by a voltage. The VCO frequency is divided by a programmable divider having
a division ratio N. The divided VCO frequency is compared to the reference frequency
in the PFD. When the VCO is running too slow, clock edges from the divided VCO
frequency will come after the edges from the reference clock. The difference in phase is
detected by the phase detector, and up pulses are generated, Fig. 1.2a.

Figure 1.2: Waveforms in PLL Phase-Frequency detector

4 1.2. TRANSCEIVER OVERVIEW

When the VCO is running too fast, the reference clock will lag, and down pulses will be
generated accordingly, Fig. 1.2b.
The up and down pulses control current sources in the charge-pump. Up pulses will pump
current into the loop-filter increasing the control voltage and down pulses will reduce the
voltage. The loop-filter voltage is connected to the control voltage of the VCO forming
a feedback system. Phase difference will be detected and the charge-pump will adjust
the control voltage until the phase difference between the reference clock and the divided
VCO clock is zero. At this point the VCO will run at exactly N times the frequency of the
reference clock.
The reason for popularity of PLL circuit is partly due to the special properties of the
reference clock. The reference clock can be implemented using a crystal oscillator having
a very stable frequency and good noise properties. Unfortunately it is not possible to build
crystal oscillators operating at high frequency, and the frequency tuning is very limited.
Voltage controlled oscillators on the other hand can operate at high frequency and can
be designed to have a relatively wide tuning range. However, VCO:s are noisy and the
frequency is sensitive to component and temperature variations.
By locking the VCO using a PLL, a stable stability can be achieved also at high fre-
quency. The output frequency can be changed by programming the division ratio. Also,
by properly selecting the loop-dynamics of the feedback arrangement, short term phase
variations of the VCO can be compensated by the PLL, improving the phase noise of the
output signal.
While other PLL configurations are possible, the charge-pump PLL have become popular
in integrated applications since it has infinite lock range, and the phase difference between
the reference clock and the feedback clock is zero when the PLL is locked.

1.2 Transceiver overview

Throughout this thesis different PLL performance parameters and design considerations
are discussed. Many of these methods were used when designing the two transceivers
BlueTraC, targeting Bluetooth applications, and TripleTraC, targeting IEEE 802.11 WLAN
applications.
In this section a brief introduction of the transceiver architectures is presented. In the
following chapters PLL performance parameters are illustrated using measurement data
from these circuit implementations.

1.2.1 BlueTraC
Fig. 1.3 shows the block diagram of the BlueTraC Bluetooth tranceiver. The transceiver
is targeting the BlueTooth version 1.2 specification [23]. The design project started as a
research project at KTH, and was later commercialized in the company Spirea AB.
1.2. TRANSCEIVER OVERVIEW 5

Figure 1.3: BlueTraC block diagram

The transceiver use direct modulation of the oscillator in transmit mode and a low-IF
receiver. The receiver is implemented using a Hartley image-reject receiver where the
local oscillator is generated using a quadrature oscillator and the base-band phase shift of
the base-band signal is performed using a poly-phase filter. The intermediate frequency is
1 MHz.
The demodulator is implemented in digital domain, using direct IF sampling. A variable
gain amplifier (VGA) keeps the input amplitude at the demodulator input at an acceptable
level. The gain control is using a mixed-signal implementation, where the gain is digitally
controlled using data from the demodulator.
Modulation of the carrier is performed using direct modulation of the oscillator. The os-
cillator have two control nodes, one to set the channel frequency, and one to modulate
the carrier. If the PLL is locked when transmitting data, the PLL would distort the mod-
ulation. To overcome this problem, the PLL is opened, i.e. the charge-pump is turned
off. The loop-filter capacitor will keep the VCO control voltage, and the PLL will operate
at a constant frequency when the PLL is open. Since BlueTooth data is transmitted in
packages, the loop will be closed in regular intervals allowing the PLL to be re-locked.
Leakage current in the oscillator control node would cause the oscillation frequency to
drift. To minimize this drift and allow the use of a small on-chip loop filter, a low-leakage
charge-pump is implemented. The charge-pump use a feedback amplifier to force the
voltage drop of the charge-pump switch transistors to zero when the PLL is open. The
implementation of the charge pump is described in detail in Paper 1
Fig. 1.4 shows a chip photo of the transceiver. The circuit is implemented using a standard
0.18µm CMOS process.
The transceiver architecture differs from a traditional open-loop architecture since the
PLL is open not only in transmit mode but also when receiving data. Doing so gives
several advantages:
6 1.2. TRANSCEIVER OVERVIEW

Figure 1.4: BlueTraC chip photo

1. Reduced noise and spurs. Since the PLL is not active in receive mode, noise and spurs
are determined by the VCO only.
2. Lower current consumption. Current consumption is reduced by turning off PLL
blocks when transmitting and receiving data. The charge-pump noise do not affect
system performance since the PLL is not active during data transmission. It is there-
fore possible to use a reduced charge-pump current.
3. Simplified frequency compensation. The VCO low gain port can be used to fine tunes
the oscillation frequency when receiving data. This is used to compensate frequency
errors and simplifies the demodulator implementation [24].

Since the PLL is open both when transmitting and receiving data, it is possible to use a
wide loop-filter bandwidth.
Fig. 1.5 shows a comparison of the phase-noise of an open loop oscillator and an oscillator
locked in a PLL. When locked in a PLL, phase-noise at frequencies within the loop-filter
bandwidth is relatively flat and determined by the PLL components. Using a wide loop-
filer bandwidth (Fig. 1.5a) will result in increased phase-noise compared to an unlocked
oscillator. For this reason the PLL loop-filter is traditionally selected to have relatively
low cut-off frequency (Fig. 1.5b). However, a narrow bandwidth requires large loop-filter
components, and are often difficult or bulky to implement on-chip [25].
Since the BlueTraC PLL is disabled when transmitting and receiving data, the phase-
noise is determined entirely by the VCO. PLL noise and spurs will not degrade the output
1.2. TRANSCEIVER OVERVIEW 7

Figure 1.5: Typical oscillator output spectrum of a PLL operating in locked and open-loop mode.

spectrum, and the loop-filter can be selected as wide as possible. This allows the use of
small on-chip loop-filter components.
Enabling and disabling of PLL blocks are controlled by a state machine. When transmit-
ting or receiving a data package the BlueTraC PLL operates as follows:

1. Before the package starts the PLL is enabled to set correct channel frequency. The
PA is disabled during PLL lock in order not to transmit at unwanted frequencies. The
modulation voltage of the low gain port is centered to give zero frequency deviation.

2. A short time before the data packet starts, the PA or the receive chain (LNA, Mixer
and Demodulator) is enabled depending if the transceiver should operate in transmit
or receive mode. The enabled blocks change the load on the oscillator, causing the
frequency to shift. To compensate frequency change, the PLL is kept locked bringing
the oscillator back to the correct frequency.

3. Just before the package starts the PLL is opened. To minimize charge-injection, the
PLL is opened by putting the charge-pump in high impedance mode. This is done
by disabling the pump pulses from the phase detector. The disabling is synchronized
with the reference clock so the PLL is never opened when the charge-pump is injecting
current into the loop-filter.
When the PLL is disabled, the loop-filter capacitors hold the VCO control voltage. If
the leakage current is low, the oscillator frequency will remain centered at the correct
channel.

4. When the transceiver is in transmit mode, transmit data is fed into the low gain port of
the oscillator. The Gaussian shaped modulation voltage is generated using a digital to
analog converter and a digital lookup table.
8 1.2. TRANSCEIVER OVERVIEW

The design goals when specifying the transceiver was to achieve a highly integrated solu-
tion using low current consumption and small chip area.
In order to save power the divider and phase detector are disabled when the PLL is open.
The input stage of the divider remains active however, since this block is connected di-
rectly to the VCO and would cause frequency shift if powered down.
Since the transmitter is using direct modulation, the VCO is operating at exactly the same
frequency as the power amplifier. For this reason there will be no frequency pulling due
to coupling from the PA to the VCO. This relaxes the reverse isolation requirement of the
buffer between the VCO and the PA.
However, in the first prototype some parts of the architecture was chosen too aggressively,
and the test circuit was experiencing some problems.
The local oscillator was implemented using a quadrature oscillator, using the quadrature
calibration scheme described in [26]. While ensuring good quadrature matching, the ana-
log feedback in the calibration scheme was degrading the oscillator phase-noise. The
degraded phase noise could be corrected by using a mixed signal feedback using a pro-
grammable capacitor bank instead of the analog feedback using a varactor. A second
problem with the oscillator was inaccurate varactor models, causing the modulation index
to bee too high.
The receiver was also suffering from insufficient LO buffering. The buffering was de-
liberately designed weak in order to save current. This made interfering signals from
the receiver leak into the oscillator, causing frequency pulling. The oscillator could also
experience injection locking when receiving very strong signals.
BlueTraC was never put into production, but the lessons learned from the implementation
gave important input to future projects.

1.2.2 TripleTraC
Fig. 1.6 shows the block diagram of the TripleTraC Wireless LAN transceiver circuit. The
transceiver target multi band multi standard operation complying with the IEEE 802.11
a,b and g standards.
WLAN 802.11b and g both use a frequency band between 2400 and 2485 MHz, while
the 802.11 a use several bands in the range 5150 to 5825 MHz. To accommodate both
frequency bands the transceiver use a wide-band IF receiver and two step up conversion.
Fig. 1.7 shows the frequency plan of the transceiver. In receive mode the RF band at 5
GHz and 2.4 GHz is down converted to an IF at 1.3 to 1.5 GHz. The architecture use
separate low-noise amplifiers for each frequency band. The down conversion mixers are
shared between the 2.4 and 5 GHz bands in order to reduce chip area. Since the receive
bands are widely separated, the image rejection provided by the RF band select filter and
the narrow-band operation of the LNA:s is sufficient, and no further image rejection is
needed.
1.2. TRANSCEIVER OVERVIEW 9

Figure 1.6: TripleTraC block diagram

Figure 1.7: TripleTraC frequency plan.

The IF signal is down-converted to base-band using a quadrature mixer. The analog base-
band consists of a 4th order Butterworth active RC filter and a variable gain amplifier
having a control range of 70 dB. The cutoff frequency of the filter is automatically cali-
brated using an on-chip calibration circuit.
The transmit path use a two step up converter, using the same intermediate frequency
as the receiver. Two on-chip pre amplifiers are used, one for each frequency band. The
amplifier output powers are programmable between -32 dBm to 0 dBm in 2 dBm steps.
The transceiver use two integer-N PLL circuits to generate the local oscillator signals. The
first PLL (LO1) is programmable in coarse frequency steps between 3840 to 4320 MHz
10 1.2. TRANSCEIVER OVERVIEW

using a reference frequency of 20 MHz. The second PLL is programmable in 1 MHz steps
between 1310 and 1510 MHz. The quadrature output signal needed at the IF mixers are
generated using a poly-phase filter.
The use of two PLL circuits relax the tuning range since the frequency tuning are shared
between the PLL:s. The quadrature generation is also somewhat relaxed, since LO2 is
operating at relatively low frequency. The solution do however put higher demands on
the PLL phase noise and spur requirements, since the total phase noise will be the sum of
noise originating from both PLL:s

Figure 1.8: VCO center frequency calibration circuit.

In order to achieve a robust implementation, both LO1 and LO2 perform automatic fre-
quency calibration at power up using an on-chip calibration circuit as illustrated in Fig.
1.8. The circuit utilize the PLL control voltage and a window comparator to detect if the
oscillator is running at a too high or too low frequency. By using a digital up and down
counter, a digital tuning word is adjusted until the tuning voltage is within the allowed
range. A delay circuit in the calibration logic ensures the control word is not updated until
the PLL is settled.
Fig. 1.9 shows a die micro photograph of the TripleTraC transceiver.
The transceiver is implemented using a 0.18µm CMOS process and occupies a total die
area of 12mm2 . The circuit is using a 48-pin QFN package with exposed ground paddle
in order to achieve low inductance ground.
1.2. TRANSCEIVER OVERVIEW 11

Figure 1.9: TripleTraC chip photo

12 1.2. TRANSCEIVER OVERVIEW
Chapter 2

PLL performance parameters

A functional frequency synthesizer must fulfill a basic set of requirements such as being
able to generate all required frequencies, doing so with sufficient accuracy and delivering
the correct output power. In addition, the frequency synthesizer must have sufficiently
high spectral purity.

Figure 2.1 shows the measured output spectrum of a typical PLL in locked condition.

Figure 2.1: Output spectrum of a typical PLL in locked condition

13
14 2.1. FREQUENCY RANGE AND ACCURACY

The output signal from an ideal frequency synthesizer would be a pure sinusoidal, having
no noise or frequency error, i.e. all power would be located at one frequency. The real
PLL implementation however suffer from non-idealities such as phase noise and unwanted
frequency components.
Phase noise is random phase variations of the oscillator output and shows as power "skirts"
around the carrier, (a in Fig. 2.1). Phase noise is generated by all components in the
frequency synthesizers, and shaped by the loop-dynamics of the PLL.
Spurious frequency components can be seen as discrete frequency components in the
output spectrum, often symmetrically located around the carrier (b in Fig. 2.1). Spurious
tones can be interference of other blocks in a transceiver, or originate from repetitive
operation in PLL building blocks.
The frequency synthesizer is usually part of a radio system targeting a specific standard,
for example GSM or BlueTooth. In these standards, radio performance parameters are
accurately specified to ensure interoperability between different manufacturers. Since the
radio transceiver can be implemented using many different architectures, the standard do
not directly specify PLL performance parameters. Instead the standard typically include
specifications such required modulation accuracy and maximum allowed emission in ad-
jacent bands. These parameters have to be mapped to the transceiver architecture, giving
the requirements on phase-noise and spurious performance.
While the functional requirements of the PLL are usually straight forward to specify and
simulate, the spectral purity requires a much more thorough treatment.
This chapter discuss PLL performance parameters and how the frequency synthesizer
affects a telecommunication system. While the main focus of this work is PLL frequency
synthesizers, most results are also valid for other frequency generation methods. Methods
to calculate PLL phase noise is discussed in chapter 4.

2.1 Frequency range and accuracy

The frequency range is usually limited by the tuning range of the VCO. Achieving high
performance over a wide tuning range is challenging [27] and oscillators are usually de-
signed not to have more tuning range than required. The oscillator tuning range is always
designed to have some margin in order to allow correct operation even in the presence of
model errors and process variations.
In high speed circuits it may be difficult to implement functional dividers, and the fre-
quency range may be limited also by the digital divider. The number of bits in the divider
control logic also put a practical limit to the frequency range. In divider implementations
using a prescaler, the counter implementation will limit both the maximum and minimum
achievable division ratio [28]. There are no fundamental limits to the possible number of
bits in the divider, but as circuit complexity and current consumption increase with the
2.2. SETTLING TIME 15

number of bits, it is desirable not to use a divider having more bits than necessary for
correct PLL operation.
Finally, the frequency range may also be limited by the output voltage swing from the
charge-pump, especially in low voltage applications. When the charge-pump output volt-
age approach supply or ground, parameters like current miss-match increase. The PLL
may still be able to lock to the correct frequency, but degraded performance makes the
PLL violate noise and spurious requirements.

2.1.1 Frequency Spacing

Since integer-N PLL frequency synthesizers are only able to lock to multiples of the refer-
ence frequency, the frequency spacing is equal to the reference frequency. If the frequency
spacing is required to be low this will limit the maximum allowed loop filter bandwidth,
possibly resulting in increased lock time and phase noise.
In a fractional-N PLL the frequency spacing is determined by the number of bits in the
noise shaper, and the reference frequency can be high still achieving a small frequency
step. This gives more design freedom to optimize loop-filter bandwidth for good noise and
spur performance. The use of a fractional-N PLL also allows the use of different reference
frequencies. This is an advantage is applications targeting multi standard operation.
The frequency spacing will have a different value than the channel spacing if the channel
frequency if not a multiple of the channel spacing.

2.1.2 Frequency accuracy

In an integer-N PLL the frequency accuracy is determined by the accuracy of the reference
oscillator. To achieve the required accuracy, it is often necessary to calibrate the reference
oscillator.
An alternative way to achieve required frequency accuracy without calibrating the crystal
oscillator is to use a fractional-N synthesizer with very precise frequency steps. The fine
steps can also be used to compensate for temperature drift in the reference oscillator.

2.2 Settling time

The settling time specifies how fast the PLL arrives at the new frequency when changing
frequency. Since the PLL is a feedback system having limited band-width, the PLL fre-
quency will not change instantaneously. The PLL settling time depend on the frequency
step and the PLL loop dynamics.
Since the PLL will only approach the final frequency asymptotically, it is not possible
to define condition when the PLL is "locked" to the correct frequency. Instead the PLL
16 2.2. SETTLING TIME

settling time must be defined as the time when the frequency error is less than a specified
value.
Even after the frequency error is smaller than the specified limit, the frequency will con-
tinue to change. This may impact the demodulator, and a robust demodulator implemen-
tation should therefore always be able to handle a certain amount of frequency drift.
The lock time is improved by using a wide loop-filter bandwidth. Since reference spurs
and phase noise may degrade if using a too wide loop-filter, there is a trade-off between
fast lock time and good spur and noise performance. In fast lock applications it may be an
advantage to use a fractional-N PLL, since a wider PLL bandwidth may be used compared
to integer-N applications.

2.2.1 Fast lock schemes

Since lock time often is a bottleneck in PLL implementations, numerous methods exist to
improve the settling time.
One method is to dynamically adapt the PLL bandwidth. A wide bandwidth is used during
PLL lock, giving fast settling time. Once the PLL has locked to the correct frequency, a
narrow bandwidth is used to give good phase noise and spur performance.
Variable bandwidth can be achieved in a numerous ways: [29] use of a variable loop-filter.
[30] proposed changing the loop-gain by programming the charge-pump current. In [31]
and [32] fast lock is achieved by using a PFD/CP combination having small output current
for small phase errors, and large output current for big errors.
Fast switching can also be achieved by doing a careful loop-filter design using discrete
time [33].
In applications where settling time requirement is very stringent, fast frequency shift may
be achieved by using multiple PLL:s [34].

2.2.2 Frequency stability

Interfering blocks, load variations and changes in bias or supply voltage will affect the
oscillator center frequency even when the PLL is locked.
This is illustrated in Fig. 2.2 where the PLL frequency is measured when the power
amplifier is enabled.
In Fig. 2.2 the Power Amplifier (PA) is implemented on the same die as the PLL, creating
interference between the blocks. When the PA is enabled, the change in current consump-
tion will affect the power supply voltage, causing the oscillator frequency to shift.
The impact of the frequency change will also affect the modulation. Fig. 2.3 shows the
demodulated signal of a 802.11b data package. The initial frequency error is visible as
2.3. SPURIOUS TONES 17

Figure 2.2: Measured frequency vs time when TX-chain is enabled. The power amplifier cause
the PLL frequency to change more than 20 kHz affecting the preamble of the transmitted package.

an irregularity in the beginning at the package. The frequency instability generate phase
variations in the modulated signal, causing rotation of the constellation points.
To handle frequency stability problems, careful attention must be payed to oscillator sup-
ply and grounding. The PLL control voltage must be separated from interfering signals
and the loop filter properly grounded. Loading stages must be sufficiently isolated us-
ing oscillator buffers. Interfering blocks should be separated as much as possible in the
layout.
Fig. 2.4 shows the difference in oscillator stability when using common or separate supply
regulators for the power amplifier and the frequency synthesizer. In Fig. 2.4 the PA is
enable at t = 20µs. When using common supply for the PA and VCO, the PLL need 30µs
to settle to the correct frequency. Using separated supplies, this time is reduced to around
10µs.

2.3 Spurious tones

Spurious tones are generated within the PLL itself, or by interfering clocks in the transceiver.
Fig. 2.5 shows the measured output spectra from the 2.4 GHz output of the transceiver
in Paper 4 and 5. The transceiver have two local oscillators, LO1 operating at 3.84 GHz,
18 2.3. SPURIOUS TONES

Figure 2.3: Demodulated 802.11b package

and LO2 operating at 1.4 GHz. In addition to the wanted output signal at 2.4 GHz, a wide
range of spurious tones are visible. The leakage from the local oscillators, the harmonics
and the different inter-modulation products are indicated in the figure.

2.3.1 Reference spurs

A small fraction of the reference clock will always leak through the loop-filter and mod-
ulate the VCO, creating sidebands around the oscillator output at a distance equal to the
reference frequency. When the PLL frequency change, the reference spurs will move
along with the carrier.

The power of the reference spurs are related to charge-pump miss-match, charge-pump
leakage or charge-injection [13], and are filtered by the loop-filter.

Reference spurs can be minimized by doing a careful charge-pump design, and by using
a low cutoff frequency in the loop-filter.
2.3. SPURIOUS TONES 19

Figure 2.4: Measured oscillator stability using common and separated supply lines

Figure 2.5: Measured spurious tones at TripleTraC PA output when operating in 2.4 GHz band.
20 2.3. SPURIOUS TONES

2.3.2 Fractional reference spurs

In a fractional-N PLL implementations, spurs may appear at fractions of the reference
frequency. When using a Σ∆ noise shaper, repetitive patterns in the noise shaper, so called
idle tones, may also generate spurious tones. The fractional spurs can be reduced by
applying so called dithering, i.e. adding pseudo random noise to the least significant bit
in the frequency control word.
Even when dithering is properly applied, fractional spurs may still be present in the output
spectrum due to folding of high frequency noise in non-linear PLL components such as
the charge-pump [20].
In certain prescaler implementations, spurs may also appear at fractions of the reference
clock in also integer-N PLL:s [25]. This is due to cyclic operation of components in the
PLL and can be resolved by using re-timing of the prescaler output.

2.3.3 Reference harmonics

Many PLL blocks, such as the phase detector and the divider, are digital circuits operating
at the frequency of the reference clock. Since digital signals have steep rise and fall times,
signals will contain high frequency components at harmonics of the reference clock. The
harmonics may couple to the PLL output, creating spurious tones at multiples of the ref-
erence frequency. The coupling could be through the supply, bias, magnetic or inductive
coupling of nearby wires, or coupling though the substrate.
In an integer-N PLL, the reference harmonics will be located at the same frequency as the
carrier and the reference spurs. In measurements reference spurs and reference harmonics
can be distinguished by changing the PLL frequency. The reference spurs will follow the
PLL frequency, while the amplitude of reference harmonics remains relatively constant as
the PLL frequency change.
In fractional-N PLL implementations, strong reference harmonics may also appear when
the distance between the PLL output and an harmonic of the reference clock is less than
the PLL bandwidth [19]. A possible reason for this is down-conversion of the VCO in the
charge-pump, as discussed in chapter 4.3.

2.3.4 Overtones
The PLL output will contain energy at harmonics of the fundamental frequency if the
output from the VCO is not a pure sinusoidal. If propagating to the output these harmonics
may violate the out of band emission requirements. Overtones are usually possible to filter
out.
Many applications of the PLL signal, for example when driving a mixer, require fast
switching where the best waveform is a square wave rather than a pure sinusoidal. In this
case overtones are unavoidable, and may even be desired for good mixer performance.
2.4. PHASE NOISE 21

In other cases the overtone content needs to be minimized. When generating a quadrature
signal using a polyp-phase filter, the harmonic content must be low in order to achieve
good phase matching [35].

2.3.5 Inter-modulation spurs

When several clocks are present on the same circuit, non-linear components may cre-
ate inter-modulation products at a frequency equal to the sum or difference between the
interfering frequencies.
Inter-modulation spurs can be traced by changing the PLL frequency, and noticing how
the spur frequency change.

2.4 Phase noise

Electrical components in PLL building blocks generate noise. This noise affects the PLL,
creating phase variations of the PLL output signal, so called phase noise. Phase noise
affects both the transmitted and received signal, and will distort the modulation of trans-
mitted data.
The trend in modern communication circuits is towards higher data rates and better band-
width utilization. This requires more advanced modulation schemes, increasing the re-
quirements on the local oscillator phase noise. Correspondingly there is an increased
demand for methods to calculate and reduce frequency synthesizer phase noise [36][19].
Designing PLL:s having sufficiently low phase noise is especially challenging in highly
integrated solutions, where the lack of high quality components and interference between
transceiver building blocks will degrade synthesizer performance [37].
Figure 2.6 shows a typical phase-noise distribution of a locked PLL, and the blocks con-
tributing to noise at different offsets.
This chapter discuss phase noise from a radio system perspective. Calculation of PLL
noise and the contributions from PLL building blocks is handled in section 4.

2.4.1 Phase noise spectra

The phase noise spectra can be calculated in a number of different ways, and the spectral
distribution will depend on how the noise spectra is defined [12]. This section summarize
the most common definitions used in radio applications.
The output signal vo (t) from a generic oscillator having a sinusoidal output signal and a
nominal angular frequency ω0 is:
22 2.4. PHASE NOISE

Figure 2.6: Typical phase-noise distribution

vo (t) = (A + a(t)) cos(ω0t + φ(t)) (2.1)

where A is the mean amplitude and a(t) is the zero-mean amplitude noise. φ(t) is the
phase disturbance in radians. The phase disturbance is the deviations from the ideal
output phase, including effects of the random zero-mean phase noise, initial phase error
and integrated effects of frequency offset and drift.
Oscillators always have an amplitude control mechanism or are followed by a limiting
buffer. For this reason variations of the phase is dominant and the amplitude variations
can normally be neglected.
Normalized spectrum
Neglecting the frequency drift of the oscillator, the Fourier transform of the autocorre-
lation function of vo can be calculated giving the Theoretical Spectrum Wvo ( f ), i.e. the
spectrum of vo . The unit of Wvo is V 2 /Hz.
In radio applications the phase noise is normally expressed as the normalized spectrum
L (∆ f ) at a frequency offset ∆ f from the carrier.

Wvo ( f0 + ∆ f )
L (∆ f ) = (2.2)
A2 /2
2.4. PHASE NOISE 23

i.e. the noise power relative the total power in the signal. f0 is the carrier frequency in Hz.
The normalized phase noise spectrum is expressed in dBc/Hz.
The normalized spectrum is often plotted in log-log scale. Fig. 2.7 shows a typical plot of
the normalized phase noise spectrum.

-100
E5500_PN

-105

-110

-115
Phase Noise [dBc/Hz]

-120

-125

-130

-135

-140

-145
1000 10000 100000 1e+06 1e+07
Freq offset [Hz]

Figure 2.7: Measured phase noise

Phase noise spectrum

The normalized spectrum L refers to the voltage output signal vo . In phase noise calcula-
tions and and simulations it is often more convenient to use the phase disturbance φ and
the corresponding phase noise spectrum Wφ ( f ).
Unlike the normalized spectrum, Wφ goes to infinity for small frequency offsets. This can
intuitively be understood as the phase difference between an ideal reference oscillator and
a real synthesizer implementation will go to infinity if the two oscillators are left running
long enough.

2.4.2 Relating phase noise to normalized spectrum

Unfortunately there is no simple relation between the phase noise spectrum Wφ and the
normalized spectrum L .
However, for moderate frequency offsets the normalized spectrum can be approximated
if the phase variations are considered to create a narrow-band frequency modulation of
the carrier. If the carrier is frequency modulated at a frequency ωm having a peak phase
deviation θ p , the output voltage vo can be calculated:
24 2.4. PHASE NOISE

vo (t) = V cos(2π f0t + θ p cos(ωmt)) (2.3)

Expanding (2.3) gives:

vo (t) = V (cos(ω0 ) cos(θ p sin(ωmt)) − sin(ω0t) sin(θ p sin(ωmt))) (2.4)

If the maximum phase deviation is small, i.e. θ p << 1, the output signal can be approxi-
mated:

vo (t) ≈ V (cos(ω0t) − θ p sin(ω0t) sin(ωmt)) (2.5)

and after expanding the equation

θp
 
vo (t) ≈ V cos(ω0t) − (cos((ω0 + ωm )t) − cos((ω0 − ωm )t) (2.6)
2
i.e the output signal have two side-bands at a frequency offset ωm having a power equal
to V θ p /2.
Using equation (2.6) the relative amplitude of the sideband can be calculated:

Vsideband V θ p /2 θ p
= = (2.7)
Vsignal V 2
The power is proportional to the squared voltage:

θ2p θ2
 2
Vnoise
= = rms (2.8)
Vsignal 4 2
Using the phase noise spectra Wφ ( f ), the normalized spectrum L ( f ) can then be approx-
imated:

Wφ ( f )
L( f ) ≈ (2.9)
2
The approximation in (2.9) will be accurate as long as the frequency deviation is small,
but will fail at large frequency offsets. Also, at large frequency offsets the phase part of
the noise in oscillator buffers will dominate, and (2.9) will give wrong result.
Since the phase deviations are relatively small at the frequencies of interest in most PLL
implementations, equation (2.9) is usually a good approximation of the normalized spec-
trum
Many circuit simulations simulates the phase noise spectra Wφ but displays Wφ /2. Be-
fore interpreting simulation results it is advisable to read the simulator reference manual
carefully, especially for phase noise at small frequency offsets.
2.5. PHASE NOISE IMPACT ON SYSTEM PERFORMANCE 25

2.4.3 Measuring phase noise

Phase noise measurement equipment or signal source analyzers are capable of directly
measure phase noise [38].
The normalized phase noise spectrum can be also measured approximately using a spec-
trum analyzer. Since the spectrum analyzer presents the integrated power over the reso-
lution bandwidth, the normalized spectrum have be calculated by dividing the measured
power with the resolution bandwidth and subtracting the carrier power.
The results from measuring phase noise using a spectrum analyzer have to be interpreted
with care, since the internal phase noise of the instrument is added to the measurement
result. Thermal noise of analyzer input stage will set the noise floor, and will limit the
minimum detectable phase-noise. When measuring phase noise the spectrum analyzer
input attenuation should be reduced as much as possible to allow measurement of low
noise power. Also, since a spectrum analyzer can only measure one frequency at a time,
measuring the phase noise using a spectrum analyzer requires the oscillator to be fairly
stable.
Since fully integrated PLL frequency synthesizers are rather noisy but the center fre-
quency is kept stable by the PLL, PLL phase noise can be directly measured using a
spectrum analyzer in most applications. Measuring phase noise of free running oscillator
is usually difficult however, since the center frequency of the oscillator often drift faster
than the sweep time of the spectrum analyzer.

2.5 Phase noise impact on system performance

Phase noise affects a system differently depending on the frequency offset from the car-
rier. Systems are usually designed to tolerate frequency errors and drift in oscillation
frequency, and are therefore not very sensitive to phase noise at small frequency offsets.
Phase noise at medium frequency offsets affect signal modulation, and is becoming in-
creasingly important in systems using advanced modulation schemes.
At large offset the phase-noise requirements are usually stringent.

2.5.1 Large frequency offsets

Phase noise at large frequency offsets (A in Fig. 2.6) affect both the transmit and receive
path of a radio transceiver. Large frequency offset in this context mean frequencies equal
or greater than the channel bandwidth.
Receive path
In the receiver, phase noise makes the mixer down-convert signals outside the speci-
fied frequency band, so called reciprocal mixing [39]. When receiving a weak signal
26 2.5. PHASE NOISE IMPACT ON SYSTEM PERFORMANCE

in the presence of a strong interferer the reciprocal mixing makes both signals be down-
converted to the same intermediate frequency. Since the interfering signal may be much
stronger than the wanted signal, the phase noise must be sufficiently low in order not to
degrade the signal to noise ratio.
The signal to noise ratio in the presence of phase noise and an interferer can be calculated:
Z
SNR = Pwanted − Punwanted − L (∆ f )d∆ f (2.10)
B

where Pwanted and Punwanted are the power of the wanted and unwanted signals respec-
tively, and B is offset frequency range of the adjacent channel. The required SNR can be
approximated by assuming the phase noise is flat in the unwanted frequency band:

L (∆ f ) ≤ Pwanted − Punwanted − SNRrequired − 10 log(Bchannel ) (2.11)

Most radio standard documents specify how strong interfering signals must be tolerated.
Equation (2.11) can be used to give a first approximation of the required phase noise in
order to tolerate the blocking signals.
Transmit path
In the transmit path phase noise will make the transmitter emit signals outside the allowed
frequency band. In most standards the allowed Adjacent Channel Power Ratio (ACPR) is
specified. ACPR covers all signal emission in adjacent bands, including phase noise and
spurious tones.
The ACPR due to phase noise can be calculated by integrating the noise power over the
adjacent band B:
Z
ACPR = L (∆ f )d∆ f (2.12)
B

When specifying phase noise, a few dB of margin is often added to account for simulation
errors and variations.

2.5.2 Medium frequency offsets

At medium frequency offsets (B,C in Fig. 2.6) phase noise will distort the signal modu-
lation. In for example an audio fm application, phase noise at medium offsets would be
recognized as an audible noise.
The system impact of this noise depends on the modulation scheme and demodulator im-
plementation. Many digital communication systems, for example GSM or DCS-1800, use
phase modulation, and in these standards the maximum allowed phase errors are specified.
Usually both the root mean square (RMS) and the peak phase error is specified [40].
2.6. PHASE NOISE IN OFDM SYSTEM 27

In standards using more complex modulation schemes such as Quadrature Amplitude

Modulation (QAM), Error Vector Magnitude (EVM) is used to specify the allowed mod-
ulation error. Since the EVM is the total modulation error including effects of not only
phase noise but also amplitude noise, distortion and quadrature missmatch, EVM can not
be used to directly specify the phase noise. Instead, the specification tradeoff between
phase noise and other non-linearities.
The impact of phase noise in OFDM systems is covered in more detail in section 2.6

2.5.3 Small frequency offsets

Phase noise at small frequency offsets (D in Fig. 2.6) often have little or no impact on
system performance.
Since there is always a residual phase error in the reference oscillator, no frequency syn-
thesizer run at exactly the correct frequency and there will always be a difference between
the local oscillators in the transmitter and the receiver. Even if it was theoretically possible
to create two perfectly synchronized oscillators, Doppler shift and reflections in moving
objects would still introduce frequency errors.
All radio receivers must therefore have a mechanisms to handle frequency errors of the
received signal. Low frequency phase noise are not distinguishable from frequency errors,
so this mechanism will also handle phase noise at small frequency offsets.

2.6 Phase noise in OFDM system

In Orthogonal Frequency-Division Multiplexing (OFDM), a high speed data stream is
split into several low speed streams, and closely spaced sub carriers are used to carry
data [41]. Each sub-carrier is modulated using a conventional modulation scheme such
as Binary Phase Shift Keying (BPSK) or Quadrature Amplitude Modulation (QAM). The
frequency spacing of the sub-carriers is selected to be spectrally orthogonal, i.e. at the
center frequency of a sub carrier all other sub-carriers have a spectral null. Ideally each
sub-carrier can then be demodulated without interference from other sub-carriers.
Fig. 2.8 shows an example of the frequency distribution of the sub-carriers of an OFDM
signal. Real OFDM implementations can use many sub-cariers, for example do Digital
Video Broadcasting systems use as much as 8192 sub-carriers [42]. In addition to the data
carriers, several carriers are reserved for guard intervals and pilot signals. Guard intervals
are inserted at the center frequency and band edges in order to relax the requirements
on filters and LO-leakage. Several sub-carriers are also used for pilot tones to allow
compensation for phase and amplitude variations. The pilot tones are important for how
the phase noise affects the OFDM system.
The sub-carriers are typically generated by using digital signal processing techniques such
as Inverse Fast Fourier Transform (IFFT) algorithms. While computationally intensive,
28 2.6. PHASE NOISE IN OFDM SYSTEM

Figure 2.8: OFDM sub-carriers

recent advances in digital signal processing have made OFDM an attractive option also
for consumer and hand-held applications.
OFDM is becoming increasingly popular over single-carrier schemes due to its ability to
withstand multi-path fading and narrow-band interferers. OFDM is currently used in both
wire-bound systems such as xDSL [43] and numerous wireless communication systems
such as WLAN 802.11a and g [44] [45], WiMax [46] and Digital Video Broadcasting
(DVB) [47]. OFDM was recently selected also for the next generation mobile communi-
cation system, Long Term Evolution [48]

2.6.1 Preamble and frequency compensation

The major drawback with OFDM is its relatively sensitivity to phase noise [49]. To under-
stand how phase variations affect an OFDM system it is necessary to study a data package
and the demodulator implementation.

Figure 2.9: 802.11a/g OFDM training structure

2.6. PHASE NOISE IN OFDM SYSTEM 29

In most OFDM implementations data is transmitted in packages containing a preamble

and a payload. Fig. 2.9 shows the preamble of a typical OFDM package, in this case
802.11a/g WLAN [44]. The preamble contain a training sequence to allow signal detec-
tion, gain adjustment and transmitter and receiver to synchronization. The preamble is
detected in the demodulator and frequency and gain errors are compensated.

Figure 2.10: Blocks affecting the phase-noise in an OFDM receiver

Fig. 2.10 shows the block diagram of a principle direct conversion receiver used in an
OFDM system. The PLL and mixer down-converts the received signal and feeds it into
an Analog to Digital Converter (ADC). The rest of the signal processing is performed in
digital domain.
Since the frequency of the PLL always have a small error, the signal will not be down-
converted exactly to DC in the first down conversion stage (a in Fig. 2.10). After converted
to digital domain, the frequency error is detected during the preamble using a frequency
estimation circuit. A compensation signal is generated, and a second mixing, performed
in digital domain, removes the residual frequency error (Fig. 2.10b). If data is transmitted
in packages, the frequency will be re-estimated in regular intervals. The frequency com-
pensation circuit will therefore also compensate for phase variations originating from low
frequency phase noise. This makes the receiver relatively insensitive to phase noise close
to the carrier.

2.6.2 Common phase error

The frequency compensated signal is split into spectral components using a FFT circuit,
where the constellation points are formed by the real and imaginary part of the respective
sub-carrier Fig. 2.10c.
Phase variations at frequencies within the sub-carrier bandwidth (Fig. 2.6 D up to C,
depending on implementation) will create phase variation on the demodulated signal, ro-
tating the symbol constellation. Since all carriers are up and down converted using the
same local oscillators, the phase error will be common to all sub-carriers. Using infor-
mation from the pilot carriers the phase error can therefore be detected and compensated
[50]. This method is called common phase-error correction.
30 2.6. PHASE NOISE IN OFDM SYSTEM

The pilot carriers contain a known data sequence modulated using a simple scheme, for
example Binary Phase Shift Keying (BPSK). Since the position of the constellation of
the pilot data is known, the phase error can be detected and other constellations in the
received data de-rotated accordingly. Fig. 2.11 shows the constellation diagram of a
WLAN 802.11g package with and without tracking of pilot tones. The pilot constellation
points are visible as two dots at the x-axis. Tracking of pilot tones have shown to be able to
compensate for phase noise for frequencies from zero up to approximately the sub-carrier
spacing [50].

Figure 2.11: Signal constellation with and without pilot tone tracking

2.6.3 Inter Carrier Interference

Noise at larger frequency offsets (B in Fig. 2.6) can not be compensated for by tracking
the pilot tones, and will create Inter Carrier Interference (ICI) [50].

The demodulator for the wanted carrier has a power frequency response which has a
sinc2 ( f ) characteristic. It therefore rejects all sideband carriers, but cannot reject the
adjacent carriers phase-noise sidebands. In the receiver system, this will have similar
impact as additive Gaussian noise and deteriorate the signal to noise ratio.

Fig. 2.12 shows how phase noise from adjacent carriers are added within a sub-carrier.
The number of adjacent carriers and accordingly the ICI depend on the sub-carrier num-
ber. For example will carriers at the far ends of the channel have less adjacent carriers and
therefore experience less ICI compared to carriers in the middle of the band. For exact
calculation of ISI this, and also the sinc shape of the channel have to be taken into account
[51].
2.6. PHASE NOISE IN OFDM SYSTEM 31

Figure 2.12: Neighbor sub-channels phase noise degrades channel SNR

2.6.4 Integrated Noise

If the number of sub-carriers are large, the signal degradation due to phase noise can be
approximated using the Total Integrated Noise, Lint [52].
Lint is calculated by integrating the total phase-noise of the local oscillator, omitting low
frequency noise where the frequency and pilot tracking circuits will compensate phase
variations:
Z − f1 Z f2 Z f2
Lint = L ( f )d f + L ( f )d f = 2 L ( f )d f (2.13)
− f2 f1 f1

where f1 is the highest operation frequency of the demodulator pilot tone tracking circuit.
f1 depends on the demodulator implementation and the number of sub-carriers, but is in
practical implementations somewhere between 1/10th up to the sub-carrier spacing. f2 is
usually selected half the OFDM channel bandwidth. The absolute value of f2 is usually
not critical since the phase-noise drops steeply at high frequency offsets.
Note that a frequency band − f1 to f1 around the carrier have to be omitted since the total
integrated noise Ltot per definition equals one:
Z ∞
Ltot = L ( f )d f ≡ 1 (2.14)
−∞

Lint is commonly used to specify phase noise of local oscillators used in OFDM systems.
The integrated noise gives an indication of the maximum signal to noise ratio of the signal.
For more accurate prediction of the influence of PLL phase noise, the receiver perfor-
mance have to be simulated using a realistic model of the demodulator implementation to
correctly take into account effects of pilot tone tracking [53].
32 2.7. AMPLITUDE AND PHASE MATCHING

2.7 Amplitude and phase matching

In many architectures the local oscillator needs to deliver a quadrature signal, i.e. a signal
having two outputs 90◦ out of phase.
The amplitude and phase accuracy of the quadrature signal impact the image rejection
[54], [55]. The Image Reject Ratio is a function of the gain and phase miss-match and can
be calculated:

1 + (1 + ε)2 − 2(1 + ε) cos(α)

IRR = (2.15)
1 + (1 + ε)2 + 2(1 + ε) cos(α)

where ε and α is the gain and phase miss-match respectively. Figure 2.13 plots the maxi-
mum allowed gain and phase errors for constant image rejection.

1.2
45 dB
50 dB
60 dB
65 dB
1

0.8
Gain error (%)

0.6

0.4

0.2

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Phase error (degrees)

Figure 2.13: Image rejection

Careful design of quadrature generation circuit is required to achieve good matching.

A quadrature signal can be generated using a simple passive phase shifting RC network.
Since the simple RC network only have equal output amplitudes at one frequency, practi-
cal quadrature generation are often performed using multi-stage poly-phase filters. When
using poly-phase filters it is required to use input signal having low harmonic content,
since the phase accuracy of the filter output signal is sensitive to the harmonic content of
input signal, as shown in [35].
An alternative way to generate a quadrature signal is to use a digital divider.
2.8. OTHER PLL DESIGN CONSIDERATIONS 33

If the image rejection is required to be high it is possible to do on-chip calibration, as

was performed for the LO signals in paper 4. Methods to reduce the impact of phase
miss-match using digital compensation techniques have also been proposed [56].

2.8 Other PLL design considerations

In a real product it is necessary to specify a number of addition performance parameters in

addition to the parameters regulated by wireless standard. These parameters include the
operation environment, current consumption etc, and while they do not directly affect the
function of the transceiver, they are often the differencing factor determining if a product
becomes competitive or not.

2.8.1 Operation temperature and allowed temperature drift

Depending on the package and the power consumption, on chip temperature may be sev-
eral degrees higher than the ambient temperature [57].
Not only need the circuit to operate in the specified temperature range, but the temperature
must also be allowed to change. This may be a problem in applications using automatic
calibration. Calibration is usually performed when the circuit power up. When the circuit
is operating, the temperature may increase, causing circuit performance to change. This
may degrade phase noise performance or even cause the PLL to loose lock.

2.8.2 Supply domains and isolation

The signal integrity and isolation between blocks do to a large extent depend on the par-
tition of supply domains, and the layout of interconnect [58]. In order to achieve efficient
isolation, the chip partitioning must be done carefully.
Since RF circuits are often pad-limited, the number of supply and ground pins used must
be selected to give enough isolation while still having a reasonable count.

2.8.3 Testing and calibration

Simulations and measured results never agree perfectly. This may be due to inaccurate
models or process variations.
In order to achieve high yield it is desirable to allow large process variation while still
maintaining good circuit performance. This may be possible by calibrating the chip.
Trimming can be performed using measurement and trimmable fuses.
34 2.8. OTHER PLL DESIGN CONSIDERATIONS

Many parameters, like the VCO oscillation frequency, IQ phase and amplitude matching
and filter cutoff frequencies may also be calibrated automatically using on-chip calibration
circuits.

2.8.4 Output power

To give correct operation of blocks using the PLL signal, the output amplitude must be
within specified limit.
Special attention must be payed to the mixer input amplitude, since the mixer performance
is strongly dependent on the LO amplitude. It is often desirable to treat the mixer and LO
buffer as one block where the input amplitude is allowed to vary, still ensuring proper
mixer operation.
If the tuning range is wide the output power level from the VCO will also vary with the
operating frequency [27]. In such cases there may be a need for an amplitude control
circuit or a limiting amplifier.

2.8.5 Power up and power down time

The time for the circuit to go from idle to active state is affected by how fast the bias is
reaching its correct values, how long until VCO:s reach their final amplitude etc. The
power up time is also affects the switch time of the PLL.
In PLL implementations, the reference oscillator usually have the longest power up time,
due to the high Q-value in the resonator. In application where the transceiver switch
between active mode when transmitting or receiving data, and power save mode between
data packages, the reference oscillator often have to be enabled up also in the power save
mode in order to achieve desired power up time.

2.8.6 Supply voltage and power consumption

Due to the CMOS scaling rules, allowed supply voltage tend to drop when moving to
more advanced processes The lower supply voltage and faster devices helps reduce the
power consumption, but limits the dynamic range of analog circuits.
In a PLL designs there is always a trade-off between performance and power. Parameters
such as the VCO phase-noise becomes better for when oscillation amplitude and power
increase. A circuit operating at high frequency also consumes more power than a low
frequency circuit.
In low power applications also the power down time and idle current consumption needs
to be taken into consideration, since if the PLL is active for only short periods of time, the
idle current may account for a considerable fraction of the total power consumption.
2.8. OTHER PLL DESIGN CONSIDERATIONS 35

2.8.7 Chip area

As well as the power-consumption it is desirable to minimize the chip silicon area. Also
in this case there is a trade-off between performance and area. The use of inductors may
allow reduced power consumption and improved performance, but are consuming large
area. High-Q on chip inductors consume more area compared to a low-Q inductor [59].
There is also a trade-off between isolation and area. More space between critical blocks
and wires are good for the isolation, but increase the chip area.
36 2.8. OTHER PLL DESIGN CONSIDERATIONS
Chapter 3

PLL modeling and simulation

Simulation of a PLL is relatively complex compared to the simulation of other transceiver

blocks. Due to the number of components involved, the non-linear operation and the
wide range of time-constants, traditional analog simulation techniques, such as transient
simulation using a Spice type simulator, are often not practical.
To handle the complexity and be able to predict PLL performance, several modeling ap-
proaches have been developed. Models of different levels of accuracy are useful at dif-
ferent stages in the design process. Each method has advantages and drawbacks, and
normally a combination of the different methods are used at different stages of the PLL
design.
Linear (s-domain) model
Although PLLs are inherently nonlinear circuits, PLL operation can in many circum-
stances be approximated using linear models.
Fully linear models are useful when sizing loop-filter components and doing stability
analysis [16][12]. The models are simple enough for hand-calculations, can be used in
spread-sheet calculations or incorporated in a small signal circuit simulation [25].
The linear models can also be extended to give an approximative prediction of PLL phase
noise. This topic will be handled in section 4.
Discrete time PLL models
The linear models do not take the sampled nature of the divider and phase detector into
account, giving incorrect results for frequencies close to the reference frequency. To over-
come this limitation, PLL models using discrete time state equations have been developed
[60][61]. These models are accurate also for frequencies close to the PLL reference fre-
quency, and are useful to predict the PLL lock time [33].

37
38 3.1. PLL TYPE AND ORDER

Numerical PLL models

The linear and discrete time models have the drawback of requiring recalculation of
analytical expressions when making changes to the circuit topology. When including
second order effects caused by for example interconnect and ESD components, the in-
volved expressions quickly becomes very complex. Also, effects such as spurious tones
in fractional-N synthesizers is difficult to predict using the analytical models. In many
cases it is therefore more convenient to use numerical simulations to predict the PLL per-
formance. Numerical models can be used to accurately simulate closed loop PLL [62],
and simulations are much faster than mixed signal simulations.
Behavioral and mixed signal PLL model
Analytical and numerical models are useful when dimensioning and designing the PLL
building blocks, but when implementing the actual circuit it is also necessary to verify all
connections to guarantee the blocks works correctly together. In practical circuit designs
it is therefore good practice not only to verify the interface between block using traditional
simulation techniques, but also simulate the complete PLL using mixed signal simulators.
To speed up the mixed signal simulation and still achieve accurate simulation results,
critical blocks such as the charge-pump and phase detector are simulated using accurate
spice-type schematics, but high frequency blocks such as the VCO and prescaler can
be modeled using behavioral models [63]. The mixed signal simulations runs quickly
compared to a transistor level simulation, and are able to accurately simulate switch time
including non-linear effects.
Spice simulation
Due to the very long simulation times, direct Spice type simulation is normally not prac-
tical during the design process. For example can a simulation of the locking performance
of a PLL take days or even weeks using modern circuit simulators. Even when possible
to simulate the produced results may not give much design insight. Also, due to the many
time steps, numerical accuracy and truncation errors may affect the simulation results.
It is however often useful to run at least one transient simulation in order to verify the
functionality of the complete PLL.
While Spice type simulation is currently not practical, this may change with increased
computational power and recent developments in simulation algorithms. Simulators de-
veloped with specific focus on PLL simulation [15] allows quick analysis of non linear
stochastic systems. While still limited to certain PLL topologies, simulation and noise
analysis by directly using the circuit schematic may be feasible in the near future.

3.1 PLL type and order

In literature PLL topologies are sorted into types and orders. Following the definition in
[12], the PLL type indicates the number of integrators in the loop. The PLL order is the
number of poles in the open-loop transfer function.
3.1. PLL TYPE AND ORDER 39

Type-I
The oscillator can be viewed as a phase integrator, and since there is always at least one
oscillator present in a PLL, the lowest PLL type is one.
This kind of PLL use a XOR type phase detector. [12] provides useful information re-
garding type-I PLL:s.
Since the type-I PLL have a limited lock range it is rarely used in analog frequency synthe-
sizers, but have many applications in frequency demodulation and clock recovery. Also,
recent implementations of All Digital PLLs can often be classified as Type-I [64].
Type-II
In a charge-pump PLL the loop-filter capacitor integrates the output current from the
charge-pump. This creates a second integrator in the PLL, and a charge-pump PLL is
therefore of type-II.
Due to the wide lock range and the theoretically zero phase difference between the output
and reference phase, the type-II is currently the most common PLL type in frequency
synthesizers.
Second order type-II PLL
While a second order type-II PLL is possible in theory, all practical PLL implementations
are at least of order II.
However, since the second order type-II PLL can be analyzed using parameters known
from control theory such as natural frequency ωn and damping factor ζ the second order
type-II PLL is commonly found in application notes [65] and literature [13].
Third order type-II PLL
The most common type and order found in literature and PLL frequency synthesizer im-
plementations targeting wireless applications is a charge-pump PLL using a second order
loop-filter. When a second order loop-filter is used in a PLL, the open-loop transfer func-
tion becomes order three. The third order PLL also has the advantage of always being
stable.
The third order type-II PLL topology will be studied extensively in following chapters.
PLL of higher order
To suppress noise and spurious tones, a loop-filter of higher order may often be required.
PLL:s using more than two integrators are also used in special applications, but are not
common in frequency synthesizers.
40 3.2. LINEAR MODELS OF PLL BUILDING BLOCKS

3.2 Linear models of PLL building blocks

Figure 3.1 shows the block diagram of a linear PLL model, and the corresponding model
equations.

Figure 3.1: PLL linear model

Classical small signal analysis of PLL loop-filter components in combination with Laplace
transforms of other frequency dependent blocks allows the PLL to be analyzed in fre-
quency domain. Using such models, the PLL transfer function can be calculated and the
PLL can be analyzed using common control theory.
The linear model is typically applicable for frequencies sufficiently lower than the PLL
reference frequency, and the model is only accurate when the phase error is small, i.e
when the PLL is locked. Outside this region the linear model will give wrong result, and
the model must therefore be used with care.
The linear model use different quantities in different nodes. All blocks in the linear model
operates in phase domain, except the charge-pump output, loop-filter and oscillator con-
trol node where voltage and current is used.
When using the linear model it is often practical to use phase disturbance rather than the
absolute phase when analyzing the PLL performance. The output voltage V (t) from a
signal having a constant amplitude A, frequency ω0 and phase disturbance θ(t) is

V (t) = A · sin(ω0t + θ(t)) (3.1)

The phase disturbance θ(t) is the deviation from the ideal phase, and can include random
zero-mean phase noise, initial phase errors and frequency drift.
In the linear model θo , θ f b and θre f represent the phase disturbance of the oscillator out-
put, feedback signal at the output of the divider and the reference oscillator respectively.
In order to analyze the circuit we need to derive linear models for all PLL building blocks.

3.2.1 Phase Frequency Detector and Charge Pump

Fig. 3.2 shows the block diagram of a typical zero dead zone phase-frequency detector
(PFD) and charge-pump (CP).
3.2. LINEAR MODELS OF PLL BUILDING BLOCKS 41

Figure 3.2: Implementation of a zero dead-zone PFD and Charge-Pump

The PFD is implemented using two edge triggered latches, and a delayed reset circuit. The
phase frequency detector is trigged by the edges of the reference and feedback signals, and
is reset once both edges have been detected.

Figure 3.3: PFD and charge-pump operation when the feedback signal lags, leads and are in phase.

Fig. 3.3 shows typical waveforms in the phase-frequency detector. When the VCO is
running too slow, the edges of the fb signal will come after the edges of the ref signal. This
will generate an up-pulse, increasing the frequency of the VCO (Fig. 3.3a). Accordingly,
when the edges of the fb signal come before the ref signal a down pulse is generated
(3.3b).
The up and down signals control switchable current sources in the charge-pump. The
width of the up- and down-pulses is proportional to the phase difference between the
feedback and reference signal. When the phase difference between the two inputs is
small, the output pulse would be very short. Since the charge-pump switches have a
limited speed it may not switch completely if the pulses are too short, creating a dead
zone for small phase errors where no current is output. To set a minimum width of the
pulses, a delay in the reset circuit is introduced. When the fb and ref signals are in phase,
up and down pulses of minimum length are generated (3.3c). A PFD using such a delay is
called a zero-dead zone PFD. The operation of this delay circuit is important for the noise
analysis, but do not affect the linear PLL model.
42 3.2. LINEAR MODELS OF PLL BUILDING BLOCKS

The average output current from the charge-pump will be proportional to the phase differ-
ence between the ref and fb signals (fig. 3.4) and can be expressed:

θre f − θ f b
Icp = KD · (3.2)
2π

where KD is called the phase-detector gain and is measured in amperes per radian. In the
linear model it is assumed the up and down currents are equal. The magnitude of KD is
then equal to the charge-pump pump current divided by 2π.

Figure 3.4: Linear model of Phase Frequency Detector and charge-pump

3.2.2 VCO model

Fig. 3.5 shows the oscillation frequency as a function of the control voltage for a typical
voltage controlled oscillator.

Figure 3.5: Linear model of VCO

Due to non-linear components in the oscillator, the oscillation frequency will not be di-
rectly proportional to the control voltage. For small changes in control voltage however,
the change in oscillation frequency is approximately proportional to the change in control
voltage. In the linear model it is assumed the oscillation frequency is proportional to the
control voltage. Expressing the oscillation frequency as a function of the control voltage
using a function f (VCtrl ), the relative frequency change for a change in control voltage
will be:

d
KVCO = f (V ) (3.3)
dV
3.2. LINEAR MODELS OF PLL BUILDING BLOCKS 43

KVCO is called the VCO gain factor or oscillator gain and is measured in Hz/V.
Since the oscillator gain will change depending on the control voltage, the linear PLL
model will only be valid for one frequency.
In some text-books the mathematically more correct concept instantaneous frequency is
used instead of frequency. The frequency of a signal is defined as the number of periods
in a unit time. Using this definition the frequency is only defined for a stationary sig-
nal. For non stationary signals it is mathematically more correct to use the instantaneous
frequency, defined as the derivative of the phase. In the following discussion we use the
definition of instantaneous frequency when discussion the frequency of the oscillator.
The phase of the oscillator if found by integrating the frequency:
Z t
θVCO (t) = θ0 + 2π f (V (t)) dt (3.4)
0

where θ0 is the initial phase of the oscillator. The phase disturbance used in the linear
PLL model can now be expressed using the oscillator gain KVCO :
Z t
θVCO (t) = 2πKVCO · Vctrl dt (3.5)
0

Laplace transforming equation (3.5) gives the oscillator transfer function:

θVCO 2πKVCO
= (3.6)
Vctrl s

Equation (3.6) is used in the linear PLL model.

3.2.3 Divider model

The transfer function of the frequency divider can be expressed:

θout 1
= (3.7)
θin N

where N is the division ratio of the divider.

To understand how the linear model of the frequency divider is derived it is illustrative to
study the waveforms at the input and the output of the divider, Fig. 3.6.
The divider is implemented as a counter where the output is changed after a predetermined
number of cycles. In the example in Fig. 3.6 the division ratio is two. A phase disturbance
at the divider input can be interpreted as a time shift ∆t. Since the divider is triggered by
the edges of the input signal, a time shift ∆t at the input will generate an equal time shift
44 3.2. LINEAR MODELS OF PLL BUILDING BLOCKS

Figure 3.6: A constant time difference corresponds to different phase shifts in a digital divider.

at the output. However, since the input and output period time is different, the relative
phase shift caused by the time shift ∆t is reduced by the division ratio.
In the example in Fig. 3.6, ∆t is 1/4 of a period at the input, corresponding to a phase shift
of 90◦ . At the output the phase shift is only 1/8 of the period, corresponding to a phase
shift of 45◦ .

3.2.4 Loop filter

The loop-filter contains only linear electrical components and can be directly analyzed
using classical small signal analysis. The implementation and order of the loop-filter
depends on the application, voltage ranges, required spurious suppression etc.
Second order passive loop-filter
The second order passive loopfilter, (Fig. 3.7), is the simplest and most common loop-
filter configurations.

Figure 3.7: Second order loop-filter

Since the configuration is simple enough to allow straight forward analytical analysis, we
will use the second order loop-filter in the initial discussion about loop-filter stability and
phase margin. Analysis can later be extended to higher order filters by using insights from
the simple filter.
The second order loop-filter have two poles and one zero. The zero is required in order to
give sufficient phase margin and a stable PLL operation.
The linear transfer function F(s) of the second-order passive loop-filter is:
3.2. LINEAR MODELS OF PLL BUILDING BLOCKS 45

Vout sC2 R + 1
F(s) = = (3.8)
Iin s(C1 +C2 + sC1C2 R)

where Vout is the voltage across the loop-filter and Iin is the current from the loop-filter.
Identifying the poles and zeros, equation (3.8) can be expressed:

1 + s/ωz 1
F(s) = · (3.9)
s(1 + s/ω p ) C1 +C2

where

C1 +C2
ωp = (3.10)
C1C2 R

and

1
ωz = (3.11)
RC2

The loop-filter component values are adjusted to give the PLL the correct bandwidth and
phase margin. Appendix A describes how to calculate the loop-filter components.
Third order loop filter
In order to suppress spurious content of reference spurs and noise from fractional-N PLL
synthesizers, it is often desirable to use a higher order loop-filter. Fig. 3.8 shows the
circuit diagram of a third order loop-filter.

Figure 3.8: Third order loop-filter

The extra RC link creates a pole at high frequency, suppression high frequency spurious
and noise.
The transfer function of the third order loop-filter is

1 + sC2 R2
F(s) = (3.12)
s(A2 s2 + A1 s + A0 )
46 3.3. LINEAR PLL MODEL

where

A0 = C1 +C2 +C3 (3.13)

A1 = C2C3 R2 +C1C2 R2 +C1C3 R3 +C2C3 R3 (3.14)

and

A2 = C1C2C3 R2 R3 (3.15)

Unlike the second order loop-filter there are no closed form expression for calculating
the exact loop-filter components. The components can however be calculated by using
approximations of the time constants, or by using numerical methods [13].
Other loop-filter topologies
PLL implementations having high spurious content, for example 3rd order fractional-N
PLL synthesizers, require higher order loop-filter to efficiently filter out high frequency
spurs.
In certain PLL implementations, for example where the varactor voltage range is required
to be higher than the available output swing of the charge-pump, an active loop-filter may
also be desirable. Active implementations and higher order loop-filter configuration can
be analyzed using the small signal PLL model, see [12] or [13] for details.

3.3 Linear PLL model

When the small signal models of all PLL building blocks are known the results can be
combined to calculate the transfer function of the total PLL. Using equation (3.2)), (3.6),
(3.7) and (3.8) the open loop-transfer function can be expressed:

KD 2πKVCO 1
G(s) = · F(s) · · (3.16)
2π s N
Figure 3.9 shows the corresponding open loop bode plot and pole-zero constellation for a
PLL using a second order passive loop-filter.
The loop-filter and the VCO form one pole each at the origin. The resistor forms a zero
together with C2 , improving the phase margin.
The open loop has unity gain at frequency ω1 , where

ω1 = 2π · BW (3.17)
3.3. LINEAR PLL MODEL 47

Figure 3.9: Loop-filter bode plot and corresponding poles and zeros

BW is called the loop-filter bandwidth. The loop-filter bandwidth is an important de-

sign parameter and is used to trade-off lock-time and phase noise. The BW need to be
sufficiently low in order to allow stable PLL operation.
In literature there are other definitions of the PLL band-width. In [12] the loop-gain K is
used to define the bandwidth of the PLL. K can be recognized as the open-loop gain in
the proportional path, excluding the 1/s factor caused by the integration of the VCO. For
all practical phase-margins the difference between K and BW is less than 1 dB.
The open-loop transfer function is an important tool to calculate bandwidth and phase
margin of the PLL. Is is however usually not possible to directly measure the PLL band-
width, since the infinite DC gain would cause PLL blocks to saturate.

3.3.1 System transfer function

Closing the loop gives the system transfer function:

KD KVCO F(s)
H(s) = (3.18)
s + KD KVCO
N
F(s)

The system transfer function describes how a phase disturbance at the reference input
propagates to the oscillator output.
For low frequency phase disturbances the open loop-gain is high and (3.18) reduce to
become equal to N, i.e. the gain is entirely determined by the feedback divider. This is the
48 3.4. DISCRETE TIME PLL MODEL

feature used in frequency synthesizers, where the output phase is exactly N times higher
than the reference phase.
For a third order type-II PLL the system transfer function is

s ω1z + 1
H(s) = BN · (3.19)
s3 ωNp + s2 N + s ωBz + B

where

KD KVCO
B= (3.20)
C1 +C2

ω p and ωz are calculated using equation (3.10) and (3.11).

3.4 Discrete time PLL model

The linear model is accurate only when analyzing frequencies sufficiently lower than the
reference frequency. For higher frequencies the linear approximation will introduce sig-
nificant errors. These errors affect the accuracy of lock time estimations as well as the
noise transfer functions. To overcome the limitations of the linear model the PLL can be
analyzed using discrete time models.
In the discrete time model the phase/frequency detecor is regarded as a sampler of the
phase error. The charge pump is assumed to inject current impulses where the charge is
proportional to the sampled phase error [10]. The loop gain of the discrete time system
can be calculated by obtaining the impulse invariant transform, as proposed in [60].
For a second order PLL the time-domain impulse response of the cascaded filter and VCO
is found by inverse transforming the open-loop gain G(s) [33]:

KC τ1
        
KC b−1 b·t
gC (t) = ·t + · · 1 − exp − (3.21)
b 2 b τ1

where KC = (KVCO ICP )/(2πNC1 ), τ1 = RC2 and b = 1 +C2 /C1 .

3.5 Numerical PLL models

Some aspects, such as modulated PLL:s and spurious tones in fractional-N PLL frequency
synthesizers, are difficult to accurately predict using the simple linear or discrete time PLL
models.
3.5. NUMERICAL PLL MODELS 49

While these aspects are possible to simulate using mixed signal PLL simulations, even
the speed improvements using behavioral models may not be sufficient during the de-
sign phase. Spurious simulation often require several iterations, and in order to find low
frequency spurious tones long simulation are required.

An elegant solution to achieve accurate yet fast simulations was proposed by in Perrott in
[36] and [62]. In a PLL, most noise is in the phase information and not in the amplitude.
The proposed simulation method use fixed and relative long time steps when running a
time domain simulation. The relative phase of all clocks are represented using floating
point numbers.

Figure 3.10: Conversion of contious time waveform to discrete time samples for digital a) and
analog waveforms b).

Behavioral models of digital logic are written so the phase information of all clocks are
preserved (Fig. 3.10a). The transient response of analog blocks such as the loop filter are
modeled using state equations. (Fig. 3.10b). Noise from oscillators passive components
are incorporated as random fluctuations on the signals.

In [62] PLL building blocks are modeled using behavioral models written C++. The
resulting net-list is compiled and executed, giving very efficient simulations. The software
CppSim is available for free download [66].

While it is somewhat difficult to write new analog blocks, logical functions such as PLL
noise shapers are easy to describe using standard C++ code. This makes the CppSim sim-
ulator useful to explore noise shaper implementations, where reference spurs and phase
noise can be simulated and evaluated.

An alternative modeling approach is proposed in [61] where the PLL is modeled exactly
using state equations. In this method the transient response of the loop-filter components
are calculated exactly, giving a low number of time steps required. While accurate, the
method requires extensive recalculation of the equations involved, and the method is thus
not very flexible.
50 3.6. MIXED-SIGNAL PLL MODEL

3.6 Mixed-signal PLL model

Before manufacturing a circuit it is desirable to run a top level verification. The goal of the
simulation is to verify the top-level functionality i.e check that all connections are correct,
that no polarities are switched and that all bias and enable signals have the right direction
and magnitude.
I order to avoid potential mistakes when creating schematics and test-benches, the top
level simulation should ideally be performed using the same schematic as used when
running layout verification.
Running such a simulation using the full Spice net-list would be very time consuming,
especially when including digital blocks such as calibration circuits and Σ∆ noise shaping
logic. It is therefore necessary to create simplified simulation models that still are capable
of accurately simulate the performance of the PLL.
Modern circuit simulators are capable of running so called mixed-signal simulations,
where different parts of the circuit are described using different modeling techniques.
Analog blocks can be modeled using either traditional Spice net-lists or using hardware
description languages (HDL) such as VHDL AMS or VerilogA. Digital blocks are mod-
eled using Register Transfer Level (RTL) output from synthesis tools or using HDL de-
scriptions.
Fig. 3.11 shows a typical partition between different blocks in a fractional-N PLL fre-
quency synthesizer.
The idea behind the mixed signal model is to provide an accurate model of the PLL
operation that is still efficient to simulate.

• Blocks operating at low frequency such as bias circuits and the phase-frequency
detector, charge-pump and loop-filter are simulated using the spice net-lists. This
is done in order to capture potential errors such as connecting the bias to the wrong
polarity, switching signals and also correctly model output swing and saturation
problems in the charge-pump. Parasitic components such as bond pad capacitance
and ESD protection can also be included in the loop-filter model.
• Blocks containing many logical gates such as calibration logic and noise shaper
will have a large number of transistors, and is therefore expensive to simulate us-
ing a spice simulator. Such blocks are more efficient to simulate using either the
VHDL or Verilog code directly, or preferably the RTL code output from the digital
synthesis tool.
• High frequency blocks such as the VCO and the input stage of the prescaler need
very short time steps if simulated directly using a Spice simulator. In the mixed
signal model the high frequency paths of these blocks is modeled using behavioral
models, where the time domain RF signals are replaced by a voltage representing
the frequency.
3.6. MIXED-SIGNAL PLL MODEL 51

Figure 3.11: Models used for different blocks in mixed signal simulation. In order to speed up
simulation, the high frequency signal at the VCO output is simulated using a voltage representing
the frequency.

The partition between the blocks are not fixed, and different representations having more
or less accuracy can be used during the design process. For example may the bias cir-
cuit be replaced by ideal current sources an the initial simulations to further speed up
simulation.
In addition to the behavioral top-level simulation is it also useful to run at least one DC
or transient simulation of the complete top level and verify the all supply and ground nets
are correct and all blocks properly biased.
In the following section examples of behavioral models of a VCO and divider are de-
scribed in detail.

3.6.1 Behavioral VCO model

In order to capture the non-linear tuning voltage to frequency performance and also in-
clude effect of trim codes, the VCO frequency can be described using a simple equation.
In this section the high frequency oscillator in TripleTraC paper 4 serves as an example for
the behavioral modeling. Fig. 3.12 shows the simulated and measured frequency versus
control voltage for LO1. The frequency is plotted for three different trim codes. Due to
somewhat inaccurate varactor models, the simulated and measured frequency do not agree
exactly. The behavioral model is modeled based on the measured frequency response.
52 3.6. MIXED-SIGNAL PLL MODEL

Figure 3.12: Simulated, measured and modeled frequency vs control voltage for three different
trim codes.

The frequency response could be modeled using a table and linear interpolation, but in
this example a simple mathematical model could easily be obtained by manually curve
fitting the model to the measured data.
Since the inductance of the oscillator is fixed, The output frequency is determined by
the sum of the trim capacitor and the varactor. The oscillation frequency can then be
described:

1
f= p (3.22)
2π L · (Ctrim +Cvar )

L, Ctrim and Cvar can be found by curve fitting the model to measured or simulated data.
In the example in Fig. 3.12 it was found the varactor could be accurately represented by a
tanh function:

Cvar (VCtrl ) = 1.05 − 0.2 ∗ tanh(2.5(VCtrl − 0.2)) (3.23)

The values and the function dependent on the actual oscillator implementation, and equa-
tion (3.23) is only valid for the oscillator in paper 4. The trim capacitor is proportional to
the trim code:

Ctrim (Trimcode) = 1 − 0.075 ∗ Trimcode (3.24)

3.6. MIXED-SIGNAL PLL MODEL 53

When fitting the curves it is important not only to get small errors for the absolute frequen-
cies, but also to have correct derivative of the curves. The derivative determines the VCO
gain, and wrong gain may result in incorrect lock times or even unstable PLL operation.
When frequencies are represented by a voltage in the simulation it may be necessary to
scale the numerical values in order not to create accuracy problems in the simulator. In
the modeled example 1 GHz is represented by 1 V in the simulator rather than 1 GV since
such high voltage would create ill-conditioned matrices and warnings from the simulator.
The behavioral model of the oscillator can be implemented using voltage dependent volt-
age sources, or written in a hardware description language.
A complete listing of the VerilogA implementation of the example VCO is available in
Appendix B.1. This model also include checks for the bias current and enable signals by
using if clauses.

3.6.2 Behavioral Divider model

Fig. 3.13 shows the block diagram of a behavioral model of the divider.

Figure 3.13: Divider behavioral model.

The input signal into the model is a voltage representing the frequency. The input signal
is divided by the divider division ratio N.
Since the output signal should be a time domain waveform, the divider is implemented as
a voltage controlled oscillator.
A window comparator and control logic verifies the bias current and enables the output
only when bias is within acceptable limits.
To correctly capture the output slope and driving capability of the divider, an inverter is
inserted at the output of the divider. This buffer is modeled using accurate Spice transis-
tor models. Using Spice models of the buffer also verifies that the supply voltages are
correctly connected.
54 3.7. SIMULATING PLL PERFORMANCE

In most divider implementations the division ratio is updated only when the counter has
reached it full value, in order to avoid erroneous values when changing division ratio. In
the behavioral VerilogA implementation this is implemented by latching the division ratio
when a full division cycle is completed.
The complete VerilogA representation of the divider is available in Appendix B.2.

3.7 Simulating PLL performance

Using the PLL models, performance parameters such as bandwidth, phase-margin, stabil-
ity and settling time can be simulated.

3.7.1 Stability

PLL stability can be analyzed using the linear PLL model and methods known from con-
trol theory, such as root-locus, bode plots and the corresponding stability measures phase-
and gain margin.
As long as the loop-filter bandwidth is low enough for the linear PLL model to be valid,
a second order loop-filter is always stable. However, parasitic components may introduce
higher order poles, and the phase shift from these poles may decrease the phase margin.
Variation in loop-gain due to changes in PLL division ratio and non-linear oscillator tuning
curve may also degrade phase margin at under certain operation conditions.
Fig. 3.14 shows the bode plot of a PLL using a 3rd order loop-filter for two different open
loop gain settings. For the nominal gain there is sufficient phase margin (PMNom in Fig.
3.14). Increasing the loop gain, for example by reducing the divider setting to a very small
value, gives negative phase margin and unstable PLL operation (PMHighgain in Fig. 3.14).
Note that changing the loop gain do not affect the position of the poles and zero, and the
phase of the open-loop transfer function is identical for both loop gain settings.
The unstable operation can also be illustrated by using a root locus plot of the system
transfer function, as illustrated in Fig. 3.15. When the division ratio is decrease, the poles
split and moves towards the right half plane. A real PLL implementation should of course
be designed to be stable for all loop-gains.
For loop-filter bandwidth higher than approximately 1/5 of the reference frequency, the
linear PLL model fails and the PLL may become unstable, even when the linear model
predicts a stable system [33]. To guarantee stable operation the conventional approach is
to limit the PLL bandwidth to 1/20 of the reference frequency [10].
In special applications may limiting the bandwidth to 1/20 of the reference frequency give
unnecessary long lock times. Using the dead-beat response it is possible to design a stable
stable loop filter having higher cutoff frequency in order to achieve faster settling time
[33].
3.7. SIMULATING PLL PERFORMANCE 55

Figure 3.14: Bode plot of PLL using 3rd order loop filter for two different settings of feedback
divider ratio.

3.7.2 Settling time

Using the linear PLL model, the PLL lock time can be estimated by calculating the tran-
sient response for a frequency change.
For a second order PLL it is trivial to calculate the exact frequency response using param-
eters known from control theory such as natural frequency ωn and damping ζ.
For a third order PLL having a bandwidth lower than 1/20th of the reference frequency
the lock time can be estimated by neglecting the zero and the third pole.
The lock time can then be approximated:

1 ∆ωout
ts = · ln (3.25)
ξ · ωBW ∆ωerr

where ωerr is the closed-loop bandwidth and ξ is the damping factor of the complex
conjugate poles:

ξ = cos(α p ) (3.26)
56 3.7. SIMULATING PLL PERFORMANCE

Figure 3.15: Root locus when sweeping feedback divider ratio. The PLL becomes unstable for
small division ratios.

α p is the angle of the complex poles in the closed loop transfer function. Placing the
poles 45◦ on the root locus does not provide the fastest settling time as would be expected
from the second order PLL approximation [33]. Instead the fastest settling is achieved by
placing the the tree poles at equal distance from the origin of the axes.
The settling time can be calculated by simulating the transient response of the PLL. Fig.
3.16 and 3.17 shows the simulated frequency versus time for a third order loop-filter when
switching from 1.5 to 1.4 GHz (LO2 in Paper 4 and 5). The transient response is simulated
using both linear PLL model (Fig. 3.16) and behavioral model (Fig. 3.17).
The linear PLL is not accurate for lock time simulations since it do not include non-linear
effects such as cycle slipping and variations in VCO gain into account, but may still be
preferred in initial PLL simulations since its simulation times are short enough to allow
iteration of different loop filter settings. The lock time is also easier to estimate using the
linear model, since the waveform is not influenced by high ripple caused by the charge-
pump operation.
3.7. SIMULATING PLL PERFORMANCE 57

1500
Frequency

1480

1460
Frequency (MHz)

1440

1420

1400

1380
0 1e-05 2e-05 3e-05 4e-05 5e-05
Time (s)

Figure 3.16: Lock transient simulated using linear model

1500
Frequency

1480

1460
Frequency (MHz)

1440

1420

1400

1380
0 1e-05 2e-05 3e-05 4e-05 5e-05
Time (s)

Figure 3.17: Lock transient simulated using behavioral PLL model

58 3.7. SIMULATING PLL PERFORMANCE
Chapter 4

PLL noise analysis

This chapter describes the phase-noise properties of PLL building blocks and how the
knowledge of block noise can be combined to predict the phase-noise performance of a
locked PLL.

Since the PLL blocks are non-linear, noise will fold and noise also at high frequency
will be important also for blocks operating at low frequency. Due to the strongly non-
linear operation, traditional AC noise analysis is not applicable when calculating the noise
properties of PLL building blocks. Instead, non-linear methods taking the time varying
noise sources and switching operation have to be used.

Understanding the noise mechanisms of the PLL blocks is important, not only in order to
design frequency synthesizers having good spectral purity, but also to correctly configure
circuit simulators.

4.1 Noise in digital circuits

Digital PLL blocks such as the prescaler and phase-frequency detector are not sensitive
to noise in traditional meaning, but do still contribute to PLL phase noise since noise in
digital gates is translated to timing jitter.

Analytical jitter expressions and trade-off between noise and power consumption in bal-
anced differential pair prescalers was investigated in [18].

If a digital circuit is driven by a periodic signal, the timing uncertainties in the transition
can be interpreted as timing jitter or phase noise [67]. The phase-noise in digital circuits
increase linearly with increased frequency and number of cascaded gates [68],[69].

59
60 4.1. NOISE IN DIGITAL CIRCUITS

4.1.1 Amplitude noise to jitter conversion

Assume the noise free output from a digital circuit is a T-periodic signal having a wave-
form v(t) (Fig. 4.1). Due to noise in devices, supply and interconnect etc. this waveform
is displaced by a stochastic process n(t). The voltage at the output of the digital circuit
can then be expressed:

vn (t) = v(t) + n(t) (4.1)

If the digital circuit is realized using electrical component it can be assumed that n(t) is a
T-periodic cyclo-stationary zero-mean Gaussian process.

Figure 4.1: Noise to jitter conversion in digital gate.

Noise at the input of a digital gate will propagate to the output only at the switch transition,
i.e. when the input voltage is close to the threshold voltage of the gate. If the switch
transition occurs at time tc the timing jitter at the output of a gate is equal to the noise
voltage at the input divided by the derivative of the switch transition. If the output timing
jitter is a function p(t), the variance at the time of the transient can be calculated:

σ2n
σ2p = (4.2)
dv 2


dt

where dv/dt is the slope at the time tc .

Since vt is a periodic signal, the phase of the output is sampled at fout = 1/Tout . Due to
the sampling process, noise at frequencies around all harmonics of fout will fold and con-
tribute to the total output jitter. If fout is considerable lower than the noise bandwidth the
frequency distribution of the jitter σ2p will be relatively white even when n has a frequency
dependency.
If σ2p can be considered to be white, the phase noise at the digital output is [18]:
4.1. NOISE IN DIGITAL CIRCUITS 61

Ldig = 4π2 fout · σ2p (4.3)

The amplitude noise can be directly simulated using a modern circuit simulator. Fig.
4.2 shows the output waveform and the corresponding time varying noise power spectral
density.

Figure 4.2: Noise at the output of a digital gate simulated using SpectreRFT M simulator

The plot clearly shows the noise has its peak at the transitions. It also shows that the noise
when switching from high to low state is slightly higher than the noise when switching
from low to high. This is due to the somewhat higher transconductance of the NMOS
devices. The jitter is however lower on the falling edge despite the higher noise voltage,
since the voltage derivative is higher on the falling slope.
In many applications only one of the edges is important for the phase noise. For example
is the input of the phase frequency detector normally only detecting the rising edge. This
has to be taken into consideration when calculating the PLL phase noise.

4.1.2 Phase noise in cascaded digital circuits

When several digital blocks are cascaded and the noise in each block is uncorrelated,
the total phase noise can be calculated by adding the variance of each block. The total
62 4.2. PHASE FREQUENCY DETECTOR

variance will be:

n
σtot
2
= ∑ σ2i (4.4)
i=1

The cascaded noise for an asynchronous divide by 8 circuit is illustrated in Fig. 4.3a. For
each gate the jitter increase. In order to keep the noise down the logical depth should be
minimized. A way to do this is to synchronize the output to the input clock [70] (Fig.
4.3b). Synchronizing the block also simplifies the noise calculation, since only the signal
path affected by the clock has to be taken into account (Fig. 4.3c).
The magnitude of the digital jitter can be improved by proper choice of circuit implemen-
tation, and simple re-timing schemes may reduce the amount of phase noise originating
from digital circuitry such as prescalers significantly .

Figure 4.3: Resamling of clock reduce jitter in divider.

4.2 Phase Frequency Detector

Jitter in digital gates and the reset delay circuit in the Phase Frequency Detector will
propagate to the output and be converted to current noise in the charge-pump. Due to the
4.2. PHASE FREQUENCY DETECTOR 63

operation of the charge-pump, the gate jitter can not be added directly as they can is the
case in cascaded digital circuits.
Fig. 4.4a shows a principle diagram of a zero dead zone phase frequency detector and the
corresponding output current from the charge-pump.

Figure 4.4: Noise in phase frequency detector.

The output current from the PFD/Charge-Pump combination can be divided into three
regions:
During the time toc the charge-pump is pumping current. The width of the current pulse is
proportional to the time difference between the reference and feedback clock rising edges.
The position of the edges will have a timing uncertainty determined by the jitter originat-
ing from the digital circuits. The variance of the output current will be proportional to
Iout multiplied by sum of the timing variance of the rising and falling edge. Assuming the
reference and feedback path have equal variance, the total variance of the output current
in the pump pulse will be:

σ2Ioc = 2 · Iout
2
· σ2oc (4.5)

where σ2oc is the variance of the clock edges. The unit of the current variance is A2 .
During the dead zone pulse td the output current from the charge-pump depends on the
matching α between the up and down current, i.e. the output current during the dead-zone
pulse will be Icp ·α. The length of td is determined by the propagation delay of the gates. If
the variance of the dead-zone pulse is σ2dz the variance of the charge-pump output current
due to the delay jitter will be:

σ2Idz = (αIout )2 · σ2dz (4.6)

64 4.3. FOLDING OF NOISE AND INTERFERERS IN CHARGE-PUMP

i.e. for a perfectly matched charge pump jitter in the dead-zone reset circuit will not
contribute to the output noise.
In the third region, when there is no current in the charge-pump the PFD make no contri-
bution to the output noise.
By combining equation (4.5) and (4.6) the total variance of the output current can be
calculated:

σ2Itot = Iout
2
· (2σ2oc + α2 σ2dz ) (4.7)

The timing jitter of the digital gates in the phase-frequency detector can be simulated
using the same methods as when simulating jitter in digital circuits.
Referring the noise to the input, jitter in the PFD can be summed with jitter in other digital
circuits in the clock signal paths.

4.3 Folding of noise and interferers in Charge-Pump

When the PLL is locked the average output current from the charge-pump will be zero,
but the charge-pump will still produce noise pulses during the "dead-zone" pulse.
The charge-pump operation can be viewed as a sample-track or natural sampling opera-
tion, where the noise current is delivered to the loop filter during the dead-zone pulse, and
is zero otherwise, as illustrated in Fig. 4.5.

Figure 4.5: Charge pump noise sampling.

When the PLL is locked, the current sources will be switched by a periodic function r(t)
having a pulse width equal to td and a period T = 1/ fre f . fre f is the frequency of the
reference clock. r(t) is one during the dead-zone pulse and zero otherwise.
4.3. FOLDING OF NOISE AND INTERFERERS IN CHARGE-PUMP 65

Due to the sampling operation, noise at harmonics of the reference clock will fold into
frequencies within the PLL band-width. The noise sampling for white + 1/f noise was
analyzed in [20]. A more elaborate investigation of the effects of interferers and noise
filtering is presented in paper 6.
In the following noise analysis it is assumed all charge-pump noise is originating from
the current sources and that the switch operation is instantaneous and do not contribute to
the noise. We can then express the modulating signal current in the charge-pump using a
random process x(t).
The time domain output current from the charge-pump can then be expressed:

z(t) = r(t) · x(t) (4.8)

In sampling theory this is called a "switched sampling" process [71]. If x(t) has a Fourier
transform X( f ) the resulting output spectrum can be calculated:

Z( f ) = R( f ) ∗ X( f ) (4.9)

The Fourier transform R( f ) can be obtained from the Fourier series coefficients of r(t).
If we define the periodic function r( f ) to be 1 for −td /2 < t − nT < td /2 and 0 otherwise
the Fourier coefficients cn will be:

Z T
1 i2πnt sin(nπtd fre f ) td ntd
cn = r(t)e− T = = sinc( ) (4.10)
T 0 nπ T T

The resulting output spectrum Z( f ) can be expressed:

∞
Z( f ) = ∑ cn · X( f − n fre f ) (4.11)
n=−∞

Equation (4.11) shows that interferers at all harmonics of fre f will be folded to a low
frequency. Interferers at frequencies close to multiples of the reference frequency are
of special interest since they will fold to frequencies within the PLL bandwidth. These
frequencies will not be filtered out by the loop-filter and will thus modulate the VCO.
If x(t) is a stochastic signal represented by a noise power spectral density Sx ( f ) the re-
sulting output spectral density Sz ( f ) can be calculated:

∞
Sz ( f ) = ∑ |cn |2 · Sx ( f − n fs ) (4.12)
n=−∞

Since cn = c−n and Sx (− f ) = Sx ( f ) the spectrum can be rewritten:

66 4.3. FOLDING OF NOISE AND INTERFERERS IN CHARGE-PUMP

∞
Sz ( f ) = c20 Sx ( f ) + ∑ |cn |2 · (Sx (n fs + f ) + Sx (n fs − f )) (4.13)
n=1

In all real circuit implementations it can safely be assumed that Sx is constant for small
frequency offsets ( f << fs ) around harmonics of the reference frequency, with the ex-
ception of DC where the circuit may experience flicker noise. Equation (4.13) can then
be approximated:

∞
Sz ( f ) ≈ c20 Sx ( f ) + 2 ∑ |cn |2 · Sx (n fs ) (4.14)
n=1

Equation (4.14) can be interpreted as that noise at low frequency will be weighted a factor
c0 and noise around harmonics of the reference frequency will be weighted and folded to
low-frequency according to Fig. 4.6a and b.

Figure 4.6: Folding of noise in charge-pump.

The down-converted noise will modulate the VCO and create sidebands around the oscil-
lator output (Fig. 4.6c).

4.3.1 Special case white + 1/f noise

A special but very common special case is where the noise distribution is white with the
addition of low frequency 1/f noise. In this case the noise calculations can be significantly
simplified. In this case Sx can be expressed:
 
fc
Sx ( f ) = Sw · 1 + (4.15)
f
4.3. FOLDING OF NOISE AND INTERFERERS IN CHARGE-PUMP 67

where Sw is the power spectral density of the white noise, and fc is the flicker noise
corner, i.e. the frequency where the flicker noise have the same power spectral density as
the white noise.
White noise
The contribution of the white noise to the charge-pump output noise can be calculated

∞ ∞
Szw ( f ) = ∑ |cn |2 · Sw = Sw · ∑ |cn |2 (4.16)
n=−∞ n=−∞

Using Parseval’s identity (4.16) can be rewritten:

Z T
1 td
Szw ( f ) = Sw · |r(t)|2 dt = Sw (4.17)
T 0 T

Equation (4.17) tells us that the white noise will be attenuated with the duty cycle of the
dead zone pulse.
1/f noise
The 1/f noise will according to equation (4.14) only have significant magnitude for the
first Fourier coefficient c0 . c0 can be calculated:

Z T
1 td
c0 = f (t)dt = (4.18)
T 0 T

The charge-pump noise is the sum of the white and 1/f noise components and the total
noise spectral density can be expressed:

 
td fc td
Sz ( f ) = Sw · + · ( )2 (4.19)
T f T

Equation (4.19) shows that due to the sampling nature of the charge-pump the output noise
power and flicker noise corner will both be lower by a factor td /T compared to the current
source noise. This can be interpreted as the output noise is lower and will be "white"
compared to the noise in the current sources.
Fig. 4.7 shows the simulated noise at the output of the charge-pump as a function of
the voltage. Since the output noise from the charge-pump is not constant, PLL operation
should be verified at the control voltage where the charge-pump noise is highest.
Methods to reduce charge-pump noise and interferers by adjusting the dead-zone pulse
width is discussed in paper 7.
68 4.4. OSCILLATOR PHASE NOISE

Figure 4.7: Charge-pump output noise vs loop-filter voltage.

4.4 Oscillator phase noise

From a system level perspective it is observed that the phase noise distribution of an
oscillator often can be divided into three distinct regions. Fig. 4.8 shows the phase noise
of a typical free running oscillator.

Figure 4.8: Typical phase-noise distribution of a free running oscillator

For moderate frequencies the phase noise drops 20 dB/decade. Close to the carrier the
phase noise drops more than 20 dB/decade. Often there is a 30 dB/decade region due to
up-converted flicker noise, but close to the carrier the slope of the phase noise can be even
steeper. Really close to the carrier, the phase noise will flatten out or increase infinitely,
depending if the plots shows the normalized spectrum or the phase noise spectrum as
discussed in section 2.4.1.
4.4. OSCILLATOR PHASE NOISE 69

For large frequency offsets the phase-noise is relatively flat. Phase noise at large offsets
may not originate from the oscillator, but rather be the phase component of the additive
noise generated by amplifiers following the oscillator.
When the phase noise follows the distribution in Fig.4.8, the normalized phase noise L
(not taking the region very close to the carrier into account) as a function of the frequency
offset ∆ω can be expresses using the so called Leeson-Cutler model after two well sited
publication [72] and [73].

∆ω1/ f 3
2 !  !
ω0

2FkT
L (∆ω) = 10 log · 1+ · 1+ (4.20)
Ps 2QL ∆ω |∆ω|

In this model Ps express the oscillator output power, ω0 is the oscillation frequency, QL
is the loaded Q of the oscillator tank and ω1/ f 3 is the transition frequency between the 20
and 30 dB/decade regions. k and T is Boltzmann’s constant and the absolute temperature
respectively. F is an empirical noise fitting parameter.

4.4.1 Oscillator Impulse Sensitivity Function

A problem with the Leeson-Cutler model is that F and ω1/ f 3 have to be found empirically,
since the strongly non linear operation of an oscillator makes traditional small signal noise
calculation fail when calculating oscillator phase noise.
A general theory how noise sources in an oscillator converts to phase and amplitude noise
was proposed in [74]. A similar and somewhat simplified but more intuitive method to
understand phase noise was presented in [17], with minor corrections in [75] and [76]. A
comparison of the methods in [17] and [74] is presented in [77].
The theory in [17] is based on the so called Impulse Sensitivity Function (ISF) describing
how oscillator noise is affected by a current disturbance.
According to the ISF theory, the phase perturbation of an oscillator depends on where in
the oscillation cycle an interfering signal is injected. Fig. 4.9 shows the phase shift of an
LC-tank oscillator when a current impulse is injected at different instants in the oscillation
cycle.
When the current is injected at the oscillation peak amplitude (Fig. 4.9a), there will be an
amplitude but no phase shift in the oscillator. A current impulse when the amplitude is
zero (Fig. 4.9b) on the other hand cause a phase shift but no change in amplitude.
Since a stable oscillator has mechanisms to control the oscillation amplitude, an amplitude
disturbance will not sustain. In a free-running oscillator there is however no mechanism
to control the phase, and any phase fluctuation will persist indefinitely.
From the intuitive discussion we understand that the phase sensitivity of an oscillator
depends on the instance when the pulse is injected. By plotting the relative phase shift as
70 4.4. OSCILLATOR PHASE NOISE

Figure 4.9: Phase shift due to current impulse in oscillator

a function of the phase φ where a pulse is injected, the Impulse Sensitivity Function Γ(φ)
can be expressed. Γ(φ) is a dimensionless 2π periodic function.
Using the ISF we can calculate the oscillator phase noise. The phase noise L caused by a
noise source i2n can be calculated by Fourier expanding Γ.

 ∞
 ∑ n
i2n
∆f c 2
n=0
L (∆ω) = 10 log  
(4.21)
 4qmax ∆ω2 
 2 

where cn are the Fourier components of Γ and qmax is the maximum charge stored in the
oscillator. ∆ω is the offset frequency from the carrier.
Fig. 4.10 shows the ISF for different oscillators. The ISF is approximately proportional to
the derivative of the oscillator waveform. In an oscillator having non sinusoidal waveform,
the ISF will therefore be non symmetrical (Fig. 4.10a). A ring oscillator (Fig. 4.10b) is
only sensitive to noise in the transitions and the ISF is pulse like.
In the following sections the ISF will be used to express the phase noise of oscillators
having a sinusoidal waveform. A general explanation of noise calculation using the ISF
method is available in [17].

4.4.2 Cyclo-stationary noise sources

Since the voltage swing in an oscillation is large enough to cause the bias point of active
components to change, oscillator noise sources will not be stationary. In order to correctly
4.4. OSCILLATOR PHASE NOISE 71

Figure 4.10: Impulse Sensitivity Function for different oscillator waveforms.

calculate the phase noise it is therefore important to take into account not only when the
noise is injected, but also how the noise is varying during the oscillation cycle.
A noise source that is varying periodically is called cyclo stationary and can be expressed

in (t) = in0 (t)α(ω0t) (4.22)

where in0 (t) is a stationary white noise process and α(ω0t) is a 2π periodic weighting
function describing how the noise is varying over the oscillation cycle. ω0 is the oscillator
frequency.
A weighted sensitivity function Γe f f taking the time varying noise into account can be
calculated:

Γe f f (φ) = Γ(φ)α(φ) (4.23)

When calculating the phase noise of an oscillator containing time varying noise sources
Γe f f should be used.

4.4.3 Special case white noise + 1/ f noise

In real oscillators the noise spectrum can often be expressed in terms of white noise and
low frequency 1/ f noise. In this special but common case, phase-noise calculations can
be greatly simplified.
The phase noise due to a white noise current is proportional to the square of the RMS
value of Γ [75]
72 4.4. OSCILLATOR PHASE NOISE

!
i2w Γ2
L (∆ω) = 10 log · 2 rms 2 (4.24)
∆ f 2qmax ∆ω

where qmax is the maximum charge in the oscillator capacitance and ∆ω is the offset
frequency from the carrier. In an LC oscillator qmax is equal to the peak voltage multiplied
with the resonator capacitance.
Equation (4.24) can be interpreted as the white noise creates a region around the oscillator
where the phase noise is inversely proportional to ∆ω2 i.e. the noise drops 20 dB per
decade.
In order to reduce the influence of white noise, the noise power spectral density can be
decreased, Γrms can be minimized by carefully sizing oscillator devices as will be dis-
cussed in chapter 5. Phase noise can also be reduced by increasing the maximum charge
qmax . In LC oscillators this can be achieved by increasing the oscillation amplitude or by
increasing the capacitance keeping the amplitude and frequency constant by increasing
the current and reducing the inductance.
The 1/ f noise will create a region at small frequency offsets where the phase noise drops
30 dB/decade. According to the ISF theory the transition frequency between the 20 and
30 dB/decade regions ω1/ f 3 can be calculated

Γavg
 2
ω1/ f 3 = ω1/ f · (4.25)
Γrms

where Γavg is the average value of Γe f f . In order to minimize the 1/f noise contribution,
the waveforms should be symmetrical giving a small DC level of the ISF.
Note that since the ISF theory do not take amplitude variations into account, the results
predicted by equation (4.25) will not be accurate in the presence of non linear capacitors.
For more accurate calculations the methods suggested in [74] should be used. Since the
phase noise calculations in most circuit simulators use methods similar to [74], the ac-
curacy of phase noise simulations are usually determined by the device model accuracy
rather than the calculation method.

4.4.4 White noise in LC oscillators

In oscillators where the waveform is sinusoidal, for example in LC tank oscillators, the
ISF can be directly calculated. A cosinusoidal tank voltage Vo (φ) having a peek voltage
A0 is expressed

Vo (φ) = A0 · cos(φ) (4.26)

4.5. REFERENCE OSCILLATOR NOISE 73

and the corresponding tank ISF, Γtank will be [17]

Γtank (φ) = sin(φ) (4.27)

The RMS value Γrms,tank of (4.27) is

s
Z 2π
1 1
Γrms,tank = sin2 (φ)dφ = √ (4.28)
2π 0 2

In an LC tank resonator having an inductance L, a capacitance C and an equivalent parallel

resistance RP across the tank, the noise contribution from the resistor is

4kT
i2R p /∆ f = (4.29)
RP

where k is Bolzmann’s constant and T the absolute temperature. Combining equation

(4.24), (4.28) and (4.29) the 20 dB/decade portion of the oscillator phase noise can be
directly calculated:
 
kT
L (∆ω) = 10 · log (4.30)
RPVo2 (C∆ω)2

The noise predicted in equation (4.30) is the minimum achievable phase noise for a LC
resonator having an equivalent parallel resistance RP .

4.5 Reference oscillator noise

The phase noise from the reference oscillator can be calculated using the same methods
as for other oscillators as described in section 4.4. Thanks to the high quality resonator,
the phase noise of the reference oscillator is usually very low, but reference oscillator will
still dominate the PLL noise at certain frequencies.
Since the reference oscillator is a free-running oscillator, the phase noise will have a
large magnitude at small frequency offsets. For this reason the reference oscillator always
dominates the phase noise at small frequency offsets in a PLL.
The PLL phase-noise originating from the reference oscillator is also much higher than
the reference oscillator noise itself, since inside the PLL bandwidth the reference phase
is multiplied by the PLL division ratio. For PLL:s having a high division ratio, reference
oscillator noise may dominate also at relatively large frequency offsets.
In many applications, phase-noise on the reference clock do not originate from the oscil-
lator itself, but rather from the oscillator buffer. Noise from the oscillator buffer can be
74 4.6. NOISE IN ∆Σ NOISE SHAPER

calculated using the same methods as for digital blocks. The reference oscillator buffer
must have very low amplitude noise, since the input voltage coming from the oscillator
is sinusoidal and has a relatively low amplitude. The maximum derivative of the input
voltage will therefore be low, giving high phase noise according to equation (4.2).

4.6 Noise in ∆Σ noise shaper

Noise analysis of ∆Σ noise shapers and their impact on PLL systems is a broad research
topic in itself. A more detailed analysis of the ∆Σ noise shaper and the impact on the PLL
phase-noise performance is beyond the scope of this work, and this section will only give
a brief explanation of the noise-shaper impact on the PLL noise. For a more complete
description the reader is referred to [19] and [20].
The ∆Σ noise shaper modulates the least significant bits of the PLL divider, giving an
average division ratio other than an integer value. When the PLL is locked, the average
charge-pump current will be zero, but due to the operation of the noise shaper, short up
and down pulses will still be generated. The current generated by these pulses can be
viewed as a zero mean error current i∆Σ superimposed on the charge-pump output current.
The Σ∆ noise shaper is designed so the power spectral density of i∆Σ has most power at
high frequency. Ideally, the noise current is then filtered out by the PLL loop-filter.
However, due to non-idealities in the PLL such as non-linear phase to charge conversion
in the PFD and charge-pump, ∆Σ noise at high frequency may fold into frequencies inside
the PLL bandwidth increasing the close in noise of the PLL.
Also, due to the activity of the noise shaper, the average duty cycle of the current pulses
from the charge-pump will increase, creating additional noise.
Since the noise originating from the ∆Σ noise shaper is generated by the operation of a
digital circuit rather from a physical process it will experience different, and sometimes
unexpected, noise properties compared to other noise sources. For example may the noise
spectral distribution change considerably when making only minor adjustment to the di-
vision ratio. In many cases the noise shaper will also experience properties not found
in other noise sources, such as spurious tones due to repeating patterns in the output se-
quence. These phenomena can be verified using behavioral modeling of the noise shaper
[62].
In order to reduce the impact of the ∆Σ modulator, the noise-shaper topology should be
selected to give as small range of division ratio as possible. Noise is also reduced by
ensuring a linear phase to charge conversion in the PFD and charge-pump. When the
variations in division ratio makes the charge-pump produce both up and down current
pulses, a linear phase to charge conversion requires good matching between the up and
down currents.
4.7. LINEAR PLL NOISE MODEL 75

4.7 Linear PLL noise model

When the power spectral density of all PLL building blocks are known, the total PLL
noise can be calculated. Using the small signal PLL model presented in section 3.3 the
transfer function for each noise source to the output can be expressed. While the linear
PLL model is not able to exactly predict the PLL noise, the model is still very useful for
loop-filter design and noise optimization.
Since noise sources are located at different positions in the loop, they will have different
transfer functions to the PLL output. The PLL noise sources can be divided into three
major categories: noise that can be referred to the PFD input, loop-filter noise, and VCO
phase noise.
Noise from the reference oscillator, digital dividers, the phase frequency detector and
the charge-pump can be referred to the PLL input. These noise sources will have the
same noise transfer function as the PLL. If a noise source referred to the input has a
power spectral density Sz ( f ), the resulting output power spectrum Wθ0 of the PLL can be
expressed:

Wθ0 ( f ) = |H( f )|2 · Sz ( f ) (4.31)

where H( f ) is the PLL system transfer function:

KD KVCO F(s)
H(s) = (4.32)
KD KVCO F(s)
s+
N
H(s) is a low pass function where the magnitude is equal to the division ratio N at frequen-
cies within the loop filter bandwidth, and goes to zero outside the bandwidth. Equation
(4.31) can therefore be interpreted as the noise power spectral density will be multiplied
a factor N 2 within the PLL bandwidth, and will be a attenuated at high frequency.
The folded current noise at the charge-pump output can be referred to the PLL input by
weighting the power spectral density of the detector gain. The transfer function can also
be expressed directly:

2πKVCO F(s)
D(s) = (4.33)
KD KVCO F(s)
s+
N
The oscillator noise is referred to the output of the oscillator and has a transfer function:

1
T (s) = (4.34)
KD KVCO F(s)
1+
sN
76 4.8. SIMULATING PLL NOISE USING CIRCUIT SIMULATOR

The PLL output noise power spectrum due to the oscillator is:

WθVCO = |T ( f )|2 · SVCO ( f ) (4.35)

where SVCO is the phase noise spectrum of the VCO. T ( f ) will have a small value for
frequencies within the PLL bandwidth and be approximately one for high frequencies.
This is an important feature of the PLL, since it mean oscillator phase noise at small
frequency offsets will be attenuated by the PLL.
The transfer function of thermal noise from loop filter components depends on the loop-
filter configuration. For a third order loop-filter, the loop-filter noise will have a band-pass
characteristics.
Knowing the noise sources power spectral density and using equation (4.32) to (4.35), the
output power spectrum of the PLL can be calculated.

4.8 Simulating PLL noise using circuit simulator

An efficient way to simulate the combined effect of PLL noise sources is to model phase-
noise using AC simulation in a standard circuit simulator.
Since a circuit simulator is normally only capable of handling voltage and current, the
phase disturbance θ has to be represented using a voltage in the simulation. Phase noise
of PLL blocks can be modeled using noise look-up tables or by using noisy resistors
and diodes. Noise from physical resistors in loop-filter components are modeled by the
simulator.
Fig. 4.11 shows the small signal model of a PLL.

Figure 4.11: PLL modeled using Cadence simulator

4.8. SIMULATING PLL NOISE USING CIRCUIT SIMULATOR 77

In a PLL design project, phase noise is conveniently simulated using separate noise views
of the PLL building blocks. In this way noise can be simulated using the same top-level
schematic as used in other steps of the PLL design, minimizing the risk of schematic
errors.
Another advantage of using small signal simulation is that parasitic components such as
interconnect resistances and capacitance of ESD protection can easily be incorporated
in the simulation. Including these components using analytical methods would require
recalculation of the noise transfer function, which is a non trivial task for complex loop-
filters.
The AC model is equivalent to the linear PLL model described in section 3.3, and can be
used also to estimate lock time and to calculate the bandwidth and phase margin of the
PLL.
The AC-noise simulation will directly calculate the corresponding phase noise spectrum
Wo . In order to estimate the normalized spectrum L the noise spectrum should be divided
by two according to equation (2.9). Since the simulated noise power spectral density is
proportional to the squared
√ voltage, the normalized spectrum can be directly simulated by
dividing the voltage by 2.√In Fig. 4.11 this is achieved by a voltage controlled voltage
source E0 having a gain 1/ 2.

4.8.1 VCO

In the small signal model the VCO can be modeled using a current controlled current
source and a capacitor (Fig. 4.12).

Figure 4.12: VCO noise model

The voltage source V0 at the output of the block is used to represent the phase noise of
the oscillator. In this example the phase noise is extracted from a noise table in a text file
noise_table.txt. Note that in order to correctly calculate the output noise, the table
should contain the phase noise spectrum and not the normalized spectrum.
78 4.8. SIMULATING PLL NOISE USING CIRCUIT SIMULATOR

The transfer function of the schematic in Fig. 4.12 is:

VOut ggain
= (4.36)
VCtrl sC
where ggain is the transconductance of the voltage controlled current source. The AC and
DC voltage of V0 is zero and do not affect the transfer function. Setting the transconduc-
tance ggain = 2πKVCO and the capacitance to 1 gives the transfer function:

VOut 2πKVCO
= (4.37)
VCtrl s
Letting VOut be equivalent to θVCO makes the transfer function of (4.37) equivalent to the
small signal model in equation (3.6).
An alternative way to model the VCO phase-noise is to add the white noise source to the
1/f noise from a diode, as illustrated in Fig. 4.13.

Figure 4.13: VCO noise modelled using noisy diode

Injecting the 1/f + white noise as a current into the integrating capacitor simulates the 20
dB/decade and 30 dB/decade regions of the oscillator phase noise.
The advantage of modeling oscillator noise using a diode is that noise power and flicker
noise corner can be parameterized, which may be useful in initial PLL simulations where
noise tables of simulated VCO noise are not available.

4.8.2 Divider
The frequency divider is simply modeled as a voltage controlled voltage source where the
voltage gain is 1/N (Fig. 4.14). The phase noise of the divider is modeled using a voltage
source at the output in the same way as the phase noise of the VCO.
4.8. SIMULATING PLL NOISE USING CIRCUIT SIMULATOR 79

Figure 4.14: Divider noise model

4.8.3 PFD and Charge Pump

The PFD and Charge-Pump combination is modeled using a voltage controlled current
source, where the transconductance is equal to KD = ICP /2π as illustrated in Fig. 4.15.

Figure 4.15: PFD and Charge pump noise model

Noise from the PFD digital circuits and reset delay is modeled using a noise source at
one of the inputs. The folded charge-pump noise as calculated using equation (4.14) or
(4.19) is included using a noise current in parallel with the charge-pump output. Using
look-up tables, this noise current can also be modeled to include increased charge-pump
noise caused by the operation of the ∆Σ modulator in a fractional-N PLL.

4.8.4 Loop filter

The transfer function of the loop-filter and thermal noise in loop-filter resistors is auto-
matically calculated by the AC-noise simulator.
This is perhaps the biggest advantage using a circuit simulator to simulate PLL noise,
since the influence of complex loop-filters can easily be simulated without the need to
derive closed form transfer functions.
80 4.9. DISCRETE TIME AND NUMERICAL NOISE SIMULATION

4.8.5 Simulating noise using small signal model

Once all PLL blocks are modeled, the AC transfer function and noise of the closed PLL
is simulated using normal AC and noise analysis. Total PLL noise as well as the contribu-
tions from each PLL block can be found as illustrated in Fig. 4.16. The figure shows the
phase noise contributors of the TripleTraC PLL:s presented in paper 4 and 5.

Figure 4.16: Simulated phase noise contributers LO1 TripleTraC WLAN transceiver

If noise sources are carefully modeled the total simulated PLL noise using the AC model
shows good correspondence with measured performance. Fig. 4.17 shows a comparison
between the the total simulated and measured phase noise of the transceiver.
Using the phase-noise simulation the dominating noise source can be located. In Fig.
4.16 it is evident that the reference clock buffer (XCO buffer) is dominating the phase
noise at small and moderate frequency offsets. The noise was located to be flicker noise
in the reference clock input stage. This could be verified in measurements by using an
external reference clock. Since the external clock had faster transitions, noise from the
input buffer was reduced. Fig. 4.18 shows a comparison of measured phase noise using
internal reference oscillator, and external clock. When using an external reference clock,
the close in phase noise is lower.

4.9 Discrete time and numerical noise simulation

A limitation of the small signal noise model is that the sampled nature of the charge-pump
is not taken into account. This makes the noise simulation to be somewhat inaccurate,
4.9. DISCRETE TIME AND NUMERICAL NOISE SIMULATION 81

Figure 4.17: Simulated and measured phase noise TripleTraC WLAN transceiver

Figure 4.18: Measured PLL phase noise using internal and external reference oscillator

especially if the loop-filter bandwidth is wide compared to the PLL reference frequency.
For a more correct noise prediction, phase noise can be simulated using the discrete time
PLL model described in section 3.4, or using numerical methods discussed in section 3.5.
Fig. 4.19 shows a comparison between the linear and discrete time noise transfer function
for phase noise at the reference clock. The PLL is simulated using a loop-filter having a
bandwidth 1/10th of the reference frequency.
For low frequencies the two models agree. For high frequencies the linear model under es-
82 4.10. PLL NOISE OPTIMIZATION

timates the noise. The transfer zeros at harmonics of the PLL reference frequency clearly
visible in the discrete time model are also not present in the linear model.
For most PLL applications where the PLL bandwidth is substantially lower than the ref-
erence frequency the linear PLL model is sufficient for most noise simulations.

70
Linear
Discrete time

60

50
Noise gain [dB]

40

30

20

10

0
1000 10000 100000 1e+06 1e+07
Frequency [Hz]

Figure 4.19: Noise transfer function

Fig. 4.20 shows the output spectra of a fractional-N PLL synthesizer simulated using a
numerical model. The reference spur and noise from VCO and charge-pump are clearly
visible. A drawback with the numerical method is that the different noise contributors can
not be distinguished. Unlike the linear PLL models the numerical method is however able
to simulate noise from the Σ∆ noise shaper.
The results may however be somewhat inaccurate, since the method fails to capture effect
of non-linearities of the charge-pump and phase detector due to static, dynamic and delay
miss-match [20]. These can be major contributors of in-band noise in fractional-N PLL
frequency synthesizers.

4.10 PLL noise optimization

Since noise sources within the PLL is shaped by the loop filter, the phase noise perfor-
mance of the complete PLL can be optimized by tuning the loop-filter parameters.
The sum of the PFD, charge-pump and digital circuits creates a noise-floor within the
PLL bandwidth ω1 that is relatively flat (Fig. 4.21a). Outside the PLL bandwidth the
noise drops.
4.10. PLL NOISE OPTIMIZATION 83

CppSim Simulated Phase Noise for Cell: sd_synth, Lib: Synthesizer_Examples, Sim: test.par

noiseout_filt
−80 −42

−90 −52

−100 −62

−110 −72
L(f) (dBc/Hz)

Spurs (dBc)
−120 −82

−130 −92

−140 −102

−150 −112

−160 −122

0.01 0.1 1 10
Frequency Offset from Carrier (MHz)

Figure 4.20: Phase noise of a fractional-N PLL frequency synthesizer simulated using CppSim

Figure 4.21: Shaping of PLL noise sources

The transfer function of the VCO noise has the opposite behavior. Outside the PLL band-
width the VCO noise transfer function is 1, i.e. the PLL output noise equals the VCO
noise. Inside the bandwidth the VCO noise is suppressed by the PLL, Fig. 4.21b.
The best loop-filter band-width ωopt is approximately where the in-band noise equals the
VCO noise, as illustrated in Fig. 4.22.
If the loop-filter is too narrow, the VCO noise will not be suppressed by the PLL, making
the in-band noise higher than necessary. Accordingly, a too wide loop filter will not filter
out noise from the charge-pump etc, increasing the phase noise at large frequency offsets.
At the PLL bandwidth ω1 the noise will experience an overshoot due to the finite phase
margin of the PLL feedback (Fig. 4.21a). This overshoot will increase the noise around
84 4.10. PLL NOISE OPTIMIZATION

Figure 4.22: Optimum PLL bandwidth

ω1 for both the VCO and other noise sources. In applications where the PLL noise is
required to be below a certain limit at an offset close to ωopt it may be desirable to select a
somewhat lower PLL bandwidth than ωopt . This result in increased in-band noise, but the
noise at ωopt will not experience overshoot. By using a lower bandwidth the PLL noise
can also be lower since the phase noise is dominated by the VCO only, instead of being
the sum of the VCO and other noise sources. The hight of the overshoot can be reduced
by increasing the phase margin.

4.10.1 Lorentzian approximation of integrated phase noise

In OFDM applications the total integrated noise is important.

If the phase-noise is assumed to be flat having a normalized phase noise L up to the loop-
filter band-width ω1 , and fall 20 dB/decade for higher frequency offsets, the Phase-Noise
can be approximated using a Lorentzian function:

Lo ω21
L (∆ω) = (4.38)
∆ω2 + ω21

The Laurentian function is used to simulate phase noise in many system level simulators.
Integrating (4.38) between two frequencies ωa and ωb gives the integrated noise:

Z ωb
ωb ωa
Lint = L ( f ) dω = L0 ω1 (arctan( ) − arctan( )) (4.39)
ωa ω1 ω1

Equation (4.39) is useful when exploring the trade-off between VCO noise and other noise
sources to meet a specified integrated phase-noise requirement. By rearranging equation
(4.39) and keeping Lint constant, the required in-band noise can be calculated as a function
of the PLL bandwidth. In combination with equation (4.38) the VCO-noise at specified
offset can be calculated.
4.10. PLL NOISE OPTIMIZATION 85

Equation (4.39) will slightly underestimate the integrated noise since the overshoot around
the loop-filter bandwidth is not taken into account.

-75
VCO phase noise @ 1 MHz
Close in noise-floor

-80

-85

-90
Phase noise [dBc/Hz]

-95

-100

-105

-110

-115
10000 100000 1e+06
PLL bandwidth [Hz]

Figure 4.23: Required close in and VCO noise in order to acheive -36 dBc integrated phase noise

Fig. 4.23 shows the required close in and VCO phase noise in order to achieve a total
integrated noise of -36 dBc. The plots can be interpreted as if the close in noise is -95
dBc/Hz, the optimum bandwidth is 100 kHz, and the allowed VCO phase noise (of the
free-running oscillator) at 1 MHz offset is -110 dBc/Hz.
This kind of calculations are useful in initial specification of the PLL since the power
consumption can be reduced significantly if the VCO phase noise requirement is relaxed.

4.10.2 Optimizing of integrated phase-noise

The loop-filter bandwidth, but also the phase margin and the relation between the pole
and zero in the loop-filter affects the integrated noise performance. Thanks to the quick
simulation time of the small signal PLL model, the simulation can be used to find the
optimum loop-filter bandwidth and phase margin.
Fig. 4.24 shows a simulation of the integrated phase-noise for an example PLL where the
close in phase-noise is -94 dBc/Hz, and the VCO noise at 1 MHz offset is -120 dBc/Hz.
The VCO noise drops 20 dB/decade, giving an optimal PLL bandwidth where the VCO
noise equals the close in noise of approximately 50 kHz.
The integrated phase noise is plotted versus the PLL bandwidth for three different PLL
phase margins. A clear minimum is visible for loop-filter bandwidth between 50 and 60
kHz.
86 4.10. PLL NOISE OPTIMIZATION

-38.5
PM 45
PM 75
PM 80
-39

-39.5
Integrated noise [dBc]

-40

-40.5

-41

-41.5

-42
30000 40000 50000 60000 70000 80000 90000 100000
Bandwidth [Hz]

Figure 4.24: Integrated noise vs BW using three different phase margins

Fig. 4.24 also shows that the integrated phase noise drops when increasing the phase
margin. This is due to the reduced overshoot. Fig. 4.25 shows the total PLL phase-noise
vs frequency offset for PLL:s having different phase margins. When increasing the phase
margin the overshoot is less pronounced, but noise at both small and large frequency
offsets increase.
The optimal phase margin depends on the slope of the VCO. Since the loop-filter band-
width is often relatively small, the slope of the VCO noise may be 30 dB/decade rather
than 20 dB/decade at the offset of the loop-filter bandwidth.
Fig. 4.26 shows the integrated noise vs phase margin for two PLL:s where the VCO noise
drops 20 dB/decade and 30 dB/decade. When the noise drops 20 dB/decade the phase
margin should be selected as high as possible. When the VCO noise drops 30 dB/decade
the minimum integrated phase noise is achieved for a phase margin of 75◦ .
Due to physical limitations of loop-filter components, phase margins above 70◦ may often
be impractical to realize.
4.10. PLL NOISE OPTIMIZATION 87

-85
PM 45
PM 60
PM 80
-90

-95
Noise [dBc/Hz]

-100

-105

-110

-115

-120
100 1000 10000 100000 1e+06
Frequency [Hz]

Figure 4.25: PLL output noise

-38
20 dB/decade
30 dB/decade

-38.5

-39

-39.5
Phase noise [dBc]

-40

-40.5

-41

-41.5

-42
30 40 50 60 70 80 90
PM [deg]

Figure 4.26: Integrated noise vs PM

88 4.10. PLL NOISE OPTIMIZATION
Chapter 5

Oscillators

The oscillator is one of the most challenging blocks to design in a PLL. While oscilla-
tors may have a very simple topology, the strongly non-linear operation makes intuitive
understanding difficult and oscillator analysis is not straight forward.
The oscillator is usually dominating PLL phase noise at large frequency offsets. In order
to meet system requirements it is necessary to design oscillators having sufficiently low
phase noise. Preferably noise should be reduced without increasing power consumption
or using expensive external components. This is difficult in fully implemented solutions,
and requires careful optimization of resonator losses and device sizes. b Accordingly,
design and implementation of fully integrated oscillators have received immense atten-
tion from the research community during recent years. Uncountable number of oscillator
implementations have been reported.
In this chapter, different oscillator topologies are reviewed. The CMOS-LC oscillator
receives special attention, since this is the most widely used topology in highly integrated
radio circuits. The noise mechanisms of the CMOS-LC oscillator are explained, and
methods to optimize phase noise are reviewed.
In section 5.3 a novel oscillator topology giving improved phase noise performance is
presented.

5.1 Oscillator principles

The purpose of an oscillator is to generate a periodic output signal without using an input
signal. This can be achieved using several principally different methods, where the os-
cillator topology is selected based on requirements on operation frequency, tuning range,
chip area and spectral purity.

89
90 5.1. OSCILLATOR PRINCIPLES

In PLL applications the frequency of the oscillator must be controllable. While the oscilla-
tor frequency is normally set by a tuning voltage, a so called Voltage Controlled Oscillator
(VCO) frequency can also be controlled using a current [78] (Current Controlled Oscil-
lator, ICO) or by digital programmable elements [79] (Digitally Controlled Oscillator,
DCO).
In reality, fully integrated oscillators often use a combination of voltage and digital meth-
ods to control the frequency to allow digital calibration.

5.1.1 Delay element oscillators

Delay based oscillators are based on one or more delay elements in a feedback configu-
ration. Typical delay based oscillators are ring-oscillators and the relaxation oscillators.
Fig. 5.1 shows the schematic of a three stage inverter ring oscillator.

Figure 5.1: Ring oscillator

The oscillation frequency f0 of the oscillator can be calculated:

1
f0 = (5.1)
3(T1 + T2 )

where T1 is the delay of the rising edge and T2 is the delay of the falling edge. By changing
the delay times, for example by modifying the supply voltage or bias current in a current
starved inverter, the frequency can be varied.
5.1. OSCILLATOR PRINCIPLES 91

Delay based oscillators typically have poor phase-noise performance compared to res-
onator based oscillators [80], [81], [82]. However, since delay based oscillators don’t rely
on an inductor to operate, they can be implemented using small chip area. Another advan-
tage is the often high tuning-range, often several decades [83]. Ring oscillators are often
preferred in application where the circuit area must be small, but where spectral purity is
not critical. Ring oscillators are not common in high performance radio applications, but
may be feasible in applications such as UWB transceivers [84].

5.1.2 Phase shifting oscillators

A feedback system becomes unstable when the phase shift around the loop is 360◦ and
the gain is equal to one. The oscillation is summarized in the Barkhausen’s criteria for
oscillation:

Gain = 1 at ω0 (5.2)

Phase = n · 360◦ at ω0 (5.3)

where n is an integer.
Fig. 5.2 shows the schematic of an example phase shift oscillator.

Figure 5.2: Phase shift oscillator

If used in conjunction with an amplitude control mechanism, phase shift oscillators are
capable of generating a sine wave having low distortion over a wide tuning range. The
oscillator topology has historically been used in measurement equipment, notably the
92 5.2. CMOS LC-VCO

HP 200A [85], the first product of Hewlet Packard. HP 200A is a precision sine wave
oscillator based on a Wien bridge oscillator.
Phase shift oscillators are rarely used in modern applications, but are commonly found as
unwanted oscillations in amplification stages.

5.1.3 Resonator based oscillators

Resonator based oscillators are the most common topology in radio applications. In res-
onator based oscillators, the oscillation frequency is determined by a resonance circuit,
for example an inductor capacitor combination (LC oscillator) or a mechanical resonator
(Chrystal oscillator). An amplifier compensates for loss in the resonance circuit and keeps
a sustained oscillator. Example of resonator based oscillators are differential LC oscilla-
tors and Colpitts oscillators. LC oscillators will be discussed in detail in chapter 5.2 and
5.3.

5.2 CMOS LC-VCO

Due to the differential structure and relatively good phase noise performance, the differ-
ential LC oscillator, see Fig. 5.3, is one of the most popular oscillator configurations in
fully integrated RF CMOS applications.

Figure 5.3: Differential CMOS LC oscillator

5.2. CMOS LC-VCO 93

The convention to call the topology "LC-VCO" is a little unfortunate, since a large number
of VCO topologies, for example single ended and differential Colpitts oscillators, use
Voltage control and LC resonators. Since "LC-VCO" is commonly used in literature to
indicates a current biased differential LC oscillator using cross coupled CMOS transistors,
the name is used throughout this thesis.
The topology has been investigated thoroughly in a large number of publications.
The feasibility of fully integrated CMOS oscillators achieving high spectral purity was
demonstrated in [86]. The importance of inductors was realized early, and methods to
improve inductor Q-value using bond-wire inductors [87], enhanced hollow inductors
[88] and using back-etching to reduce substrate loss [7] have been proposed. The impact
of different varactor types is investigated in [89] and [90].
The contribution from bias noise was recognized in [91], and the high frequency bias noise
has been observed to be a dominant contributor to oscillator phase noise [92]. Methods to
reduce bias noise using tail noise filtering [93][94][95] and by removing the bias current
generator have been suggested [96].
The impact of device type and sizing is investigated in [97][21] and [22]. Due to the
lower flicker noise PMOS devices are often preferred [98]. PMOS devices may also
be selected since they often resides in separate wells and are therefore less sensitive to
substrate interference [99].
The use of single ended and differential inductors are investigated in [100]. The advan-
tages and disadvantages using single ended and differential varactors is discussed in [101].
Using differential varactors can give significant rejection of common mode interferers on
the oscillator control node [102].
Despite the popularity, it was not until quite recently the operation and noise mechanisms
of the configuration was fully understood. While early publications [88] use empirical
equations for the oscillator phase noise, it was not until the arrival of the ISF theory
[17] the tools for doing an analytical treatment of the oscillator phase noise was possible.
Recent publications using the ISF theory to give insights to phase noise mechanisms and
analytical expressions for phase noise in CMOS-LC oscillators [103][104].
In this chapter, design considerations in integrated CMOS oscillators are reviewed.

5.2.1 Principle of operation

The LC-VCO contain two major parts: The passive LC tank determining the oscillation
frequency, and the active devices that compensate the loss in the tank (Fig. 5.3). Most
practical oscillator implementations also include bias circuitry and a buffer amplifier.
The LC tank contains an inductor (L) and capacitor (C), where the oscillation will oscillate
at the frequency where the reactance of the inductor cancels the reactance of the capacitor.
The oscillation frequency can be calculated using the familiar equation:
94 5.2. CMOS LC-VCO

1
f0 = √ (5.4)
2π LC

In order to be able to vary the oscillation frequency the capacitor is often implemented us-
ing a voltage controlled capacitor (varactor) or an array of digitally controllable capacitors
[105], or a combination thereof [79].
An alternative way to adjust the frequency is to switch the inductor [106], or by using
MEMS to tune the inductance value [107]. Using these methods, wide tuning range can
be achieved at the expense of increased area or complicated processing steps.
A third way tune the oscillation frequency is to change the bias current. This method has
the drawback that the oscillation amplitude and the phase-noise performance is a strong
function of the bias current.

5.2.2 Start criteria

The start condition of the oscillator can be investigated using small signal analysis. Fig.
5.4a shows a simplified small signal model of the resonance circuit and corresponding
losses.

Figure 5.4: VCO tank model and equivalent circuit

5.2. CMOS LC-VCO 95

At the resonance frequency the reactive components cancel and the tank becomes purely
resistive. The equivalent resistance can then be divided into two parts, the loss part, rep-
resented by an equivalent parallel resistor Rp, and the negative resistance provided by the
active devices, Fig. 5.4b. The oscillator will start as long as the active circuit provides
enough gain to overcome the losses in the tank i.e. when the magnitude of the negative
resistance is smaller than the magnitude of Rp. The total resistance will then be negative.
To guarantee a proper oscillation there must be a certain margin for process variations and
model errors. This is called the start margin and describes the quota between the losses
in the passive component in the resonance circuit, and the negative resistance provided
by the active devices. For the CMOS-LC oscillator the negative resistance of the active
devices is:

2
Ractive = − (5.5)
gm

where gm is the transconductance of the transistors. In the start margin calculations it is

assumed the transconductance of M1 and M2 are equal. Knowing gm the start margin can
be calculated:

Rp R p · gm
Start margin = − = (5.6)
Ractive 2

The oscillator will start if the start-margin is equal or greater than one. Typical values for
real oscillator implementations is a start margin between 1.5 and 2.
Simulation of start margin using AC simulation
The start margin can be simulated using AC simulation, but in order to accurately sim-
ulate gm and resonance frequency, the circuit must be correctly bias and loaded. Since
the capacitance of the active devices will affect the oscillation frequency, they must be
included in the tank circuit. In high frequency oscillators the active devices accounts for a
large portion of the tank capacitance, and the difference between the loaded and unloaded
resonance frequency can be large.
A practical method to simulate the start margin is to insert an AC current source across
the tank according to Fig. 5.5a, and calculate the voltage and currents into the tank and
the active devices
At the resonance frequency the voltage Vtank will be purely real. The equivalent series
resistance (Fig. 5.5b) can be found taking the real part of the impedance:
 
Vtank
Rs = ℜ (5.7)
Itank

The corresponding parallel equivalent circuit (Fig. 5.5c) is calculated:

96 5.2. CMOS LC-VCO

Figure 5.5: Testbench to simulate start magin

R2s + Xs2
Rp = (5.8)
Rs

where Xs is the imaginary part of the impedance:

 
Vtank
Xs = ℑ (5.9)
Itank

The equivalent impedance of the active circuit is calculated using the same method.
Fig. 5.6 shows simulated impedances in a resonance circuit. The circuit will oscillate at
the frequency when the imaginary part of the voltage across the oscillator is zero.
Note that the resonance frequency of the LC tank alone (where the real part of the tank
impedance peaks) is somewhat higher than the resonance frequency of the complete os-
cillator. This is due to the capacitive loading of the active devices somewhat lowers the
resonance frequency of the oscillator.
Unwanted oscillations
5.2. CMOS LC-VCO 97

400
Vtank imaginary part
LC tank Rs
LC tank equivalent Rp
Oscillation frequency
300 Active circuit equivalent negative resistance

200
Impedance [Ohm]

100

-100

-200
1e+09 1.5e+09 2e+09 2.5e+09 3e+09
Frequency [Hz]

Figure 5.6: Oscillator impedance

When including parasitic components such as interconnect inductance and capacitance,

the oscillator may have several oscillation modes. Usually only one of the frequencies is
desired, and the start margin for higher oscillation modes should be low to avoid unwanted
oscillations.
Simulation of start margin using stability probe
Some circuit simulators, for example SpectreT M , can directly perform stability analysis
simulation. This simulation is a convenient way to to directly simulate the start margin of
an oscillator. The stability probe is usually only able to simulate the stability for one os-
cillation mode, and may therefore not be able to find stability problems for high frequency
parasitic oscillations.

5.2.3 Steady state amplitude

As the amplitude in the oscillator increase, the circuit can no longer be analyzed using
small signal approximations.
Fig. 5.7 shows the start transient of a typical oscillator. In a real circuit the oscillation
starts due to noise or an interferer coupling into the oscillator. In simulations the oscillator
may not always start unless an interference such as a current pulse or a damped sinusoidal
current is injected.
When the oscillation reach steady state, the transistors will act as commutating switches,
steering the bias current into the resonance circuit. Fig. 5.8 shows the drain current of
98 5.2. CMOS LC-VCO

2.3
vco_start_transient
2.2

2.1

1.9
Drain voltage [V]

1.8

1.7

1.6

1.5

1.4

1.3

1.2
0 5e-09 1e-08 1.5e-08 2e-08
Time [s]

Figure 5.7: VCO start transient

M1 and M2. The bias current is switched between M1 and M2, generating a waveform
approaching a square-wave.

Id M1
Id M2
8 Ibias

6
Drain current [mA]

1.8e-08 1.85e-08 1.9e-08 1.95e-08 2e-08

Time [s]

Figure 5.8: VCO drain currents

Current limited oscillation

5.2. CMOS LC-VCO 99

If the Q-value of the resonance circuit is reasonably high, it can be assumed the voltage
across the resonance circuit is sinusoidal. The differential peak amplitude A0 across the
oscillator can then be calculated by calculating the fundamental tone I0 f und of the current
into the resonance circuit:

A0 = I0 f und · R p (5.10)

If the current in the drains is a square-wave the amplitude can be calculated using the
fundamental Fourier component of a square wave:

4Ibias
A0 = · Rp (5.11)
π
Equation (5.11) can be used to approximate the oscillation amplitude in a current limited
oscillator.
Another way to view the amplitude limitation is to study the equivalent input impedance
into the active circuit, see Fig. 5.9. For small amplitudes the negative resistance can be
calculated using small signal AC simulation. When the amplitude increase the equivalent
negative resistance will decrease until it becomes equal to the loss in the tank circuit. This
will be the oscillation amplitude.

700
Active circuit negative resistance
Active circuit negative resistance AC simulation
Tank parallel resistance
600

500 Oscillation amplitude

Neg res (Ohm)

400

300

200

100

0
0 0.5 1 1.5 2 2.5
Ampl (Vp diff)

Figure 5.9: Negative resistance vs Amplitude

Voltage limited oscillation

The oscillation amplitude will grow linearly with the increasing bias as long as M1, M2
and the bias circuit operates in saturation. When the amplitude grows, the swing at the
100 5.2. CMOS LC-VCO

drains of M1 and M2 cause the transistors to go into the triode region, limiting the effective
output current. It is usually not desirable to operate the oscillator in this condition, since
the current consumption is high and without improving the oscillator performance.
The voltage swing may also be limited by the break down voltage of the devices. If the
inductors in the resonance circuit is connected to Vdd, as indicated in Fig. 5.3 the drain
nodes will swing to voltages above Vdd, potentially damaging the devices.
Loss in parasitic components
When calculating the oscillation amplitude it is important to take voltage dependency and
loss in parasitic components into account. Loss in non-linear components such as the
varactor or a switched capacitor bank make the tank loss vary.
Fig. 5.10 shows the simulated oscillation amplitude for different varactor voltages before
and after parasitic-R extraction. The simulation shows that the parasitic resistance in
interconnect wires lowers the amplitude significantly, but also that the varactor voltage
influence the amplitude. The start margin should be simulated in the worst corner where
the amplitude is smallest.

0.8
No parasitic extraction
Parasitic R extracted

0.7

0.6
Amplitude [Vp]

0.5

0.4

0.3

0.2
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Vtune [V]

Figure 5.10: Comparison simulated amplitude with and without parasitic R extraction
5.2. CMOS LC-VCO 101

5.2.4 Phase noise

In this section the phase noise mechanisms of the CMOS-LC oscillator is described. The
discussion use the Impulse Sensitivity Function, Γ, to quantitative describe how the oscil-
lator waveforms and operation affects the noise impact [17]. Equations approximating the
noise and impact of device sizing is calculated using using long-channel device model,
basically following the methods in [104].
The method for calculating the phase noise is to represent all oscillator noise sources with
an equivalent time varying noise current into the resonator. The time varying noise is
represented using a white noise source in0 and a noise modulation function α.

in (t) = in0 (t)α(ω0t) (5.12)

In the following discussion it is assumed the Q-value of the resonator is high enough for
the oscillator voltage to be a sinusoidal. For a sinusoidal oscillator voltage, the Impulse
Sensitivity Function is a cosine Γtank (ϕ) = cos(ϕ). Knowing the noise modulation func-
tion α the effective ISF can be calculated:

Γe f f (ϕ) = α(ϕ) · cos(ϕ) (5.13)

Studying α and Γe f f gives insight of when different blocks in the oscillator generate noise,
and how this impact the phase-noise.
Knowing Γe f f the 1/ f 2 part of the phase noise can be calculated:

Γ2e f f ,rms
!
i¯2n
L (∆ω) = 10 · log · 2 (5.14)
∆ f 2qmax ∆ω2

where i¯2n /∆ f is the power spectral density of a noise source, Γe f f ,rms is the root mean
square value of the effective ISF associated to the noise source in . ∆ω is the offset fre-
quency from ω0 . qmax is the maximum charge swing of the tank capacitance, i.e. the
charge stored in the capacitor at the peak voltage. qmax = A0Ctot , where Ctot is the total
capacitance in the resonance circuit.
The LC-VCO have three major noise contributors:

1. Thermal noise from tank resistance.

2. Active circuit noise.
3. Bias noise.

The thermal tank noise is a white time invariant noise source, and the phase noise contri-
bution from this noise can be calculated directly using equation (5.14).
The noise from the active devices and the bias is time varying, and in order to understand
the contribution from these noise sources the noise transfer functions must be calculated.
102 5.2. CMOS LC-VCO

5.2.5 Transfer functions of noise sources

When the LC-Oscillator is operating in the current limited region and has reached steady
state amplitude, the operation of the MOS active devices can be divided into three distinct
regions.

Figure 5.11: Voltage and drain currents in LC-VCO

Fig. 5.11 shows the voltage and drain currents in a LC VCO.

In the first region (1 in Fig. 5.11) only transistor M1 is conducting and M2 is switched off.
In this region transistor M1 will operate as a cascode divice, and the bias current will be
delivered directly to the tank.

In the second region (2 in Fig. 5.11), both M1 and M2 are conducting. In this region the
active devices will operate as a differential pair, steering the bias current into the tank. At
the equilibrium point (A in Fig. 5.11) the current in M1 and M2 will be equal, and the
differential current into the tank is zero.

The third region (3 in Fig. 5.11) is equivalent to region 1, but only M2 is conducting
instead of M1 .
5.2. CMOS LC-VCO 103

5.2.6 Bias noise

The tail noise can be assumed to be constant, but in the same way as the bias current
will be steered by the active devices, the noise from the bias circuit will depend on the
operation of M1 and M2 .

Figure 5.12: Bias noise transfer function and ISF

Fig. 5.12 shows the oscillator waveform and the noise modulation function of the bias
noise. When M1 or M2 is fully conducting, the bias noise pass directly into the tank and
create a differential noise current. In this case the noise modulation function is -1 or 1
depending which device is conducting (Fig. 5.12b).

In the region where both M1 and M2 are conducting, the noise current into the tank will
be partly common-mode, partly differential. At the point where the drain currents in M1
and M2 are equal (A in Fig. 5.12) there will be no differential bias noise, and the noise
modulation function will be zero.
104 5.2. CMOS LC-VCO

Multiplying the noise modulation function with the tank ISF gives the effective ISF (Fig.
5.12c). Due to the rectifying operation of the active devices, the effective ISF will become
a periodic waveform having half the period of the oscillator. Since the ISF have half
the period, it will have no frequency component at the fundamental tone. Instead, the
oscillator is most sensitive for bias noise at the second harmonic of the oscillator. For this
reason, several bias noise filter approaches use a notch at twice the oscillator frequency to
filter out the bias noise [93].
In a perfectly matched oscillator the average value of the effective ISF is zero, meaning
no low-frequency noise is up-converted and affecting the VCO. In real oscillator imple-
mentations however, a common mode interferer will not be perfectly attenuated, and low
frequency noise will still be up-converted to some extent.
The 1/ f 2 part of the phase noise depends on the RMS value of the Γe f f . By making the
active devices smaller (dotted line in Fig. 5.12c), the time ∆t is increased. This effectively
lowers Γe f f , decreasing the phase noise. From a bias point of view, the size of M1 and M2
should be as small as possible, in order to reduce the effective ISF.

5.2.7 Noise from active devices

The noise of the active devices are proportional to the transconductance of the differen-
tial pair formed by M1 and M2 . In the region where only one device is conducting, the
transconductance is zero, and the active devices do not contribute to the noise.
In the region where both devices are conducting, the noise depends on the tank voltage.
Fig. 5.13b shows a plot of the noise modulation function of the active devices. The noise
peeks when the tank voltage is zero.
Multiplying the noise modulation function with the tank ISF gives the effective ISF (Fig.
5.13c). Ideally also this ISF have an average of zero.
When increasing the size of M1 and M2 the transconductance increase but at the same
time the conduction time ∆t decrease. The two effects cancel and the RMS value of the
ISF remain approximately constant when changing the device size (Fig. 5.13c).

5.2.8 Phase noise optimization of LC-VCO

In order to minimize the phase noise of the oscillator, the following major strategies can
be used.
Improve Q value of resonator circuit
Improving the Q-value of the circuit is the best way to improve phase noise, since it also
gives reduced power consumption.
To find the distribution of loss and capacitance, it is often useful to calculate the equivalent
impedance of the resonance circuit building blocks (Fig. 5.4a).
5.2. CMOS LC-VCO 105

Figure 5.13: Active circuits noise and ISF

The inductor often dominates the loss, and careful layout of the inductor geometry is
important to give good phase noise performance [88]. It is often necessary to custom-
design the inductor for best performance in the oscillator. Accurate calculation of passive
devices can be performed using software tools like Asitic [108].
Parasitic components in interconnects can often contribute substantially to loss in the
resonance circuit, and careful post layout extraction and simulation is necessary to predict
oscillator performance.
Reduce bias noise
To reduce the contribution from the bias, the current mirror devices in the bias circuit must
be properly sized. To reduce 1/ f noise the bias circuit often have a large area. Methods
to further reduce bias noise involve tail noise filtering techniques [94][95], or the use of
a noise filter to reduce the impact of noise from the current mirror transistor [109]. It has
also been suggested to bias the current mirrors in the triode region [99].
106 5.2. CMOS LC-VCO

Optimize device sizes

Based on the discussion in section 5.2.7 the ISF of the active devices is constant, implying
a constant phase noise contribution. However, increasing the device size reduce the con-
duction angle ∆t which makes the current into the tank more square like. This increases
the oscillation amplitude giving improved phase noise.
Based on the discussion in section 5.2.6 and 5.2.7 the width of the active devices should
therefore be minimized if the bias noise is dominating, and should be maximized when
the bias noise is non dominant [104].
Increase power
By increasing the bias current, the amplitude increase and the phase noise is reduced at
the expense of increased power consumption.
If the amplitude is increases too much, the oscillator devices enters the triode region, giv-
ing voltage limited amplitude operation. Fig. 5.14 shows the oscillation amplitude when
sweeping the bias current. For small currents the amplitude is accurately approximated
using equation (5.11), but as the bias current increase the amplitude increase more slowly,
finally approaching the voltage limited regime.

4.5
vco_ampl_vs_ibias
vco_ampl_vlim_vs_ibias
vco_ampl_ac_vs_ibias
4

3.5

3
Amplitude [Vpdiff]

2.5

1.5

0.5
5 10 15 20 25
Ibias [mA]

Figure 5.14: Amplitude vs Ibias

In the voltage limited region the phase noise performance does no longer increase, or may
even degrade when the bias current is increased. Fig. 5.15 shows the simulated phase
noise at 1 MHz offset when the bias current is swept. For currents below 19 mA, phase
noise improve when the current is increased. Above 20 mA the phase noise increase,
5.3. PULSE WAVE LC OSCILLATOR 107

-125
PN 1M

-126

-127
Phase noise [dBc/Hz]

-128

-129

-130

-131

-132
5 10 15 20 25
Ibias [mA]

Figure 5.15: Phase noise vs Ibias

giving a waste of power. The optimal bias current corresponds to the region where the
oscillator is entering voltage limited operation (Fig. 5.14).
The maximum charge qmax stored in the resonance circuit is proportional to the amplitude
and the total capacitance. If the amplitude cannot be increased without entering the volt-
age limited region, the phase noise can still be reduced by increasing the capacitance, and
correspondingly reducing the inductance to keep the oscillation frequency constant. By
reducing the inductance the allowed maximum bias current is increased, and better phase
noise performance can be achieved.

5.3 Pulse wave LC oscillator

In this chapter a new oscillator topology giving improved phase noise performance is
presented.
In the proposed topology, bias noise is decoupled and effectively filtered out. Active
devices operate in class-C and in a similar way as in a Colpitts oscillator, the drain currents
peak when the oscillator is insensitive to perturbations. For the same power consumption
the pulsed current gives higher oscillation amplitude, and therefore improved phase noise
compared to a traditional oscillator.
An amplitude control circuit is used to allow large oscillation amplitude, and ensure proper
start margin.
108 5.3. PULSE WAVE LC OSCILLATOR

The topology was first proposed in [110] and a theoretical treatment of the oscillator phase
noise performance is derived and published in paper 9.

5.3.1 Operation principle

Fig. 5.16 shows a principle schematic of the proposed oscillator topology. While schemat-
ically similar to a traditional LC-VCO, the operation principle differs substantially.

Figure 5.16: Circuit diagram Pulse Wave VCO

The additional bypass capacitor Cbypass keeps the voltage Vtail at the source of M1 and M2
constant. The capacitors Cbias are large compared to the gate capacitances and AC-couples
the tank voltage to the gates.
When the oscillator operates the voltage follows a sinusoidal waveform, and since the
transistors conduct current only when the gate-source voltage is higher than the threshold
voltage vth , the drain current will be pulse shaped as illustrated in Fig. 5.17.
Fig. 5.18 shows the simulated gate and source voltage of M1 when the oscillator starts.
For clarity the Vs +Vth is also plotted. When the amplitude is small, the gate voltage equals
the bias voltage Vbias (Fig. 5.18a). The gate-source voltage is above Vth and M1 and M2
will conduct half the bias current each.
As the amplitude increases, the gate-source voltage will swing high above Vth , and the
peak drain current may be substantially higher than the bias current. The drain current
will charge the bypass capacitor, raising the source voltage (Fig. 5.18b) until the average
5.3. PULSE WAVE LC OSCILLATOR 109

Figure 5.17: Gate-source voltage and drain current in pulsed VCO

2.5
Vg
Vtail
Vtail+Vth

1.5
a
Voltage [V]

0.5 b

-0.5
0 1e-09 2e-09 3e-09 4e-09 5e-09 6e-09 7e-09 8e-09
Time [s]

Figure 5.18: Pulse wave VCO start

drain current equals half the bias current Ibias . The average gate-source voltage is now
below the threshold voltage, and the transistors operate in class-C.
For the same average current, a pulsed shaped waveform gives a higher oscillation ampli-
110 5.3. PULSE WAVE LC OSCILLATOR

tude, and therefore lower phase noise compared to the square wave current in a traditional
oscillator [111][112]. Similar to the operation of a Colpitts oscillator, the drain current
peaks when the voltage across the LC tank is maximum. According to the Impulse Sensi-
tivity Function (ISF) theory [17] the oscillator is then least sensitive to perturbations, and
the pulsed current gives minimum impact on oscillator phase noise.
In addition to shape the currents, the bypass capacitor (Cbypass in Fig. 5.16) decouples
bias noise and suppress variations on the voltage supply.
Allowing a large capacitance at the bias output also gives design freedom to size bias
devices for best noise performance. Unlike a traditional oscillator where the capacitance
at the bias should be low in order to ensure proper operation of the current sources [93],
the capacitance of the bias transistors are absorbed in the bypass capacitor in the proposed
architecture. This allows the use of large area bias devices, giving reduced 1/ f noise.

5.3.2 Bias circuit

In order to allow a large oscillation amplitude, and hence low phase noise, the bias devices
Rbias and Cbias are introduced.
Without bias devices the gate and drain will swing around Vdd , as illustrated in Fig. 5.19a.
Since the transistors will conduct a large current when the gate-source voltage is higher
than Vth , the tail capacitor will be charged and the source voltage Vs rise to a value higher
than Vdd − Vth . This limits the swing at the drain to a value less than Vth since a larger
amplitude would cause the transistors to enter the triode region, as illustrated at point A
in Fig. 5.19a.
This phenomenon has been observed in [113] and [114], where a large tail capacitance is
found to give good phase- noise performance, but only for small oscillation amplitudes.
By introducing a bias network the average gate voltage can be lowered as illustrated in Fig.
5.19b. The bias network AC couples the tank voltage to the gates of the active devices.
The bias capacitors are selected to be larger than the gate capacitances and the the resistors
to be larger than the equivalent tank resistance in order to not affect the Q-value of the
resonance circuit.
In Fig. 5.19b the bias voltage Vbias is 0V, but the voltage swing still allows the gate-source
voltage to rise above Vth to give correct average drain current. The lower gate voltage
gives a lower source voltage, allowing the tank swing to increase without the transistors
entering the triode region (B Fig. 5.19b).

5.3.3 Amplitude control

Since the bias voltage giving the best phase noise performance is low, potentially lower
than the threshold voltage of M1 and M2 , the oscillator may not get enough bias current to
5.3. PULSE WAVE LC OSCILLATOR 111

Figure 5.19: Comparison traditional and AC coupled bias

Figure 5.20: Amplitude control circuit

start. To overcome this problem an amplitude control circuit is used as illustrated in Fig.
5.20.
The control circuit use an amplitude detector A-det and a comparator to detect if the oscil-
lation amplitude is above a certain amplitude determined by Vre f . Using this arrangement
two different bias voltages are used, one high voltage Vstart ensuring proper start margin
of the oscillator, and one lower voltage Voperate giving good phase noise performance.
A low pass filter is used to avoid fast transients in the bias voltage, potentially causing the
oscillator to stop. The time constant of the bias filter should be in the same range as the
time constant of current bias node Vtail , allowing the tail voltage to adjust and keeping the
bias current constant. The low pass filter also filters out potential noise from the reference
voltages and switch.
Fig. 5.21 shows a transient simulation of Vd and Vs using amplitude control circuit. The
bias voltage is switched from Vstart to Voperate at t = 20ns.
112 5.3. PULSE WAVE LC OSCILLATOR

Fig. 5.22 shows the zoomed in drain current at t = 10ns, where the bias voltage Vstart
is used. At this point, the minimum drain source voltage becomes very low, and the
transistors enter the triode region, causing dips in the drain current.
A t = 90ns the bias voltage is Voperate . At this time the source voltage is lower, giving
more margin at the drain so the transistors always operates in saturation. This gives the
desired pulse shaped drain currents (Fig. 5.23).
In principle it would be possible to realize the oscillator using only the bias voltage, omit-
ting the current source and connecting the source of M1 and M2 directly to ground. This
would allow a slightly higher oscillation amplitude, since there is no voltage drop across
the current source. However, using this arrangement the circuit would be very sensitive
to variations in the bias voltage, making it difficult to get correct operation amplitude
in practical circuit implementations. Also, without the bias circuit, noise in the voltage
supply is no longer suppressed.

3.5
Vd
Vs

2.5

2
Voltage [V]

1.5

0.5

0
0 1e-08 2e-08 3e-08 4e-08 5e-08 6e-08 7e-08 8e-08 9e-08 1e-07
Time [s]

Figure 5.21: Pulse wave bias control

5.3. PULSE WAVE LC OSCILLATOR 113

0.025
Id1
Id2

0.02

0.015
Current [A]

0.01

0.005

-0.005
1e-08 1.01e-08 1.02e-08 1.03e-08 1.04e-08 1.05e-08 1.06e-08 1.07e-08 1.08e-08 1.09e-08 1.1e-08
Time [s]

Figure 5.22: Drain currents bias Vstart

0.025
Id1
Id2

0.02

0.015
Current [A]

0.01

0.005

-0.005
9e-08 9.01e-08 9.02e-08 9.03e-08 9.04e-08 9.05e-08 9.06e-08 9.07e-08 9.08e-08 9.09e-08 9.1e-08
Time [s]

Figure 5.23: Drain currents bias Voperate

114 5.3. PULSE WAVE LC OSCILLATOR

5.3.4 Calculation of 1/ f 2 phase noise

In this section equations approximating the phase noise contribution of the active devices
M1 and M2 are derived.
To calculate the noise, time varying drain currents are first expressed. The oscillator
conduction angle is expressed in terms of device parameters and bias current. Using these
equations, the time varying noise and effective Impulse Sensitivity Function is calculated.
When the effective ISF is known, phase noise can be calculated using methods from [17]
as explained in chapter 4.4.4.
Since both transistors have equal but uncorrelated contribution to the phase noise, the
equation are derived only for device M2 .

Figure 5.24: Oscillator waveforms and ISF

The calculations assume the Q-value of the resonator to be sufficiently high for the differ-
ential tank voltage Vo to be expressed by a cosine
5.3. PULSE WAVE LC OSCILLATOR 115

Vo (φ) = Ao · cos(φ) (5.15)

where Ao is the differential amplitude Vd1 −Vd2 and φ is the oscillator phase. Using (5.15)
the gate-source voltage of transistor M2 can be expressed

A0
vgs2 (φ) = Vbias −Vtail + cos(φ) = VGS + As cos(φ) (5.16)
2
where VGS is the difference between the bias and the average tail voltage, and As is the
voltage swing at the gate of M2 , as illustrated in Fig. 5.24a. When the matching between
M1 and M2 is good, As is equals half the differential oscillation amplitude.
The conduction angle is used to express the part of the oscillation cycle where the gate-
source voltage vgs (φ) is higher than the threshold voltage Vth and the transistors are con-
ducting. To make the equations less cluttered, Φ is here used to represent half the conduc-
tion angle:

Vth −VGS
cos(Φ) = (5.17)
As

Using the square law equation, the drain currents of M2 when the gate voltage is higher
than the threshold voltage can now be expressed

β βA2s
Id2 (φ) = (As cos(φ) +VGS −Vth )2 = (cos(φ) − cos(Φ))2 (5.18)
2 2
where β is the device and process dependent constant.

W
β = µeCox (5.19)
L
µe is the device mobility, Cox the unit gate capacitance and W and L the device width and
length. Equation (5.18) is valid as long as cos(φ) > cos(Φ).
Using (5.18) the instantaneous transconductance of M2 can be expressed:

gm2 (φ) = βAs · (cos(φ) − cos(Φ)) (5.20)

The instantaneous drain thermal noise current in,d2 is a function of gm2 .

4kT γgm2 (φ)∆ f

p
in,d2 (φ) = (5.21)

For long channel devices γ equals 2/3, but may be higher for short channel devices. T is
the absolute temperature and ∆ f is the unity bandwidth. Combining equations (5.20) and
116 5.3. PULSE WAVE LC OSCILLATOR

4kT γβAs ∆ f
p
(5.21) and merging the non time varying parameters into a constant in0,d2 =
the time varying noise can be expressed

p
in,d2 (φ) = in0,d2 · cos(φ) − cos(Φ) (5.22)

Equation (5.22) can be interpreted as a constant noise modulated by a noise modulation

function α(φ)

in,d2 (φ) = in0,d2 · α(φ) (5.23)

From a noise point of view the bypass capacitor Cbypass is large and Vtail an AC ground.
The drain current noise can therefore be considered to be directly injected into tank.
Since tank voltage is a cosine the Impulse Sensitivity Function Γ will be a sinusoidal. The
drain current is injected only into one branch of the tank, and the ISF for drain noise ΓNn
will therefore be half the ISF of the tank:

sin(φ)
ΓNn (φ) = (5.24)
2

Combining α(φ) with equation (5.24) gives the effective Γe f f :

sin(φ) p
Γe f f (φ) = ΓNn α(φ) = · cos(φ) − cos(Φ) (5.25)
2

The waveform of Γe f f is illustrated in Fig. 5.24c. To estimate the 1/ f 2 part of the oscil-
lator phase noise, the RMS value of Γe f f is calculated:

Z Φ
1 sin2 (φ)
Γ2rms,e f f = · (cos(φ) − cos(Φ)) dφ (5.26)
2π −Φ 4

Equation (5.26) can be approximated using a Taylor expansion:

 
1 2 11 1 2
Γ2rms,e f f ≈ · · Φ5 1 − Φ2 ≈ · · Φ5 (5.27)
8π 15 42 8π 15

If the matching between M1 and M2 is good, the average drain current Id2 is equal to half
the bias current:

Z Φ
1 βA2s Ibias
Id2 = · (cos(φ) − cos(Φ))2 dφ = (5.28)
2π −Φ 2 2
5.3. PULSE WAVE LC OSCILLATOR 117

Using Taylor expansion to approximate equation (5.28) and solving the equation, the con-
duction angle can be expressed

 1/5
15π Ibias
Φ≈ (5.29)
βA2s 2

Substituting (5.29) into (5.27) gives the RMS value of the effective ISF:

Ibias
Γ2rms,e f f ≈ (5.30)
8βA2s

Knowing the Γrms,e f f , the 1/ f 2 part of the oscillator phase noise can be calculated using
methods explained in section 4.4. As transistor M1 and M2 have equal noise, the total
phase noise contribution from the active devices to the oscillator is:

Γ2
!
Ibias kT γ
 
i
Lactive (∆ω) = 10 log 2 n0,d2 · 2rms,e f f 2 = 10 log · (5.31)
∆ f 2qmax ∆ω A30 C2 ∆ω2

Interesting to note is that phase noise according to equation (5.31), do not depend on the
device size or the conduction angle.
One might intuitively have expected that since a short conduction angle gives a reduced
effective ISF, it would also give reduced phase noise. However, in order to achieve the
reduced conduction angle, the MOS devices need to deliver a higher peek current, result-
ing in increased peak transconductance and noise. The two effects cancel, and as long as
other parameters such as the oscillation amplitude are constant, phase noise is relatively
independent of the conduction angle.

5.3.5 Oscillation amplitude

The oscillation amplitude is found by multiplying the first harmonic I1 of the output cur-
rent with the equivalent tank parallel resistance RP .
The first harmonic is found by Fourier expanding the drain current

Z Φ
1
I1 = Id2 (φ) cos(φ)dφ (5.32)
π −Φ

β
 
1 2
= A2s cos (Φ) sin(Φ) + sin(Φ) − Φ cos(Φ)
2
(5.33)
π 3 3

which can be approximated

118 5.4. COMPARISON LC AND PULSE WAVE VCO

βA2s 5
 
11 2
I1 ≈ 2 Φ 1− Φ (5.34)
15π 42

Combining equation (5.29) and (5.34), the fundamental current can be expressed in terms
of the bias current

Φ2
 
I1 ≈ Ibias 1 − (5.35)
14

If M1 and M2 are sufficiently wide, the current will be delivered in narrow pulses resulting
in a small conduction angle Φ. The second term of equation (5.35) will then be small and
the oscillation amplitude can be approximated:

A0 = I1 RP ≈ Ibias RP (5.36)

This result is identical to the oscillation amplitude of a Colpitts oscillator [111].

5.3.6 Total phase noise

Assuming Cbypass is large enough to completely filter out the bias noise, the total phase
noise will be the sum of the thermal noise in the tank resistor, and the noise from the active
devices.
Using equation (4.30) from section 4.4.4, the noise from RP is

 
kT
L (∆ω) = 10 · log (5.37)
RP A0C2 ∆ω2
2

Substituting equation (5.36) into (5.31) and combining with (5.37) the total phase noise
of the pulsed waved oscillator can be expressed:

 
1 kT
Ltot,pw (∆ω) = 10 log · · (1 + γ) (5.38)
RP A20 C2 ∆ω2

5.4 Comparison LC and pulse wave VCO

The total phase noise of a LC-VCO in the 1/ f 2 region is according to [111], rewritten to
use the same notation as the rest of this chapter:
5.4. COMPARISON LC AND PULSE WAVE VCO 119

!
1 kT
Ltot,lc (∆ω) = 10 log · · (1 + γ + γηgm,tail RP /2 (5.39)
RP A20,lc C2 ∆ω2

where A0,lc is the differential oscillation amplitude, and η is a function of the amplitude,
bias and process parameters.
The three terms in 1 + γ + γηgm,tail RP /2 represents the contribution from the thermal
noise, active device noise and the bias FET respectively.
The similarity between equation (5.38) and (5.39) is striking. The difference in phase
noise ∆L is

!
1 + γ + γηgm,tail RP /2
 2
A0
∆L (∆ω) = Ltot,lc (∆ω) − Ltot,pw (∆ω) = 10 log ·
A0,lc 1+γ
(5.40)
If the two oscillator topologies are oscillating at the same amplitude they would achieve
the same phase noise performance, assuming the bias noise contribution of the LC-VCO
can be made sufficiently small by minimizing η, for example using methods proposed in
[93], [94] or [95].
However, for the same bias current the pulse wave oscillator will give a higher oscillation
amplitude, and therefore also improved phase noise. The maximum amplitude of an LC
oscillator is

2Ibias RP
A0,lc = (5.41)
π
dividing equation (5.35) and (5.41), the relation between difference oscillation amplitudes
using the same bias current is found.

A0 1
1 − 14 Φ
= (5.42)
A0,lc 2/π

The pulse-wave VCO will operate in class-C for conduction angles Φ less than π/2, giving
an amplitude of the pulsed oscillator at least 1.29 times higher than the LC oscillators. For
small conduction angles the difference is up to 1.57, i.e. the phase noise in a pulse-wave
oscillator will be improved 3.9 dB compared to a LC-VCO for the same tank Q-value and
bias current.
In most LC-VCO implementations the bias noise can not be neglected, and experience
from simulation is that practical phase noise improvements are the range of 5-10 dB, as
discussed in paper 9.
120 5.4. COMPARISON LC AND PULSE WAVE VCO
Chapter 6

Conclusion

This thesis discuss the design and implementation of fully integrated PLL circuits. A
number of methods to analyze and improve circuit performance are proposed and verified
though transceiver implementations.
In low-power and low-cost applications such as BlueTooth and Zigbee, power consump-
tion and circuit area are critical design parameters. In many applications the required
components in the PLL filter are so big it is not cost effective to include the filter com-
ponents on-chip. A method to overcome this limitation is presented in paper 1, where a
frequency synthesizer targeting FSK applications is presented. The synthesizer use open-
loop modulation of the carrier, but unlike conventional implementations, the proposed
synthesizer is open both when transmitting and receiving data. Compared to other mod-
ulation schemes such as direct up-conversion or modulation using closed loop ∆Σ modu-
lation, the proposed method have lower current consumption since most PLL blocks are
disables both when transmitting and receiving data. To achieve low frequency drift a novel
charge-pump topology minimizing leakage current is proposed. The low leakage current
allows the use of a small area on-chip PLL filter giving a cost effective implementation
using no external components.
As the complexity of circuits increase, test and verification becomes problematic since
internal blocks can not be accessed and measured. To allow measurement of on-chip RF
amplitudes, a small area on-chip amplitude detector suitable for integrating is proposed in
paper 2. The small area, flat frequency response and minimal loading makes the circuit
suitable for implementation at many RF nodes throughout a transceiver. Knowledge about
on-chip amplitudes gives important information during circuit debugging and production
test.
Another problem with highly integrated circuits is variation in process and layout. In
order to make circuits robust it is desirable to design circuits that are able to achieve
good performance in the presence of process variations and layout miss-match. This can

121
122

be achieved for example by using automatic circuit calibration. A quadrature oscillator

using calibration of amplitude and phase is proposed in paper 3. The calibration scheme
detects and compensates differences in amplitude between the I and Q branch, improving
phase and amplitude matching at least a factor 10 compared to an uncalibrated circuit.
Another trend besides low power and cheap implementation is radio applications target-
ing high performance. In order to achieve high data rates emerging standards tend to use
more advanced modulation schemes, increasing the requirements on frequency synthe-
sizer spectral purity.
Since the voltage controlled oscillator is one of the most critical PLL building blocks,
oscillators require special attention in terms of device sizing and selection of bias point
and amplitude. A novel oscillator topology capable of achieving reduced phase noise
compared to the LC-VCO topology widely used in todays radio transceivers is presented
in paper 9. The theoretical phase noise reduction compared to a LC-VCO is 3.9 dB, but
thanks to the ability to effectively filter out bias noise, phase noise can often be reduced in
the range of 5-10 dB in practical VCO implementations. The proposed oscillator topology
will become an important building block in future generation radio transceivers.
To achieve good synthesizer performance it is also necessary to predict and minimize un-
wanted frequency components such as phase noise and spurious tones. Since the PLL is
strongly non-linear and involves a wide range of frequencies, circuit simulation is diffi-
cult and direct simulation using analog circuit simulators usually fails. In order to predict
PLL performance it is instead necessary to use a range of simulation and calculation tech-
niques. Throughout this thesis various methods to predict PLL spectral purity using both
analytical and numerical methods are discussed. In particular the impact of the charge-
pump noise is investigated, and methods to reduce charge-pump noise and interferes are
proposed in paper 6 and 7.
By doing careful design it is possible to integrate the frequency synthesizer into a large
system. The feasibility of designing highly integrated frequency synthesizers achiev-
ing excellent phase noise performance is confirmed with the IEEE 802.11abg WLAN
transceiver presented in paper 4 and 5.
While most circuits in this work are targeting highly integrated low cost and low current
applications, the techniques are general and the methods proposed may be used when
designing future generation high performance radio applications.
References

[1] Kirstin Ridley "Global mobile phone use to hit record 3.25 billion" Reuters, Wed
Jun 27, 2007 Available http://www.reuters.com/
[2] SCB "Sverige i siffror 2006, SCB" Publication Services Statistics Sweden ISBN
91-618-1312-5
[3] H. S. Bennett, R. Brederlow, J. C. Costa, P. E. Cottrell, W. M. Huang, A. A. Immor-
lica, J-E. Mueller, M. Racanelli, H. Shichijo, C. E. Weitzel and Bin Zhao "Device
and technology evolution for Si-based RF integrated circuits" IEEE Transactions
on Electron Devices vol. 52 no. 7, July 2005 pp 1235 - 1258
[4] Kwyro Lee, Ilku Nam, Ickjin Kwon, Joonho Gil, Kwangseok Han, Sungchung
Park and Bo-Ik Seo "The Impact of Semiconductor Technology Scaling on CMOS
RF and Digital Circuits for Wireless Application" IEEE Transactions on Electron
Devices vol. 52, no. 7, July 2005, pp 1415-1422
[5] C. Marshall, F. Behbahani, W. Birth, A. Fotowai, T. Fuchs, R. Gaethke, E. Heimeri,
Sheng Lee, P. Moore, S. Navid and E. Saur "A 2.7 V GSM transceiver ICs with on-
chip filtering" Proc. IEEE Int. Solid-State Circuits Conference, ISSCC 15-17 Feb.
1995 pp. 148-149
[6] J. Crols and M. Steyaert "A single-chip 900 MHz CMOS receiver front-end with a
high performance low-IF topology" IEEE Journal of Solid-State Circuits Vol. 30,
No. 12, Dec. 1995 pp. 1483-1492
[7] A. Rofougaran, J.Y.-C Chang, M. Rofougaran, A.A. Abidi "A 1 GHz CMOS RF
front-end IC for a direct-conversion wireless receiver" IEEE Journal of Solid-State
Circuits Vol. 31, No. 7, July 1996 pp. 880-889
[8] A. Abidi, A. Rofougaran, G. Chang, J. Rael, J. Chang, M. Rofougaran and P. Chang
"The future of CMOS wireless transceivers" Proc. IEEE Int. Solid-State Circuits
Conference, ISSCC 6-8 Feb. 1997 pp. 118-119, 440
[9] B. Marholev, M. Pan, E. Chien, L. Zhang, R. Roufoogaran, S. Wu, I. Bhatti, T.-H
Lin, M. Kappes, S. Khorram, S. Anand, A. Zolfaghari, J. Castaneda, C.M. Chien,

123
124 REFERENCES

B. Ibrahim, H. Jensen, H. Kim, P. Lettieri, S. Mak, J. Lin Y.C. Wong, R. Lee,

M. Syed, M. Rofougaran and A. Rofougaran. "A Single-Chip Bluetooth EDR De-
vice in 0.13um CMOS" Proc. IEEE International Solid-State Circuits Conference,
ISSCC. 11-15 Feb. 2007 pp. 558, 759

[10] F. Gardner "Charge pump phase-lock loops" IEEE Trans. Commun., vol. COM-28,
pp. 1849-1858, Nov 1980

[11] Roland E. Best "Phase-Locked Loops Design, Simulation and Applications" 5th
edition, 2003 McGraw-Hill ISBN 0-07-141201-8

[12] F. M. Gardner "Phaselock Techniques" Third edition, 2005 Wiley Interscience,

ISBN 0-471-4306-3

[13] D. Banerjee "PLL Perfornamce, Simulation and Design" Fourth Edition Dog Ear
Publishing, 2006 stand ISBN-10: 1598581341

[14] Mentor Graphics. "Analysis of Phase Noise in Phase-Locked Loops with Eldo RF",
MentorGraphics application note, Nov 2002

[15] Berkeley Design Automation "PLL Noise Analyzer" Software tool.

http://www.berkeley-da.com/

[16] V. Kroupa. "Noise Properties of PLL Systems" IEEE Transactions of Communica-

tions, VOL. COM-30 NO-10, October 1982.

[17] Ali Hajimiri and Thomas H. Lee "A General Theory of Phase Noise in Electrical
Oscillators" IEEE Journal of Solid State Circuits. Vol. 33. No. 2. Feb. 1998 pp.
179-194

[18] S. Levantino, L. Romano, S. Pellerano, C. Samori and A. L. Lacaita "Phase Noise

in Digital Frequency Dividers" IEEE Journal of Solid-State Circuits pp 775-784
Vol. 39, No. 5, May 2004

[19] T.A.D. Riley, N.M. Filiol, D. Qinghong, J. Kostamovaara "Techniques for In-Band
Phase Noise Reduction in DS Synthesizers". IEEE Transactions on Circuits and
Systems II: Analog and Digital Signal Processing. 2003, Vol. 50, No. 11, pp 794 -
803.

[20] H. Arora, N. Klemmer, J.C. Morizio and P.D. Wolf "Enhanced Phase Noise Mod-
eling of Fractional-N Frequency Synthesizers" IEEE Transactions on Circuits and
Systems I. Vol. 52, No. 2, Feb 2007. pp. 379-395

[21] Donhee Ham and Ali Hajimiri "Concepts and Methods in Optimization of Inte-
grated LC VCOs" IEEE Journal of Solid-State Circuits. Vol. 36, No. 6, June 2001,
pp. 896-909
REFERENCES 125

[22] Albert Jergn, Charles G. Sodini. "The Impact of Device Type and Sizing on Phase
Noise Mechanisms" IEEE Journal of Solid-State Circuits. Vol. 40. No. 2. Feb. 2007,
pp. 360-369

[23] Specification of the Bluetooth System 1.2 Available: http://www.bluetooth.com

(url)

[24] Fredrik Westman, Fredrik Jonsson, Tommy Oberg, Christer Hedqvist and Ahmed
Hemani "A Robust CMOS Bluetooth Radio/Modem System-on-Chip" IEEE Cir-
cuit and Systems Magazine. Nov. 2002 pp 7-9, 16

[25] J. Cranninkx and M. Steyaert "A Fully Integrated CMOS DCS-1800 Frequency
Synthesizer" IEEE Journal of Solid State Circuits, Vol 33, No 12, December 1998.

[26] Fredrik Jonsson and Hakan Olsson, "A Quadrature Oscillator using automatic
phase and amplitude tuning" Accepted ISCAS 2008

[27] Dries Hauspie, Eun-Chul Park, and Jan Craninckx "Wideband VCO With Simulta-
neous Switching of Frequency Band, Active Core, and Varactor Size" IEEE Journal
of Solid-State Circuits Vol. 42, No. 7, July 2007

[28] Motorola Semiconductors "MC145190 1.1 GHz PLL Frequency Synthesizers"

Datasheet available http://www.motorola.com (url)

[29] David Byrd, Craig Davis, William O. Keese "A Fast Locking Scheme for PLL
Frequency Synthesizers" National Semiconductor, Santa Clara, CA, Application
Note, July 1995.

[30] Joonsuk Lee, Beomsup Kim "A low-noise fast-lock phase-locked loop with adap-
tive bandwidth control" IEEE Journal of Solid-State Circuits Vol. 35, no. 8, Aug.
2000 pp. 1137-1145

[31] Ching-Yuan Yang, Shen-Iuan Liu "Fast-switching frequency synthesizer with a

discriminator-aided phase detector" IEEE Journal of Solid-State Circuits Vol. 35,
No. 10, Oct. 2000 pp 1445-1452

[32] L.C. Liu, B.H. Li "Fast locking scheme for PLL frequency synthesiser" Electronics
Letters Vol. 40, No. 15, 22 July 2004 pp 918 - 920

[33] S. Levantino, M. Milani, C. Samori and A. L. Lacaita "Fast-Switching Analog PLL

With Finite-Impulse Response" IEEE Transactions on Circuits and Systems-I Vol.
51, No. 9, Sep. 2004, pp 1697-1701.

[34] D. Leenaerts, R. van de Beek, G. van der Weide, J. Bergervoet, K.S. Harish, H.
Waite, Y. Zhang, C. Razzell and R. Roovers "A SiGe BiCMOS 1ns Fast Hopping
Frequency Synthesizer for UWB Radio" Proc. IEEE International Solid-State Cir-
cuits Conference, ISSCC. Feb. 2005. pp 202-203,593
126 REFERENCES

[35] Behbahani, F., Kishigami, Y., Leete, J., Abidi, A.A. "CMOS Mixers and Polyphase
Filters for Large Image Rejection" IEEE Journal of Solid-State Circuits, Vol. 36,
No. 6, pp. 873-887, June 2001.

[36] H. M. Perrott "Fast and accurate behavioral simulation of fractional-N frequency

synthesizers and other PLL/DLL circuits" "Proc. 39th Design Automation Confer-
ence. June 10-14, 2002, pp 498-503.

[37] Lawrence E. Larson "Silicon Technology Tradeoffs for Radio-Frequency/Mixed-

Signal "Systems-on-a-Chip" " IEEE Transactions on Electron Devices. Vol. 50,
No. 3, March 2003 pp 683-699

[38] "Agilent E5052A Signal Source Analyzer" Agilent Technologies Inc. Available
http://www.agilent.com

[39] B. Razavi "RF Microelectronics" Prentice Hall Upper Saddle River, New Jersey.
1998 ISBN 0-13-887571-5

[40] 3rd Generation Partnership Project "3GPP TS 45.005 Technical Specification

Group GSM/EDGE Radio Access Network Radio transmission and reception"
3GPP, 650 Route des Lucioles, Sophia Antipolis Valbonne - FRANCE

[41] J.A.C. Bingham "Multicarrier modulation for data transmission: an idea whose
time has come" IEEE Communications Magazine Vol. 28, No. 5, May 1990, pp
5-14

[42] EICTA MBRAI 2.0 "Mobile and Portable DVB-T/H Radio Access - Part 1: Inter-
face specification" ETSI 650 Route des Lucioles F-06921 Sophia Antipolis Cedex
- FRANCE

[43] Chow, P.S., Tu, J.C., Cioffi, J.M. "Performance Evaluation of a Multichannel
Transceiver System for ADSL and VHDSL services" IEEE Journal of Selected
Areas in Communications, Vol. 9, No. 6, pp. 909-919, August 1991.

[44] IEEE Std 802.11a "Part 11: Wireless LAN Medium Access Control (MAC) and
Physical Layer (PHY) specifications" Adopted by ISO/IEC and redesignated as
ISO/IEC 8802-11:1999/Amd 1:2000(E)

[45] IEEE Std 802.11g-2003, "Part 11: Wireless LAN Medium Access Control (MAC)
and Physical Layer (PHY) specifications Amendment 4: Further Higher Data Rate
Extension in the 2.4 GHz Band", 2003.

[46] IEEE Std 802.16 "IEEE Standard for local and metropolian area networks" IEEE.
3 Park Avenue, New Yourk, NY 10016-5997, USA

[47] ETSI EN 302 304 "Digital Video Broadcasting (DVB); Transmission System for
Handheld Terminals (DVB-H)" ETSI 650 Route des Lucioles F-06921 Sophia An-
tipolis Cedex - FRANCE
REFERENCES 127

[48] 3rd Generation Partnership Project "Long Term Evolution, 3GPP

TS 36.211 - Physical Channels and Modulation" Available
http://www.3gpp.org/ftp/Specs/archive/36_series/36.211/

[49] C. Muschallik "Influence of RF oscillators on an OFDM signal" IEEE Trans. on

Consumer Electronics, Vol. 41, No. 3, Aug. 1995, pp 592-603

[50] J. H. Stott "The effect of phase noise in COFDM" EBU Technical Review, Summer
1998.

[51] Ranulph Poole "Calculating Phase Noise Contributions" BBC Research and De-
velopment Department Technical Note No. R & D 0993C(98) BBC Internal Corre-
spondence.

[52] B. Come, R. Ness, S. Donnay, L. V. de Perre, W. Eberle, P. Wambacq, M. Engels,

and I. Bolsens "Impact of front-end nonidealities on bit error rate performance of
WLAN-OFDM transceivers" Microw. J., vol. 44, no. 2, pp. 126-140 Feb. 2001.

[53] Ana Garcia Armada "Understanding the Effects of Phase Noise in Orthogonal Fre-
quency Division Multiplexing" IEEE Transactions on Broadcating, Vol. 47, No. 2,
June 2001.

[54] H. J. Bergveld, K. M. M. Kaam, D. M. W. Leenaerts, K. J. P. Philips, A. W. P.

Vaassen, G. Wetkezer. "A Low-Power Highly Digitized Receiver for 2.4 GHz Band
GFSK Application" IEEE Microwave Theory and Techniques vol. 53, pp 543-461,
Feb. 2005.

[55] J. Chabloz and C. Enz "A novel I/Q mismatch compensation scheme for a low-
IF receiver front-end" Proc. International Symposium on Circuits and Systems,
ISCAS 2004. Vol. 4, 23-26 May 2004, pp 453-6

[56] J. Tubbax, B. Come, L. Van der Perre, S. Donnay, M. Engels, Hugo De Man and
M. Moonen "Compensation of IQ imbalance and phase noise in OFDM systems"
IEEE Trans. on Wireless Communications Vol. 4, No. 3, May 2005, pp. 872-877

[57] Beat the heat Ross, P.E. Spectrum, IEEE Volume 41, Issue 5, May 2004 Page(s):38
- 43

[58] J. Wilson "RF Design Projects" Presentation Ramsis summer school 2005

[59] Martin Sanden "Inductor design" Spirea internal document.

[60] J.P. Hein, J.W. Scott, J.W. "z-domain model for discrete-time PLL’s" IEEE Trans-
actions on Circuits and Systems vol. 35, No. 11, Nov. 1988 pp 1393-1400

[61] P. K. Hanumolu, M. Brownlee, K. Mayaram and Un-Ku Moon "Analysis of

Charge-Pump Phase-Locked Loops" IEEE Transactions on circuits and systems-
I: Vol 51, NO. 9. September 2004
128 REFERENCES

[62] Perrott M. H, M. D. Trott, and C. G. Sodini. "A modelling approach for SD

fractional-N frequency synthesizers allowing straight forward noise analysis" IEEE
J. Solid-State Circuits, Vol. 33, No. 8, Aug. 2002, pp 1028-1038

[63] M. Hinz, I. Konenkamp, E. H. Horneber "Behavioral modeling and simulation of

phase-locked loops for RF front ends" Proceedings of the 43rd IEEE Midwest Sym-
posium on Circuits and Systems. Vol. 1, 8-11 Aug. 2000, pp 194-197

[64] R.B Staszewski and P.T. Balsara "Phase-domain all-digital phase-locked loop"
IEEE Trans. on Circuits and Systems II: Express Briefs Vol. 52, No. 3, March
2005 pp 159-163

[65] Motorola Semiconductors "Phase-Locked Loop Design Fundamentals" Applica-

tion Note AN535, Motorola Semiconductor Products, 1994

[66] http://www-mtl.mit.edu/researchgroups/perrottgroup/tools.html

[67] K. S. Kundert "Predicting the Phase Noise and Jitter of PLL-Based Frequency Syn-
thesizers" Designers Guide. Sep. 2002. http://www.designers-guide.com

[68] W. F. Egan "Modeling Phase Noise in Frequency Dividers" IEEE Transactions on

Ultrasonics, Ferroelectrics and Frequency Control pp 307-315 Vol. 37, No. 4, July
1990

[69] V. F. Kroupa "Jitter and phase noise in frequency dividers" IEEE Trans. Instrum.
Measure. vol. 50, pp. 1241-1243, Oct. 2001.

[70] L. Romano, S. Levantino et. al. "Low Jitter Design of a 0.35um-CMOS Frequency
Divider Operating up to 3 GHz" ESSCIRC 2002

[71] J. G. Proakis "Communication Systems Engineering" Prentice Hall, Englewood

Cliffs, New Jersey, 1994, ISBN 0-13-300625-5.

[72] D. B. Leeson, "A simple model of feedback oscillator noise spectrum", Proc. IEEE,
vol. 54, pp. 329-330, Feb. 1966.

[73] L.S. Cutler and C.L. Searle "Some aspects of the theory and measurement of fre-
quency fluctuations in frequency standards" Proc. of the IEEE Vol. 54, No. 2, Feb.
1966 pp 136-154

[74] Alper Demir, Amit Mehrotra and Jaijeet Roychowdhury "Phase Noise in Oscil-
lators: A Unifying Theory and Numerical Mathods for Characterization" IEEE
Trans. on Circuits and Systems-I: Fundamental Theory and Applications. Vol. 47,
No. 5, May 2000 pp 655-674

[75] A. Hajimiri and T. H. Lee "Corrections to ’A General Phase Noise Theory in Elec-
trical Oscillators’" IEEE Journal of Solid State Circuits. Vol. 33. No. 6. Jun 1998 p
928
REFERENCES 129

[76] Abumoslem Jannesari and Mahmoud Kamarei "Comments on ’A General Theory

of Phase Noise in Electrical Oscillators’" IEEE Journal of Solid State Circuits. Vol.
42. No. 10. Oct 2007 pp 2314
[77] Piet Vanassche, Georges Gielen and Willy Sansen "On the Difference between
Two Widely Publicized Methods for Analyzing Oscillator Phase Behavior" IC-
CAD 2002. IEEE/ACM International Conference on Computer Aided Design pp
229-233, Nov 2002
[78] Dong-Youl Jeong, Sang-Hoon Chai, Won-Chul Song, Gyu-Hyeong Cho "CMOS
current-controlled oscillators using multiple-feedback-loop ring architectures"
Proc. IEEE International Solid-State Circuits Conference, ISSCC. Feb 1997. pp
386-387, 491
[79] W.B. Wilson, Un-Ku Moon, K.R. Lakshmikumar, Liang Dai "A CMOS self-
calibrating frequency synthesizer" IEEE Journal of Solid-State Circuits. Vol. 35.
No. 10. Oct. 2000 pp 1437-1444
[80] John A. McNeill "Jitter in Ring Oscillators" IEEE Journal of Solid-State Circuits.
Vol. 32, No. 6, Jun. 1997. pp. 870-879
[81] Ali Hajimiri, Sotirios Limotyrakis and Thomas H. Lee "Jitter and Phase Noise in
Ring Oscillators" IEEE Journal of Solid-State Circuits. Vol. 34, No. 6, Jun. 1999
pp. 790-804
[82] Abidi A.A, Meyer, R.G. "Noise in relaxation oscillators" IEEE Journal of Solid-
State Circuits Vol. 18, No. 6, March 1983, pp 794-802
[83] Banu, M. "MOS oscillators with multi-decade tuning range and gigahertzmaximum
speed" IEEE Journal of Solid-State Circuits. Vol. 23, No. 6, Dec. 1988. pp. 1386-
1393
[84] B. Razavi, T. Aytur, Fei-Ran Yang, Ran-Hong Yan, Han-Chang Kang, Cheng-
Chung Hsu and Chao-Cheng Lee "A 0.13 um CMOS UWB transceiver" Proc. IEEE
Int. Solid-State Circuits Conference, ISSCC 6-10 Feb. 2005 pp. 216, 594
[85] B. Hewlett and D. Packard "HP 200A Precision sine wave oscillator" Information
available at HP virtual museum. http://www.hp.com
[86] J. Craninckx, M. Steyaert "A 1.8-GHz low-phase-noise spiral-LC CMOS VCO"
1996 Symposium on VLSI Circuits 13-15 June 1996, pp 30-31
[87] J. Craninckx, M. Steyaert "Low-noise voltage-controlled oscillators using en-
hanced LC-tanks" IEEE Transactions on Circuits and Systems II: Analog and Dig-
ital Signal Processing Vol. 42, No. 12, Dec. 1995, pp 794-804
[88] Jan Craninckx and Michiel S. J. Steyaert "A 1.8-GHz Low-Phase-Noise CMOS
VCO Using Optimized Hollow Spiral Inductors" IEEE Journal of Solid-State Cir-
cuits Vol. 32, No. 5, May 1997 pp 736-744
130 REFERENCES

[89] P. Andreani, S. Mattisson "On the use of MOS varactors in RF VCOs" IEEE Journal
of Solid-State Circuits, Vol. 35, No. 6, June 2000 pp 905-910

[90] Ryan Lee Bunch and Sanjay Raman "Large-Signal Analysis of MOS Varactors in
CMOS-Gm LC VCOs" IEEE Journal of Solid-State Circuits Vol. 38. No. 8. Aug.
2003 pp 1325-1332

[91] J. Rael and A. Abidi "Physical processes of phase noise in electrical oscillators"
Proc. IEEE Custom Integrated Circuits Conrerence, CICC, 2000. pp. 569-572

[92] A. Zanchi, C. Samori, S. Levantino and A.L. Lacaita "A 2-V 2.5-GHz-104-dBc/Hz
at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude
control loop" IEEE Journal of Solid State Circuits Vol. 36. No. 4. Apr. 2001, pp
611-619

[93] Emad Hegazi, Henrik Sjöland and Asad A. Abidi "A Filtering Technique to Lower
LC Oscillator Phase Noise" IEEE Journal of Solid State Circuits Vol. 36. No. 12.
Dec. 2001, pp 1921-1930

[94] P. Andreani and H. Sjoland "Tail current noise suppression in RF CMOS VCOs"
IEEE Journal of Solid State Circuits Vol. 37. No. 3. Mars 2002, pp 342-348

[95] Hyman N. Shanan, Michael P. Kennedy "A Technique to Reduce Flicker Noise
Up-Conversion in CMOS LC Voltage-Controlled Oscillators" ESSCIRC 2004 Pro-
ceedings of the 30th European Solid-State Circuit Conference, 2004 pp 123-126

[96] S. Levantino, C. Samori, A. Bonfanti, S.L.J. Gierkink, A.L Lacaita and V. Boccuzzi
"Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning
range and flicker noise upconversion" IEEE Journal of Solid State Circuits Vol. 37.
No. 8. Aug. 2002, pp. 1003-1011

[97] A. Hajimiri and T.H. Lee. "Design issues in CMOS differential LC oscillators"
IEEE Journal of Solid-State Circuits. Vol. 34, No. 5, May 1999, pp 717-724

[98] Chih-Ming Hung, Brian A. Floyd and Kenneth K. 0 "A fully integrated 5.35-GHz
CMOS VCO and a prescaler" Proc. IEEE Radio Frequency Integrated Circuits
(RFIC) Symposium 11-13 June 2000 pp 69-72

[99] Tsung-Hsien Lin, Ruei-Lin Hsu, Cheng-Lung Li and Ying-Che Tseng "A 5 GHz,
192.6 dBc/Hz/mW FOM, LC-VCO System With Amplitude Control Loop and
LDO Voltage Regulator in 0.18 um CMOS" IEEE Microwave and Wireless Com-
ponents Letters Vol. 17, No. 10, Oct. 2007 pp. 730-732

[100] N. Itoh, B. De Muer and M. Steyaert "Low supply voltage fully integrated CMOS
VCO with three terminals spiral inductor" Proc. 25th European Solid-State Circuits
Conference ESSCIRC 21-23 Sept. 1999 pp. 194-197
REFERENCES 131

[101] M. Tiebout "Low-power low-phase-noise differentially tuned quadrature VCO de-

sign in standard CMOS" IEEE Journal of Solid-State Circuits Vol. 36, No. 7, July
2001 pp. 1018-1024
[102] A. Kampe and H. Olsson "An LC-VCO with one octave tuning range" Proc. Euro-
pean Conference on Circuit Theory and Design Vol. 3, 28 Aug.-2 Sept. 2005 pp.
321 -324
[103] Pietro Andreani and Ali Fard "More on the 1/f2 Phase Noise Performance of
CMOS Differential-Pair LC-Tank Oscillators" IEEE Journal of Solid State Circuits.
Vol. 41. No. 12. Dec. 2006, pp 2703-2712
[104] Jian Chen, Fredrik Jonsson, Li-Rong Zheng, Diand Zhou, "Device Sizing during
Differencial Pair LC Oscillator Design". Norchip 2007
[105] Staszewski R.B., Leipold D., Chih-Ming Hung, Balsara, P.T. "A first digitally-
controlled oscillator in a deep-submicron CMOS process for multi-GHz wireless
applications" 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium
pp 81-84 June 2003
[106] M. Demirkan, S.P. Bruss, R.R. Spencer "11.8GHz CMOS VCO With 62% Tuning
Range Using Switched Coupled Inductors" Proc. IEEE Radio Frequency Integrated
Circuits RFIC 3-5 June 2007 pp. 401-404
[107] Y. Ito, Y. Yoshihara, H. Sugawara, K. Okada and K. Masu "A 1.3-2.8 GHz Wide
Range CMOS LC-VCO Using Variable Inductor" Asian Solid-State Circuits Con-
ference, 2005 Nov. 2005 pp. 265 - 268
[108] A.M. Niknejad "Modeling of passive elements with ASITIC" IEEE Radio Fre-
quency Integrated Circuits (RFIC) Symposium 2-4 June 2002 pp. 303-306
[109] S. Saeedi, S. Mehrmanesh, A. Tajalli and M. Atarodi "A technique to suppress tail
current flicker noise in CMOS LC VCOs" Proc. IEEE International Symposium on
Circuits and Systems 21-24 May 2006 pp.
[110] F. Jonsson "En oscillator med lågt fasbrus" Spirea internal documentation, Mars.
2000
[111] Pietro Andreani, Xioyan Wang, Luca Vandi and Ali Fard "A Study of Phase Noise
in Colpitts and LC-Tank CMOS Oscillators" IEEE Journal of Solid State Circuits,
Vol. 40. No. 5. May 2005 pp 1107-1118
[112] Alir Fard and Pietro Andreani "An Analysis of 1/f2 Phase Noise in Bipolar Colpitts
Oscillators (With a Diression on Bipolar Differential-Pair LC Oscillators)" IEEE
Journal of Solid State Circuits. Vol. 42. No. 2. Feb. 2007, pp. 374-384
[113] B. Soltanian, P.R. Kinget "Tail Current-Shaping to Improve Phase Noise in LC
Voltage-Controlled Oscillators" IEEE Journal of Solid-State Circuits Vol. 41, No.
8, Aug. 2006 pp. 1792-1802
132 REFERENCES

[114] Andrea Mazzanti, Pietro Andreani "A 1.4mW 4.9-to-5.65 GHz Class-C CMOS
VCO with an Average FoM of 194.5 dBc/Hz" Proc. IEEE International Solid-State
Circuits Conference, ISSCC. Feb 2008, pp. 474-475,629
Appendix A

Calculation of loop-filter
components

Figure A.1 shows the circuit diagram of a second order loop-filter.

Figure A.1: 2nd order loop-filter.

The loop filter has a transfer function F(s):

sC2 R + 1
F(s) = (A.1)
s(C1 +C2 + sC1C2 R)
Identifying the poles and zeros, equation (A.1) can be expressed:

1 + s/ωz 1
F(s) = · (A.2)
s(1 + s/ω p ) C1 +C2
where

C1 +C2
ωp = (A.3)
C1C2 R

133
134

and

1
ωz = (A.4)
RC2
In a PLL the open loop transfer function is:

KVCO 1
G(s) = KD · F(s) · · (A.5)
s N
where KD and KVCO is the phase detector and VCO gain respectively. N is the feedback
divider division ratio.
Figure A.2 shows the corresponding bode plot and pole-zero constallation for the open
loop PLL.

Figure A.2: Loop-filter bode plot and corresponding poles and zeros

The loop-filter and the VCO form one pole in the origin each. The uncompensated loop
would be unstable, and the resistor create a compensating zero to improve the phase mar-
gin.
The open loop have unity gain at frequency ω1 , where

ω1 = 2π · BW (A.6)

BW is called the bandwidth of the PLL.

This section describes a method to calculate the component values of the loop-filter com-
ponents in order to acheive a maximum phase margin PM at the the unity gain frequency
ω1 .
A.1. CALCULATION OF FREQUENCY OF POLE AND ZERO 135

A.1 Calculation of frequency of pole and zero

The total phase shift around the open loop is:

ϕ = −180 + ϕz − ϕ p (A.7)

Since the PLL use negative feedback, the phase margin will be:

PM = ϕz − ϕ p (A.8)

or expressed using poles and zeros:

PM = arctan(ω/ωz ) − arctan(ω/ω p ) (A.9)

The frequency where maximum phase margin is achieved is calculated by setting the
derivative of the phase margin to zero. Solving the equation gives the frequency ω1 where
maximum phase margin is acheived:

ω2 = ω p ωz (A.10)

Assuming we want maximum phase margin at the loop-filter bandwidth, ω = ω1 . Com-

bining (A.9) and (A.10) the phase margin can then be expressed:

PM = ϕz − ϕ p = arctan(ω p /ω1 ) − arctan(ω1 /ω p ) (A.11)

Equation (A.11) can be interpreted as ϕz and ϕ p are the angles of oposit corners in a right
triangle. Since the sum of the angles in a triangle is 180◦ , the sum of ϕz and ϕ p is

ϕz + ϕ p = 90◦ (A.12)

The phase margin can now be expressed:

PM = ϕz − (90◦ − ϕz ) (A.13)

giving that:

PM + 90◦
ϕz = (A.14)
2
and corresponding:
136 A.2. CALCULATION OF COMPONENT VALUES

90◦ − PM
ϕp = (A.15)
2
The frequency of the poles and zeros can now be expressed in terms of ω1 and PM:

90◦ − PM
 
ωz = ω1 · tan(ϕz ) = ω1 · tan (A.16)
2
and

PM + 90◦
 
ω p = ω1 · tan(ϕ p ) = ω1 · tan (A.17)
2

A.2 Calculation of component values

When the frequency of the pole and zero are known, the values of C1 , C2 and R can be
calculated to give unity gain frequency at ω1 .
Rearranging equation (A.5), the magnitude of the open-loop transfer function at frequency
ω1 can be expressed:

ICP KVCO H(s)

|G(s)| = · (A.18)
N s

The magnitude of the frequency dependent component is:

p
H(s) 1 + (ω1 /ωz )2 1
= 2p · (A.19)
s ω1 1 + (ω1 /ω p ) C1 +C2
2

Using (A.10), equation (A.19) can be simplified to:

H(s) 1 1
= · (A.20)
s ω1 ωz C1 +C2

KD , KVCO and N are known and the magnitude at ω1 should be 1. The sum of C1 and C2
can now be identified:

ICP KVCO 1
C1 +C2 = · (A.21)
N ω1 ωz

Using equation (A.21) together with (A.3), (A.4), (A.17) and (A.16) the component values
can now be identified:
A.2. CALCULATION OF COMPONENT VALUES 137

ICP KVCO 1
C1 = · (A.22)
N ω1 ω p

ICP KVCO 1
C2 = · −C1 (A.23)
N ω1 ωz

1
R= (A.24)
ωzC2

or expressed using ω1 and PM:

ICP KVCO tan(45◦ − PM/2)

C1 = · (A.25)
N ω21

ICP KVCO 2
C2 = · 2 (A.26)
N ω1 tan(90◦ − PM)

N ω1
R= · (A.27)
ICP KVCO 1 − tan2 (45◦ − PM/2)

Equation (A.25), (A.26) and (A.27) can be used to directly calculate the loop-filter com-
ponents values to give desired loop-filter bandwidth and phase margin.
138 A.2. CALCULATION OF COMPONENT VALUES
Appendix B

Behavioral models

B.1 VCO behavioral model

// VerilogA for fj_test, vco_beh, veriloga

‘include "constants.vams"
‘include "disciplines.vams"

module vco_beh(out, enable, gnda, ibias, trim, vdda, vtune);

input vdda, gnda;

input enable, ibias, vtune;
input [2:0] trim;
output out;

electrical vdda, gnda;

electrical enable, ibias, vtune;
electrical [2:0] trim;
electrical out;

parameter real thres = 0.9; // Above thres logical 1

parameter real bias_nom = 1e-3;
parameter real tol = 0.1; // 10% tolerance

real Cvar, Ctrim, fr;

integer tr;

analog begin
// Calculate trim value
tr = V(trim[0]) > thres ? 1 : 0;

139
140 B.2. DIVIDER BEHAVIORAL MODEL

tr = tr + (V(trim[1]) > thres ? 2 : 0);

tr = tr + (V(trim[2]) > thres ? 4 : 0);

// Check enable signal and bias

if ((V(enable) > thres) &&
(I(ibias) > bias_nom*(1-tol)) &&
(I(ibias) < bias_nom*(1+tol))) begin

// If enable and bias correct, calculate frequency

Ctrim = 1-0.075*tr;
Cvar = 1.05-0.2*tanh(2.5*(V(vtune)-0.2));
fr = 100/(sqrt((Ctrim+Cvar)*10)*2*3.1415);
end else begin
// Else, set frequency output to zero
fr = 0.0;
end;

// Set outputs
V(ibias) <+ 0.9; // Fix bias input to reasonable voltage
V(out) <+ fr; // 1V = 1GHz
end
endmodule

B.2 Divider behavioral model

// Divider behavioral model
// Model for programmable divider
// dividing between 32 and 47

‘include "constants.vams"
‘include "disciplines.vams"

module divider_beh(out, N, enable, gnda, ibias, in, vdda);

input vdda, gnda;

input in, ibias, enable;
input [3:0] N;
output out;

electrical vdda, gnda;

electrical in, ibias, enable;
electrical [3:0] N;
electrical out;

parameter real thres = 0.9; // Above thres logical 1

B.2. DIVIDER BEHAVIORAL MODEL 141

parameter real bias_nom = 100e-6;

parameter real tol = 0.1; // 10% tolerance
parameter real scale = 1e9; // 1V input = 1GHz

real freq, phase;

integer div_n;

analog begin
// Reset variables at initial timestep
@(initial_step) begin
phase = 0.0;
end

// Update division value only when one full period has passed
@(initial_step or cross(V(out)-0.9, 1)) begin
div_n = 32 + (V(N[0]) > thres ? 1 : 0);
div_n = div_n + (V(N[1]) > thres ? 2 : 0);
div_n = div_n + (V(N[2]) > thres ? 4 : 0);
div_n = div_n + (V(N[3]) > thres ? 8 : 0);
end

// Check enable signal and bias

if ((V(enable) > thres) &&
(I(ibias) > bias_nom*(1-tol)) &&
(I(ibias) < bias_nom*(1+tol))) begin

// If enable and bias correct, set the frequency

freq = V(in)*scale/div_n;
end else begin
freq = 0.0;
end

// Set generate outputs

phase = idtmod(freq*‘M_TWO_PI, 0, ‘M_TWO_PI);
V(ibias) <+ 0.9; // Fix bias input to reasonable voltage
V(out) <+ 0.9*sin(phase)+0.9;

// Limit time steps so at least 10 points are generated

// each period
$bound_step(1/(freq*10));

end

endmodule