MODULE 2

Data Processing Instructions

 The data processing instructions manipulate data within registers. They are move
instructions, arithmetic instructions, logical instructions, compare instructions and multiply
instructions.
 Most data processing instructions can process one of their operands using the barrel shifter.
 If S is suffixed on a data processing instruction, then it updates the flags in the cpsr.
MOVE INSTRUCTIONS:
 It copies N into a destination register Rd, where N is a register or immediate value. This
instruction is useful for setting initial values and transferring data between registers.

Syntax: <instruction> {<cond>} {S} Rd, N

 In the example shown below, the MOV instruction takes the contents of register r5 and
copies them into register r7.

USING BARREL SHIFTER WITH DATA TRANSFER INSTRUCTION:

 Data processing instructions are processed within the arithmetic and logic unit (ALU).
 A unique and powerful feature of the ARM processor is the ability to shift the 32-bit binary
pattern in one of the source registers left or right by a specific number of positions before
it enters the ALU.
 This shift increases the power and flexibility of many data processing operations.
 For example, We apply a logical shift left (LSL) to register Rm before moving it to the
destination register.
PRE r5=5
r7=8
MOV r7, r5, LSL #2
POST r5=5
r7=20
 The above example shift logical left r5=5 (00000101 in binary) by two bits and then
r7=20 (00010100 in binary).
 Figure: Barrel shifter and ALU
 Following table shows barrel shifter operation

ARITHMETIC INSTRUCTIONS:
  The arithmetic instructions implement addition and subtraction of 32-bit signed and
unsigned values.
Syntax: <instruction>{<cond>} {S} Rd, Rn, N

 In the following example, subtract instruction subtracts a value stored in register r2 from
a value stored in the register r1. The result is stored in register r0.

 In the following example, the reverse subtract instruction (RSB) subtract r1 from the
constant value #0, writing the result in r0.

USING THE BARREL SHIFTER WITH ARITHMETIC INSTRUCTIONS:

 Example below illustrates the use of the inline barrel shifter with an arithmetic instruction.
The instruction multiplies the value stored in register r1 by three.
 Register r1 is first shifted one location to the left to give the value of twice r1. The ADD
instruction then adds the result of the barrel shift operation to register r1. The final result
transferred into register r0 is equal to three times the value stored in register r1.
LOGICAL INSTRUCTIONS:
 Logical instructions perform bitwise operations on the two source registers.
Syntax: <instruction> {<cond>} {S} Rd, Rn, N

 In the example shown below, a logical OR operation between registers r1 and r2 and the
result is in r0.

COMPARISON INSTRUCTIONS:
 The comparison instructions are used to compare or test a register with a 32-bit value. They
update the cpsr flag bits according to the result, but do not affect other registers.
 After the bits have been set, the information can be used to change program flow by using
conditional execution.
Syntax: <instruction> {<cond>} Rn, N

 Example shown below for CMP instruction, both r0 and r1 are equal before the execution
of the instruction. The value of the z flag prior to the execution is 0 and after the execution
z flag changes to 1 (upper case of Z).
 The CMP is effectively a subtract instruction with the result discarded;
Similarly the TST instruction is a logical AND operation and TEQ is a logical XOR
operation. For each, the results are discarded but the condition bits are updated in the cpsr.
MULTIPLY INSTRUCTIONS:
 The multiply instructions multiply the contents of a pair of registers and depending upon
the instruction, accumulate the results in another register.
 The long multiplies accumulate onto a pair of registers representing a 64-bit value.
Syntax: MLA {<cond>} {S} Rd, Rm, Rs, Rn
MUL {<cond>} {S} Rd, Rm, Rs

Syntax: <instruction> {<cond>} {S} RdLo, RdHi, Rm, Rs

 In the following example below shows a multiply instruction that multiplies registers r1
and r2 and places the result into the register r0.

 The long multiply instructions (SMLAL, SMULL, UMLAL, and UMULL) produce a 64-
bit result.
BRANCH INSTRUCTIONS
Q2. Explain briefly branch instructions of ARM processor.
Answer:
 A branch instruction changes the flow of execution or is used to call a routine.
 This type of instruction allows programs to have subroutines, if-then-else structures, and
loops.
 The change of execution flow forces the program counter (pc) to point to a new address.

 T refers to the Thumb bit in the cpsr.

 When instruction set T, the ARM switches to Thumb state.
 The example shown below is a forward branch. The forward branch skips three
instructions.

 The branch with link (BL) instruction changes the execution flow in addition overwrites
the link register lr with a return address. The example shows below a fragment of code
that branches to a subroutine using the BL instruction.
 
The branch exchange (BX) instruction uses an absolute address stored in register Rm.
It is primarily used to branch to and from Thumb code. The T bit in the cpsr is updated
by the least significant bit of the branch register.
 Similarly, branch exchange with link (BLX) instruction updates the T bit of the cpsr
with the least significant bit and additionally sets the link register with the return address.
LOAD-STORE INSTRUCTIONS ( Memory Access Instructions)
 Load-store instructions transfer data between memory and processor registers. There are
three types of load-store instructions: single-register transfer, multiple-register transfer,
and swap.
a) Single-Register Transfer
 These instructions are used for moving a single data item in and out of a register.
 Here are the various load-store single-register transfer instructions.
Syntax: <LDR|STR>{<cond>}{B} Rd, addressing 1
LDR{<cond>}SB|H|SH Rd, addressing 2
STR{<cond>}H Rd, addressing 2

 Example:
1. LDR r0, [r1]
o This instruction loads a word from the address stored in register r1 and places it
into register r0.
 2. STR r0, [r1]
 This instruction goes the other way by storing the contents of register r0 to the
address contained in register r1.

b) Multiple-Register Transfer
 Load-store multiple instructions can transfer multiple registers between memory and the
processor in a single instruction. The transfer occurs from a base address register Rn
pointing into memory.
 Multiple-register transfer instructions are more efficient from single-register transfers for
moving blocks of data around memory and saving and restoring context and stacks.

Syntax: <LDM|STM>{<cond>}<addressing mode> Rn{!},<registers>{ˆ}

 Here N is the number of registers in the list of registers.

c) SWAP Instruction
 The swap instruction is a special case of a load-store instruction. It swaps the
contents of memory with the contents of a register.

Syntax: SWP {B} {<cond>} Rd, Rm, [Rn]

Addressing modes:
Single-Register Load-Store Addressing Modes
 The ARM instruction set provides different modes for addressing memory.
  These modes incorporate one of the indexing methods: preindex with writeback, preindex,
and postindex

Example:

Addressing mode for load-store multiple instructions

 Table below shows the different addressing modes for the load-store multiple instructions.
Example:
mem32[0x8001c] =0x04

 If LDMIA is replaced with LDMIB post execution the content of registers is shown below

STACK OPERATIONS
 The ARM architecture uses the load-store multiple instructions to carry out stack
operations.
 The pop operation (removing data from a stack) uses a load multiple instruction; similarly,
the push operation (placing data onto the stack) uses a store multiple instruction.
 When you use a full stack (F), the stack pointer sp points to an address that is the last
used or full location.
 In contrast, if you use an empty stack (E) the sp points to an address that is the first
unused or empty location.
 A stack is either ascending (A) or descending (D). Ascending stacks grow towards higher
memory addresses; in contrast, descending stacks grow towards lower memory addresses.
  Addressing modes for stack operation

 The LDMFD and STMFD instructions provide the pop and push functions, respectively.
 Example1: With full descending

Figure: STMFD instruction full stack push operation.

Example 2: With empty descending

Figure: STMED instruction empty stack push operation.

SOFTWARE INTERRUPT INSTRUCTION

Q3. Explain briefly the software interrupt instruction.
Answer:
 A software interrupt instruction (SWI) causes a software interrupt exception, which
provides a mechanism for applications to call operating system routines.
 Syntax: SWI {<cond>} SWI_number

 When the processor executes an SWI instruction, it sets the program counter pc to the offset
0xB in the vector table.
 The instruction also forces the processor mode to SVC, which allows an operating system
routine to be called in a privileged mode.
 Each SWI instruction has an associated SWI number, which is used to represent a particular
function call or feature.
 The example below shows an SWI call with SWI number 0x123456, used by ARM
toolkits as a debugging SWI.

 Since SWI instructions are used to call operating system routines, it is required some form
of parameter passing.
 This achieved by using registers. In the above example, register r0 is used to pass parameter
0x12. The return values are also passed back via register.

Program Status Register Instructions

Q4. Explain briefly program status register instructions.
Answer:
 The ARM instruction set provides two instructions to directly control a program status
register (psr).
  The MRS instruction transfers the contents of either the cpsr or spsr to general purpose
register.
 The MSR instruction transfers the contents of a general purpose register to cpsr or spsr.
 Together these instructions are used to read and write the cpsr and spsr.
Syntax: MRS {<cond>} Rd <cpsr |spsr>
MSR {<cond>} <cpsr|spsr} _<fields>,Rm
MSR {<cond>} <cpsr|spsr} _<fields>, #immediate
 The table shows the program status register instructions

Coprocessor Instructions
Q5. Explain briefly coprocessor instructions.
Answer:
 Coprocessor instructions are used to extend the instruction set.
 A coprocessor can either provide additional computation capability or be used to control
the memory subsystem including caches and memory management.
 These instructions are used only by core with a coprocessor.
Syntax: CDP {<cond>} cp,opcode1, Cd, Cn {,opcode2}
<MRC|MCR>{<cond>}cp,opcode1,Rd,Cn,Cm{,opcode2}
<LDC|STC>{<cond>}cp,Cd,addressing

 In the syntax of the coprocessor instructions, the cp field represents the number between
p0 and p15. The opcode fields describe the operation to take place on the coprocessor. The
Cn, Cm and Cd fields describe registers within the coprocessor.
 For example: The instruction below copies coprocessor CP15 register c0 into a general
purpose register r10.
MRC p15, 0, r10, c0, c0, 0 ; CP15 register-0 is copied into general purpose
register r10.
 For example: The instruction below moves the contents of CP15 control register c1 into
register r1 of the processor core.
MRC p15, 0, r1, c1, c0, 0
Loading Constants
Q6. Explain briefly the loading constants.
Answer:
 There are two pseudo instructions to move a 32-bit constant value to a register.
Syntax: LDR Rd, =constant
ADR Rd, label

 The example below shows an LDR instruction loading a 32-bit constant 0xff00ffff into
register r0.
LDR r0, =0xff00ffff

WRITING AND OPTIMIZING ARM ASSEMBLY CODE

Writing assembly by hand gives you direct control of three optimization tools that you cannot
explicitly use by writing C source:

■ Instruction scheduling: Reordering the instructions in a code sequence to avoid processor stalls.
Since ARM implementations are pipelined, the timing of an instruction can be affected by
neighboring instructions.
■ Register allocation: Deciding how variables should be allocated to ARM registers or stack
locations for maximum performance. Our goal is to minimize the number of memory accesses.
■ Conditional execution: Accessing the full range of ARM condition codes and conditional
instructions.

Writing Assembly Code

Example 6.1
This example shows how to convert a C function to an assembly function—usually the first stage
of assembly optimization. Consider the simple C program main.c following that prints the squares
of the integers from 0 to 9:
 int square(int i)
{
return i*i;
}
 Let’s see how to replace square by an assembly function that performs the same action.
Remove the C definition of square, but not the declaration (the second line) to produce a
new C file main1.c. Next add an armasm assembler file square.s with the following
contents:

 The AREA directive names the area or code section that the code lives in. If you use
nonalphanumeric characters in a symbol or area name, then enclose the name in vertical
bars.
 The EXPORT directive makes the symbol square available for external linking.
 The input argument is passed in register r0, and the return value is returned in register r0.
 The multiply instruction has a restriction that the destination register must not be the same
as the first argument register. Therefore we place the multiply result into r1 and move this
to r0.
 The END directive marks the end of the assembly file. Comments follow a semicolon.
 Example 6.1 only works if you are compiling your C as ARM code. If you compile your C
as Thumb code, then the assembly routine must return using a BX instruction as shown
below
Example 6.2
This example shows how to call a subroutine from an assembly routine. We will take Example 6.1
and convert the whole program (including main) into assembly. We will call the C library routine
printf as a subroutine. Create a new assembly file main3.s with the following contents:

 We have used a new directive, IMPORT, to declare symbols that are defined in other files.
 The imported symbol Lib$$Request$$armlib makes a request that the linker links with the
standard ARM C library. The WEAK specifier prevents the linker from giving an error if
the symbol is not found at link time. If the symbol is not found, it will take the value zero.
 The second imported symbol ___main is the start of the C library initialization code.
 You only need to import these symbols if you are defining your own main; a main defined
in C code will import these automatically for you. Importing printf allows us to call that C
library function.
 The RN directive allows us to use names for registers. In this case we define i as an alternate
name for register r4. Using register names makes the code more readable.
 Recall that ATPCS states that a function must preserve registers r4 to r11 and sp. We
corrupt i(r4), and calling printf will corrupt lr.
 Therefore we stack these two registers at the start of the function using an STMFD
instruction. The LDMFD instruction pulls these registers from the stack and returns by
writing the return address to pc.
 The DCB directive defines byte data described as a string or a comma-separated list of
bytes.
 Note that Example 6.3 also assumes that the code is called from ARM code. If the code
can be called from Thumb code as in Example 6.2 then we must be capable of returning to
Thumb code.
EXAMPLE