Full/Low Speed USB Digital Isolator

Preliminary Technical Data ADuM4160

FEATURES isolation components provide outstanding performance
USB 2.0 compatible characteristics and are easily integrated with low and full speed
Enhanced system-level ESD performance per IEC 61000-4-x USB compatible peripheral devices.
4.0 V to 5.5V operation Many microcontrollers implement USB so that it presents only
7 mA maximum up-stream supply current @ 1.5 Mbps the D+ and D- lines to external pins. This is desirable in many
8 mA maximum up-stream supply current @ 12 Mbps cases because it minimizes external components and simplifies
2.5mA up-stream idle current the design; however, this presents particular challenges when
Bidirectional communication isolation is required. Since the USB lines must switch between
Up Stream Short Circuit Protection actively driving D+/D- and allowing external resistors to set the
High temperature operation: 105°C state of the bus, the ADuM4160 provides mechanisms for
Low and Full Speed data rate: 1.5Mbps and 12 Mbps detecting the direction of data flow and control over state of the
High common-mode transient immunity: >25 kV/μs output buffers. Data direction is determined on a packet by
16-lead SOIC wide body package packet basis.
RoHS compliant models available
The ADuM4160 uses the edge detection based iCoupler
Safety and regulatory approvals (Pending)
technology in conjunction with internal logic to implement a
UL recognition: 5000 V rms for 1 minute per UL 1577
transparent, easily configured, up-stream facing port isolator.
CSA Component Acceptance Notice #5A
Isolating the up-stream port provides several advantages in
IEC 60601-1: 250 V rms (reinforced)
simplicity, power management and robust operation.
IEC 60950-1: 600 V rms (reinforced)
VDE certificate of conformity The isolator has propagation delay comparable that of a
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 standard hub and cable. It operates with the supply voltage on
VIORM = 846 V peak either side ranging from 3.0 V to 5.5 V, allowing connection
directly to VBUS by internally regulating the voltage to the
APPLICATIONS signaling level. The ADuM4160 provides isolated control of the
USB peripheral isolation pull-up resistor to allow the peripheral to control connection
Isolated USB Hub timing. The device draws low enough idle current that a
Repeaters suspend state is not required.

1
GENERAL DESCRIPTION Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329. Other patents
pending.
1
The ADuM4160 is a USB-port isolator, based on Analog
Devices, Inc. iCoupler® technology. Combining high speed
CMOS and monolithic air core transformer technology, these

FUNCTIONAL BLOCK DIAGRAMS

Figure 1. ADuM4160

Rev. Pr F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that mayresult from its use. Specifications subjectto change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Trademarks and registeredtrademarks arethe property oftheir respective owners. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
ADuM4160 Preliminary Technical Data

TABLE OF CONTENTS
Features .............................................................................................. 1 ESD Caution...................................................................................7
Applications....................................................................................... 1 Pin Configurations and Function Descriptions ............................8
General Description ......................................................................... 1 Application Information................................................................ 10
Functional Block Diagrams............................................................. 1 Functional Description.............................................................. 10
Revision History ............................................................................... 2 Product Useage ........................................................................... 10
Specifications..................................................................................... 3 Power Supply Options ............................................................... 10
Electrical Characteristics............................................................. 3 PC Board Layout ........................................................................ 11
Package Characteristics ............................................................... 5 Propagation Delay-Related Parameters Error! Bookmark not
Regulatory Information............................................................... 5 defined.

Insulation and Safety-Related Specifications............................ 5 DC Correctness and Magnetic Field Immunity..................... 11

DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Insulation Lifetime ..................................................................... 12

Characteristics .............................................................................. 6 Outline Dimensions ....................................................................... 14
Recommended Operating Conditions ...................................... 6 Ordering Guide .......................................................................... 14
Absolute Maximum Ratings............................................................ 7

REVISION HISTORY
6

Rev. Pr F | Page 2 of 14
Preliminary Technical Data ADuM4160

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
4.0 V ≤ VBUS1 ≤ 5.5 V, 4.0 V ≤ VBUS2 ≤ 5.5 V; 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All min/max specifications apply over the entire
recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. All voltages are
relative to their respective ground.

Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
ADuM4160, Total Supply Current1
1.5 Mbps
VDD1 or VBUS1 Supply Current IDD1 (L) 5 7 mA 750kHz logic signal rate CL=450pF
VDD2 or VBUS2 Supply Current IDD2 (L) 5 7 mA 750kHz logic signal rate CL=450pF
12 Mbps
VDD1 or VBUS1 Supply Current IDD1 (F) 6 8 mA 6 MHz logic signal rate CL=50pF
VDD2 or VBUS2 Supply Current IDD2 (F) 6 8 mA 6 MHz logic signal rate CL=50pF
Idle Current
VDD1 or VBUS1 Idle Current IDD1 (I) 1.7 2.5 mA
Input Currents IDD-, IDD+, −1 +0.1 +1 μA 0 V ≤ VDD-, VDD+, VUD+,VUD-, VSPD, VPIN,
IUD+,IUD-, VSPU, VPDEN ≤ 3.0
ISPD, IPIN, ISPU,
IPDEN
Single Ended Logic High Input Threshold VIH 2.0 V
Single Ended Logic Low Input Threshold VIL 0.8 V
Single Ended Input Hysteresis VHST 0.4 0.7V
Differential Input Sensitivity VDI 0.2 V |VXD+ - VXD-|
Differential Common Mode Voltage Range VCM 0.8 2.5 V

Logic High Output Voltages VOH 2.8 3.6 V RL=15kΩ VL=0V

Logic Low Output Voltages VOL 0 0.3 V RL=1.5kΩ VL=3.6V
VDD1 and VDD2 Supply Under Voltage Lockout VUVLO 2.5 3.0
VBUS1 and VBUS2 Supply Under Voltage Lockout VUVLOB 3.6 4.3
Transceiver capacitance CIN 10 pF UD+, UD-, DD+, DD- to ground
Capacitance Matching 10 %
Full Speed Driver Impedance ZOUTH 4 20 Ω
Impedance Matching 10 %
SWITCHING SPECIFICATIONS, I/O pins Low speed
Data Rate2 1.5 Mbps CL = 50 pF
Propagation Delay3 tPHL, tPLH 325 ns CL = 50 pF
Side 1 Output Rise/Fall Time (10% to 90%) Low tRF/tFF 75 300 ns CL = 200 pF SPD=SPU=low
Speed
Side 2 Output Rise/Fall Time (10% to 90%) Low tRF/tFF 75 300 ns CL = 450 pF SPD=SPU=low
Speed
Low Speed Differential Jitter – Next Transition |tLJN| 45 ns CL = 50 pF,
Low Speed Differential Jitter – Paired Transition |tLJP| 15 ns CL = 50 pF,
SWITCHING SPECIFICATIONS, I/O pins Full speed
Maximum Data Rate4 12 Mbps CL = 50 pF
Propagation Delay5 tPHL, tPLH 20 60 750 ns CL = 50 pF
Output Rise/Fall Time (10% to 90%) Full Speed tRL/tFL 4 20 ns CL = 50 pF SPD=SPU=high
Full Speed Differential Jitter – Next Transition |tHJN| 3 ns CL = 50 pF,
Full Speed Differential Jitter – Paired Transition |tHJP| 1 ns CL = 50 pF,
For All Operating Modes

Rev. Pr F | Page 3 of 14
ADuM4160 Preliminary Technical Data
Parameter Symbol Min Typ Max Unit Test Conditions
Common-Mode Transient Immunity |CMH| 25 35 kV/μs VUD+, VUD-, VDD+, VDD- = VDD1 or VDD2,
at Logic High Output6 VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity |CML| 25 35 kV/μs VUD+, VUD-, VDD+, VDD- = 0 V,
at Logic Low Output6 VCM = 1000 V,
transient magnitude = 800 V
1
The supply current values for the device running at a fixed continuous data rate 50% duty cycle alternating J and K states. Supply current values are specified with USB
compliant load present.
2
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
3
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.

Rev. Pr F | Page 4 of 14
Preliminary Technical Data ADuM4160
PACKAGE CHARACTERISTICS
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input to Output)1 RI-O 1012 Ω
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction-to-Case Thermal Resistance, Side 1 θJCI 33 °C/W Thermocouple located
IC Junction-to-Case Thermal Resistance, Side 2 θJCO 28 °C/W at center of package
underside
1
Device considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and
Pin 16 shorted together.
2
Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION
The ADuM4160 has been approved by the organizations listed in Table 3. Refer to Table 10 and Insulation Lifetime section for details
regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.

Table 3.
UL (Pending) CSA (Pending) VDE (Pending)
Recognized under 1577 component Approved under CSA Component Certified according to DIN V VDE V
recognition program1 Acceptance Notice #5A 0884-10 (VDE V 0884-10):2006-122
Double Protection Basic insulation per CSA 60950-1-03 and IEC 60950-1, Reinforced insulation, 846 V peak
5000 V rms isolation voltage 800 V rms (1131 V peak) maximum working voltage
Reinforced insulation per CSA 60950-1-03
and IEC 60950-1, 600 V rms (848 V peak)
maximum working voltage
Reinforced insulation per IEC 60601-1 250 V rms (353 V
peak) maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
1
In accordance with UL 1577, each ADuM4160 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).
2
In accordance with DIN V VDE V 0884-10, each ADuM4160 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 4.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 5000 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 8.0 min mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) 8.0 mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)

Rev. Pr F | Page 5 of 14
ADuM4160 Preliminary Technical Data
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval.

Table 5.
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 846 V peak
Input-to-Output Test Voltage, Method B1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, VPR 1590 V peak
partial discharge < 5 pC
Input-to-Output Test Voltage, Method A VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR
After Environmental Tests Subgroup 1 1375 V peak
After Input and/or Safety Test Subgroup 2 VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 1018 V peak
and Subgroup 3
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 6000 V peak
Safety-Limiting Values Maximum value allowed in the event of a failure
( see Figure 2)
Case Temperature TS 150 °C
Side 1 Current IS1 265 mA
Side 2 Current IS2 335 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω

350
RECOMMENDED OPERATING CONDITIONS
300
Table 6.
SAFETY-LIMITING CURRENT (mA)

250
Parameter Symbol Min Max Unit
SIDE #2 Operating Temperature TA −40 +105 °C
200 Supply Voltages1 VBUS1,VBUS2, 3.0 5.5 V
Input Signal Rise and Fall Times 1.0 ms
150
SIDE #1 1
All voltages are relative to their respective ground. See the DC Correctness
100 and Magnetic Field Immunity section for information on immunity to
external magnetic fields.
50

0
03786-004

0 50 100 150 200

CASE TEMPERATURE (°C)

Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per DIN V VDE V 0884-10

Rev. Pr F | Page 6 of 14
Preliminary Technical Data ADuM4160

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings
Table 7. may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
Parameter Rating
other conditions above those indicated in the operational
Storage Temperature (TST) −65°C to +150°C
section of this specification is not implied. Exposure to absolute
Ambient Operating Temperature (TA) −40°C to +105°C
maximum rating conditions for extended periods may affect
Supply Voltages (VBUS1, VBUS2, VDD1, −0.5 V to +6.5 V
VDD2)1 device reliability.
Input Voltage −0.5 V to VDDI + 0.5 V
(VUD+,VUD-, VSPU)1, 2
Output Voltage −0.5 V to VDDO + 0.5 V
(VDD-, VDD+, VSPD, VPIN)1, 2 ESD CAUTION
Average Output Current per Pin3
Side 1 (IO1) −10 mA to +10 mA
Side 2(IO2) −10 mA to +10 mA
Common-Mode Transients4 −100 kV/μs to +100 kV/μs
1
All voltages are relative to their respective ground.
2
VDDI , VDD2, VBUSI and VBUS2 refer to the supply voltages on the input and output
sides of a given channel, respectively..
3
See Figure 2 for maximum rated current values for various temperatures.
4
Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the Absolute Maximum Ratings may cause latch-
up or permanent damage.

Table 8. Maximum Continuous Working Voltage1

Parameter Max Unit Constraint
AC Voltage, Bipolar 565 V peak 50-year minimum lifetime
Waveform
AC Voltage, Unipolar V peak
Waveform
Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1
Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1
Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

Rev. Pr F | Page 7 of 14
ADuM4160 Preliminary Technical Data

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. ADuM4160 Pin Configuration

Table 9. ADuM4160 Pin Function Descriptions

Pin No. Mnemonic Direction Description
1 VBUS1 Power Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5V to 5.5V,
connect VBUS1 to the USB power bus. Where the isolator will be powered from a 3.3V power supply,
connect VBUS1 to VDD1 and to the external 3.3V Power Supply. Bypass to GND1 is required.
2 GND1 Return Ground 1. Ground reference for isolator Side 1.
3 VDD1 Power Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5V to 5.5V, The
VDDI pin should be used for a bypass capacitor to GND1, no other connections should be made.. Where
the isolator will be powered from a 3.3V power supply, connect VBUS1 to VDD1 and to the external 3.3V
Power Supply. Bypass to GND1 is required.
4 PDEN I Pull Down Enable, This pin is read when exiting reset. This pin shall be connected to VDD1 for standard
operation. When connected to GND1 while exiting from reset, the down stream pull down resistors are
disconnected, allowing buffer impedance measurements.
5 SPU I Speed Select Up-Stream Buffer. Active high logic input. selects Full speed slew rate and timing and logic
conventions when SPU is high. This input must be set high or low and must match pin 10.
6 UD- I/O Up-stream D-
7 UD+ I/O Up-stream D+
8 GND1 Return Ground 1. Ground reference for isolator Side 1.
9 GND2 Return Ground 2. Ground reference for isolator Side 2.
10 DD+ I/O Down-stream D+
11 DD- I/O Down-stream D-.
12 PIN I Up-stream pull-up enable. SPD controls the power connection to the pull-up for the up-stream port. It
may be tied to VDD2 for operation on power up, or tied to an external control signal for application
requiring delayed enumeration.
13 SPD I Speed Select Down-Stream Buffer. Active high logic input. selects Full speed slew rate and timing and
logic conventions when SPU is high. This input must be set high or low and must match pin 7.
14 VDD2 Power Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5V to 5.5V, The
VDDI pin should be used for a bypass capacitor to GND2, no other connections should be made.. Where
the isolator will be powered from a 3.3V power supply, connect VBUS2 to VDD2 and to the external 3.0V to
3.3V Power Supply. Bypass to GND2 is required.
15 GND2 Return Ground 2. Ground reference for isolator Side 2.
16 VBUS2 Power Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5V to 5.5V,
connect VBUS2 to the USB power bus. Where the isolator will be powered from a 3.3V power supply,
connect VBUS2 to VDD2 and to the external 3.0V to 3.3V Power Supply. Bypass to GND2 is required.

Rev. Pr F | Page 8 of 14
Preliminary Technical Data ADuM4160

Table 10. Truth Table, Control Signals and Power (Positive Logic)
VSPU VUD+, VUD- VBUS1, VDD1 VBUS2, VDD2 VDD+, VPIN VSPD Notes
Input state State State VDD- Input Input
state
H Active Powered Powered Active H H Input and output logic set for Full speed logic
convention and timing
L Active Powered Powered Active H L Input and output logic set for Low speed logic
convention and timing
L Active Powered Powered Active H H VSPU and VSPD must be set to the same value,
Mixed Speed and Logic convention is not
allowed
H Active Powered Powered Active H L VSPU and VSPD must be set to the same value,
Mixed Speed and Logic convention is not
allowed
X Z Powered Powered Z L X Upstream Side 1 presents a disconnected state
to the USB cable.
X X Unpowered Powered Z X X When Power is not present on side 1, the side 2
data output drivers will revert to High Z within
32 bit times. Side 2 initializes in high Z state.
X Z Powered Unpowered X X X When Power is not present on the VDD2, the
up-stream side will disconnect the pull-up and
disable the upstream drivers within 32 bit
times.

Rev. Pr F | Page 9 of 14
ADuM4160 Preliminary Technical Data

APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION PRODUCT USAGE
USB isolation in the D+/D- lines is challenging for several The ADuM4160 is designed to be integrated into a USB
reasons. First, access to the output enable signals is normally peripheral with an upstream facing USB port as shown in
required to control the transceiver. Some level of intelligence Figure 4. The key design points are:
must be built into the isolator to interpret the data stream and 1) The USB host provides power for the upstream side of
determine when to enable and disable its up-stream and down­ the ADuM4160 through the cable.
stream output buffers. Second, the signal must be faithfully be
reconstructed on the output side of the coupler while retaining 2) The peripheral supply provides power to the
precise timing and not passing transient states such as invalid downstream side of the ADuM4160
SE0 and SE1 states. In addition, the part must meet the low 3) The isolator interfaces with the D+/D- lines of the
power requirements of the Suspend mode. peripheral controller, so it behaves like a single port
The iCoupler technology is based on edge detection, and so hub to the peripheral.
lends itself well to the USB application. The flow of data 4) Peripheral devices have a fixed data rate that is set at
through the device is accomplished by monitoring the inputs design time. The ADuM4160 has configuration pins
for activity, and setting the direction for data transfer based on a SPU and SPD that are set by the user to match this
transition from the Idle state. Once data directionality is speed on the upstream and downstream sides of the
established, data is transferred until either an End Of Packet coupler.
(EOP), or a sufficiently long idle state is encountered. At this 5) USB enumeration begins when either the D+ or D-
point, the coupler disables its output buffers and monitors its line is pulled high at the peripheral end of the USB
inputs for the next activity cable. Control of the timing of this event is provided
During the data transfers, the input side of the coupler holds its by the PIN input on the down stream side of the
output buffers disabled. The output side enables its output coupler.
buffers and disables edge detection from the input buffers. This 6) Integrated pull-up and pull-down resistors are internal
allows the data to flow in one direction without wrapping back to the coupler.
through the coupler making the iCoupler latch. Timing is based
on the differential input signal transition. Logic is included to
eliminate any artifacts due to different input thresholds of the
differential and single ended buffers. The input state is
transferred across the isolation barrier, as one of three valid
states, J. K, or SE0. The signal is reconstructed at the output side
with a fixed time delay from the input side differential input.
The requirement for low power suspend mode is addressed by
making the Idle state power consumption lower than the
Suspend limit of 2.5mA. The iCoupler has no suspend feature
apart from a low Idle current that meets the required level.
Figure 4 TypicaADuM4160l Application
The ADuM4160 is designed to interface with an up-stream
facing Low/Full speed USB port by isolating the D+/D- lines. Other than, the delayed application of pull-up resistors, the
An upstream facing port supports only one speed of operation ADuM4160 is be transparent to USB traffic, and no
so the speed related parameters, J/K logic levels and D+/D- slew modifications to the peripheral design are required to isolate.
rate are set to match the speed of the upstream facing peripheral The isolator does add propagation delay to the signals
port (see Table 10). equivalent to a hub and cable so isolates peripherals must be
treated as if there was a built in hub when determining the
A control line on the downstream side of the ADuM4160
maximum number of hubs in a data chain.
activates the Idle state pull-up resistor. This allows the down­
stream port to control when the upstream port attaches to the POWER SUPPLY OPTIONS
USB bus. The pin can be tied to the peripheral pull-up, a In most USB transceivers, 3.3V is derived from the 5V USB bus
control line, or the Peripheral’s power supply depending on through an LDO regulator. The ADuM4160 includes an
when the initial bus connect is performed. internal LDO regulator on each side to perform this function. It
also allows the regulator to be bypassed if 3.3V is available
directly. This feature is especially useful in peripherals where
there may not be a 5V power rail. Two power input pins are

Rev. Pr F | Page 10 of 14
Preliminary Technical Data ADuM4160
present on each side, VBUSx and VDDx. If 5V is available, it is side is assumed to be unpowered or nonfunctional, in which
connected to VBUSx and the internal regulator makes 3.3V to run case the isolator output is forced to a default state (see Table 10)
the coupler. If 3.3V is available, it can be provided to both VBUSx by the watchdog timer circuit.
and VDDx. This disables the regulator and powers the coupler The limitation on the ADuM4160’s magnetic field immunity is
directly from the 3.3V supply. set by the condition in which induced voltage in the transformer’s
Figure 5, shows how a typical application is connected if the receiving coil is sufficiently large to either falsely set or reset the
upstream side of the coupler was getting power directly from decoder. The following analysis defines the conditions under
the USB bus and the downstream side was receiving 3.3V from which this may occur. The 3 V operating condition of the
the peripheral power supply. ADuM4160 is examined because it represents the most
susceptible mode of operation.
PC BOARD LAYOUT
The ADuM4160 digital isolator requires no external interface The pulses at the transformer output have an amplitude greater
circuitry for the logic interfaces. For full speed operation the than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
D+ and D- line on each side of the device require a 24Ω ±1% establishing a 0.5 V margin in which induced voltages can be
series termination resistor. These resistors are not required for tolerated. The voltage induced across the receiving coil is given by
low speed applications. Power supply bypassing is required at V = (−dβ/dt)∑∏rn2; n = 1, 2, … , N
the input and output supply pins (Figure 5). Install bypass
where:
capacitors between VBUSx and VDDx on each side of the chip. The
β is magnetic flux density (gauss).
capacitor value should have a minimum value of 0.1 μF and low
N is the number of turns in the receiving coil.
ESR. The total lead length between both ends of the capacitor
rn is the radius of the nth turn in the receiving coil (cm).
and the power supply pin should not exceed 10 mm . Bypassing
between Pin 2 and Pin 8 and between Pin 9 and Pin 15 should Given the geometry of the receiving coil in the ADuM4160 and
also be considered, unless the ground pair on each package side an imposed requirement that the induced voltage be at most
is connected close to the package. 50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 6.
100
MAXIMUM ALLOWABLE MAGNETIC FLUX

10
DENSITY (kgauss)

0.1

Figure 5. Recommended Printed Circuit Board Layout 0.01

In applications involving high common-mode transients, care

should be taken to ensure that board coupling across the isolation 0.001

03786-019
1k 10k 100k 1M 10M 100M
barrier is minimized. Furthermore, the board layout should be MAGNETIC FIELD FREQUENCY (Hz)

designed such that any coupling that does occur equally affects Figure 6. Maximum Allowable External Magnetic Flux Density
all pins on a given component side. Failure to ensure this could For example, at a magnetic field frequency of 1 MHz, the
cause voltage differentials between pins exceeding the device’s maximum allowable magnetic field of 0.2 kgauss induces a
Absolute Maximum Ratings, thereby leading to latch-up or voltage of 0.25 V at the receiving coil. This is about 50% of the
permanent damage. sensing threshold and does not cause a faulty output transition.
DC CORRECTNESS AND MAGNETIC FIELD Similarly, if such an event were to occur during a transmitted
IMMUNITY pulse (and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V—still well above the 0.5 V
Positive and negative logic transitions at the isolator input
sensing threshold of the decoder.
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, either set The preceding magnetic flux density values correspond to
or reset by the pulses, indicating input logic transitions. In the specific current magnitudes at given distances from the
absence of logic transitions at the input for more than ~1 μs, a ADuM4160 transformers. Figure 7 expresses these allowable
periodic set of refresh pulses indicative of the correct input state current magnitudes as a function of frequency for selected
are sent to ensure dc correctness at the output. If the decoder distances. As shown, the ADuM4160 is extremely immune and
receives no internal pulses of more than about 5 μs, the input can be affected only by extremely large currents operated at

Rev. Pr F | Page 11 of 14
ADuM4160 Preliminary Technical Data
high frequency very close to the component. For the 1 MHz Note that at combinations of strong magnetic field and high
example noted, one would have to place a 0.5 kA current 5 mm frequency, any loops formed by printed circuit board traces
away from the ADuM4160 to affect the component’s operation. could induce error voltages sufficiently large enough to trigger
1000 the thresholds of succeeding circuitry. Care should be taken in
DISTANCE = 1m the layout of such traces to avoid this possibility.
MAXIMUM ALLOWABLE CURRENT (kA)

100 INSULATION LIFETIME

All insulation structures will eventually break down when
10 subjected to voltage stress over a sufficiently long period. The
DISTANCE = 100mm rate of insulation degradation is dependant on the
characteristics of the voltage waveform applied across the
1
insulation. In addition to the testing performed by the
DISTANCE = 5mm
regulatory agencies, Analog Devices carries out an extensive set
0.1
of evaluations to determine the lifetime of the insulation
structure within the ADuM4160.
0.01 03786-020
ADI performs accelerated life testing using voltage levels higher
1k 10k 100k 1M 10M 100M
MAGNETIC FIELD FREQUENCY (Hz)
than the rated continuous working voltage. Acceleration factors
Figure 7. Maximum Allowable Current for several operating conditions are determined. These factors
for Various Current-to-ADuM4160 Spacings allow calculation of the time to failure at the actual working
voltage. The values shown in Table 8 summarize the peak
voltage for 50 years of service life for a bipolar ac operating
condition, and the maximum CSA/VDE approved working
voltages. In many cases, the approved working voltage is higher
than 50-year service life voltage. Operation at these high
working voltages can lead to shortened insulation life in some
cases.
The insulation lifetime of the ADuM4160 depends on the
voltage waveform type imposed across the isolation barrier. The
iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 8, Figure 9, and Figure 10 illustrate these different
isolation voltage waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines ADI’s recommended maximum working voltage.

Rev. Pr F | Page 12 of 14
Preliminary Technical Data ADuM4160
In the case of unipolar ac or dc voltage, the stress on the
insulation is significantly lower. This allows operation at higher RATED PEAK VOLTAGE
working voltages while still achieving a 50 year service life. The

05007-021
0V
working voltages listed in Table 8 can be applied while
maintaining the 50-year minimum lifetime provided the voltage Figure 8. Bipolar AC Waveform
conforms to either the unipolar ac or dc voltage cases. Any cross
insulation voltage waveform that does not conform to Figure
RATED PEAK VOLTAGE
91or Figure 10 should be treated as a bipolar ac waveform and
its peak voltage should be limited to the 50 year lifetime voltage

05007-022
value listed in Table 8. 0V

Figure 9. Unipolar AC Waveform

RATED PEAK VOLTAGE

05007-023
0V

Figure 10. DC Waveform

1
The voltage presented in figure 22 is shown as sinusoidal for illustration
purposes only. It is meant to represent any voltage waveform varying
between 0 and some limiting value. The limiting value can be positive or
negative, but the voltage cannot cross 0V.

Rev. Pr F | Page 13 of 14
Preliminary Technical Data ADuM4160

OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)

16 9
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
8
10.00 (0.3937)

1.27 (0.0500) 0.75 (0.0295)

BSC 45°
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8°
0.10 (0.0039) 0°
COPLANARITY
0.10 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
0.31 (0.0122) 0.20 (0.0079) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-013- AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

032707-B
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 11. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)
Dimension shown in millimeters and (inches)

ORDERING GUIDE
Number Number Maximum Maximum
of Inputs, of Inputs, Data Rate Propagation Maximum Temperature Package Package
Model VDD1 Side VDD2 Side (Mbps) Delay, 5 V (ns) Jitter (ns) Range Description Option
ADuM4160BRWZ 1,2 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16
EVAL-ADUM4160EBZ

1
Z = RoHS Compliant Part.
2
Specifications represent full speed buffer configuration.

©2009 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
PR08171-0-5/09(PrF)

Rev. Pr F | Page 15 of 15