REGISTER TRANSFER AND MICRO OPERATIONS

REGISTER TRANSFER LANGUAGE

A digital computer system exhibits an interconnection of digital modules such as

registers, decoders, arithmetic elements, and Control logic. These digital modules are
interconnected with some common data and control paths to form a complete digital
system.

Moreover, digital modules are best defined by the registers and the operations that are
performed on the data stored in them.The operations performed on the data stored in
registers are called Micro-operations.

The internal hardware organization of a digital system is best defined by specifying:

 The set of registers and the flow of data between them.

 The sequence of micro-operations performed on the data which are stored in
the registers.
 The control paths that initiates the sequence of micro-operation

The Register Transfer Language is the symbolic representation of notations used to

specify the sequence of micro-operations.

In a computer system, data transfer takes place between processor registers and
memory and between processor registers and input-output systems. These data transfer
can be represented by standard notations given below:

 Notations R0, R1, R2..., and so on represent processor registers.

 The addresses of memory locations are represented by names such as LOC,
PLACE, MEM, etc.
 Input-output registers are represented by names such as DATA IN, DATA OUT
and so on.
 The content of register or memory location is denoted by placing square
brackets around the name of the register or memory location.

REGISTER TRANSFERThe term Register Transfer refers to the availability of

hardware logic circuits that can perform a given micro-operation and transfer the
result of the operation to the same or another register.
Most of the standard notations used for specifying operations on various
registers are stated below.

 The memory address register is designated by MAR.

 Program Counter PC holds the next instruction's address.
 Instruction Register IR holds the instruction being executed.
 R1 (Processor Register).
 We can also indicate individual bits by placing them in parenthesis. For
instance, PC (8-15), R2 (5), etc.
 Data Transfer from one register to another register is represented in
symbolic form by means of replacement operator. For instance, the
following statement denotes a transfer of the data of register R1 into
register R2.

1. R2 ← R1
 Typically, most of the users want the transfer to occur only in a
predetermined control condition. This can be shown by following if-
then statement:
If (P=1) then (R2 ← R1); Here P is a control signal generated in the
control section.
 It is more convenient to specify a control function (P) by separating the
control variables from the register transfer operation. For instance, the
following statement defines the data transfer operation under a specific
control function (P).

1. P: R2 ← R1

The following image shows the block diagram that depicts the transfer of data
from R1 to R2.
Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs of
the register R1 are connected to the 'n' inputs of register R2.

A load input is activated by the control variable 'P' which is transferred to the
register R2.

BUS AND MEMORY TRANSFERS

A digital system composed of many registers, and paths must be provided to

transfer information from one register to another. The number of wires
connecting all of the registers will be excessive if separate lines are used between
each register and all other registers in the system.

A bus structure, on the other hand, is more efficient for transferring information
between registers in a multi-register configuration system.

A bus consists of a set of common lines, one for each bit of register, through
which binary information is transferred one at a time. Control signals determine
which register is selected by the bus during a particular register transfer.

BUS SYSTEM WITH 4 REGISTERS:

The following block diagram shows a Bus system for four registers. It is
constructed with the help of four 4 * 1 Multiplexers each having four data inputs
(0 through 3) and two selection inputs (S1 and S2).

We have used labels to make it more convenient for you to understand the
input-output configuration of a Bus system for four registers. For instance, output
1 of register A is connected to input 0 of MUX1.

The two selection lines S1 and S2 are connected to the selection inputs of all four
multiplexers. The selection lines choose the four bits of one register and transfer
them into the four-line common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of
all four multiplexers are selected and applied to the outputs that forms the bus.
This, in turn, causes the bus lines to receive the content of register A since the
outputs of this register are connected to the 0 data inputs of the multiplexers.
Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the
content provided by register B.

The following function table shows the register that is selected by the bus for
each of the four possible binary values of the Selection lines.
Note: The number of multiplexers needed to construct the bus is equal to
the number of bits in each register. The size of each multiplexer must be 'k
* 1' since it multiplexes 'k' data lines. For instance, a common bus for eight
registers of 16 bits each requires 16 multiplexers, one for each line in the
bus. Each multiplexer must have eight data input lines and three selection
lines to multiplex one significant bit in the eight registers.

A bus system can also be constructed using three-state gates instead of

multiplexers.

The three state gates can be considered as a digital circuit that has three gates,
two of which are signals equivalent to logic 1 and 0 as in a conventional gate.
However, the third gate exhibits a high-impedance state.

The most commonly used three state gates in case of the bus system is a buffer
gate.

The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-
state buffers.
  The outputs generated by the four buffers are connected to form a
single bus line.
 Only one buffer can be in active state at a given point of time.
 The control inputs to the buffers determine which of the four normal
inputs will communicate with the bus line.
 A 2 * 4 decoder ensures that no more than one control input is active at
any given point of time.

Memory Transfer

Most of the standard notations used for specifying operations on memory

transfer are stated below.

 The transfer of information from a memory unit to the user end is called
a Read operation.
 The transfer of new information to be stored in the memory is called
a Write operation.
 A memory word is designated by the letter M.
  We must specify the address of memory word while writing the memory
transfer operations.
 The address register is designated by AR and the data register by DR.
 Thus, a read operation can be stated as:
 Read: DR ← M [AR]
 The Read statement causes a transfer of information into the data
register (DR) from the memory word (M) selected by the address
register (AR).
 And the corresponding write operation can be stated as:
 Write: M [AR] ← R1
 The Write statement causes a transfer of information from register R1
into the memory word (M) selected by address register (AR).

ARITHMETIC MICRO OPERATIONS

In general, the Arithmetic Micro-operations deals with the operations performed

on numeric data stored in the registers.

The basic Arithmetic Micro-operations are classified in the following categories:

1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Shift

Some additional Arithmetic Micro-operations are classified as:

 1. Add with carry
2. Subtract with borrow
3. Transfer/Load, etc.

The following table shows the symbolic representation of various Arithmetic

Micro-operations.

Symbolic Description
Representation

R3 ← R1 + R2 The contents of R1 plus R2 are transferred to R3.

R3 ← R1 - R2 The contents of R1 minus R2 are transferred to R3.

R2 ← R2' Complement the contents of R2 (1's complement)

R2 ← R2' + 1 2's complement the contents of R2 (negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2 (subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 - 1 Decrement the contents of R1 by one

Note: The increment and decrement micro-operations are symbolized by '+

1' and '? 1' respectively. Arithmetic operations like multiply and divide are
not included in the basic set of micro-operations.

Binary Adder

The Add micro-operation requires registers that can hold the data and the digital
components that can perform the arithmetic addition.

A Binary Adder is a digital circuit that performs the arithmetic sum of two binary
numbers provided with any length.
A Binary Adder is constructed using full-adder circuits connected in series, with
the output carry from one full-adder connected to the input carry of the next full-
adder.

The following block diagram shows the interconnections of four full-adder

circuits to provide a 4-bit binary adder.

 The augend bits (A) and the addend bits (B) are designated by subscript
numbers from right to left, with subscript '0' denoting the low-order bit.
 The carry inputs starts from C0 to C3 connected in a chain through the
full-adders. C4 is the resultant output carry generated by the last full-
adder circuit.
 The output carry from each full-adder is connected to the input carry of
the next-high-order full-adder.
 The sum outputs (S0 to S3) generates the required arithmetic sum of
augend and addend bits.
 The n data bits for the A and B inputs come from different source
registers. For instance, data bits for A input comes from source register
R1 and data bits for B input comes from source register R2.
 The arithmetic sum of the data inputs of A and B can be transferred to a
third register or to one of the source registers (R1 or R2).

Binary Adder-Subtractor

The Subtraction micro-operation can be done easily by taking the 2's

compliment of addend bits and adding it to the augend bits.
Note: The 2's compliment can be obtained by taking the 1's compliment
and adding one to the least significant pair of bits. The 1's compliment can
be implemented with inverters, and one can be added to the sum through
the input carry.

The Arithmetic micro-operations like addition and subtraction can be combined

into one common circuit by including an exclusive-OR gate with each full adder.

The block diagram for a 4-bit adder-subtractor circuit can be represented as:

 When the mode input (M) is at a low logic, i.e. '0', the circuit act as an
adder and when the mode input is at a high logic, i.e. '1', the circuit act as a
subtractor.
 The exclusive-OR gate connected in series receives input M and one of the
inputs B.
 When M is at a low logic, we have B⊕ 0 = B.
The full-adders receive the value of B, the input carry is 0, and the circuit
performs A plus B.
 When M is at a high logic, we have B⊕ 1 = B' and C0 = 1.
The B inputs are complemented, and a 1 is added through the input carry.
The circuit performs the operation A plus the 2's complement of B.

Binary Incrementer
The increment micro-operation adds one binary value to the value of binary
variables stored in a register. For instance, a 4-bit register has a binary value
0110, when incremented by one the value becomes 0111.

The increment micro-operation is best implemented by a 4-bit combinational

circuit incrementer. A 4-bit combinational circuit incrementer can be represented
by the following block diagram.

 A logic-1 is applied to one of the inputs of least significant half-adder, and

the other input is connected to the least significant bit of the number to be
incremented.
 The output carry from one half-adder is connected to one of the inputs of
the next-higher-order half-adder.
 The binary incrementer circuit receives the four bits from A0 through A3,
adds one to it, and generates the incremented output in S0 through S3.
 The output carry C4 will be 1 only after incrementing binary 1111.

Note: The 4-bit binary incrementer circuit can be extended to an n-bit

binary incrementer by extending the circuit to include n half-adders. The
least significant bit must have one input connected to logic-1. The other
inputs receive the number to be incremented or the carry from the previous
stage.

Shift Micro-Operations

 
Shift micro-operations are those micro-operations that are used for the serial transfer of
information. These are also used in conjunction with arithmetic micro-operation, logic
micro-operation, and other data-processing operations. There are three types of shift
micro-operations: 1.
1. Logical Shift:
It transfers the 0 zero through the serial input. We use the symbols ‘<<‘ for the logical
left shift and ‘>>‘ for the logical right shift.
Logical Left Shift:
In this shift, one position moves each bit to the left one by one. The Empty least
significant bit (LSB) is filled with zero (i.e, the serial input), and the most significant bit
(MSB) is rejected.
The left shift operator is denoted by the double left arrow key (<<). The general syntax
for the left shift is shift-expression << k.

Logical Left Shift

Note: Every time we shift a number towards the left by 1 bit it multiplies that number by
2.
Logical Right Shift
In this shift, each bit moves to the right one by one and the least significant bit(LSB) is
rejected and the empty MSB is filled with zero.
The right shift operator is denoted by the double right arrow key (>>). The general syntax
for the right shift is “shift-expression >> k”.
 Logical Right Shift

Note: Every time we shift a number towards the right by 1 bit it divides that number by
2.
2. Arithmetic Shift:
The arithmetic shift micro-operation moves the signed binary number either to the left or
to the right position.
Following are the two ways to perform the arithmetic shift.
1. Arithmetic Left Shift
2. Arithmetic Right Shift
Arithmetic Left Shift:
In this shift, each bit is moved to the left one by one. The empty least significant bit
(LSB) is filled with zero and the most significant bit (MSB) is rejected. Same as the Left
Logical Shift.

Arithmetic Left Shift

Arithmetic Right Shift:
In this shift, each bit is moved to the right one by one and the least significant(LSB) bit is
rejected and the empty most significant bit(MSB) is filled with the value of the previous
MSB.

Arithmetic Right Shift

3. Circular Shift:
The circular shift circulates the bits in the sequence of the register around both ends
without any loss of information.
Following are the two ways to perform the circular shift.
1. Circular Shift Left
2. Circular Shift Right
Circular Left Shift:
In this micro shift operation each bit in the register is shifted to the left one by one. After
shifting, the LSB becomes empty, so the value of the MSB is filled in there.
 Circular Left Shift

Circular Right Shift:

In this micro shift operation each bit in the register is shifted to the right one by one.
After shifting, the MSB becomes empty, so the value of the LSB is filled in there.

Circular Right Shift

ARITHMETIC LOGIC SHIFT UNIT

Arithmetic Logic Shift Unit (ALSU) is a member of the Arithmetic Logic Unit
(ALU) in a computer system. It is a digital circuit that performs logical, arithmetic, and
shift operations. Rather than having individual registers calculating the micro
operations directly, the computer deploys a number of storage registers which is
connected to a common operational unit known as an arithmetic logic unit or ALU.
Now, to implement the micro operation, the contents of specified registers are allocated
in the inputs of the common Arithmetic Logic Unit. The Arithmetic Logic Unit
performs an operation that leads as a result and gets transferred to a destination register.
Arithmetic Logic Unit may be a combinatory circuit in order that the complete register
transfer operation from the supply registers through the ALU and into the destination
register is performed throughout one clock pulse amount. Sometimes, the shift micro
operations are performed in a separate unit, but sometimes it is made as a part of full
ALU.
 One stage of ALSU

We can combine and make one ALU with common selection variables by adding
arithmetic, logic, and shift circuits. We can see the, One stage of an arithmetic logic
shift unit in the diagram below. Some particular micro operations are selected through
the inputs S1 and S0.
4 x 1 multiplexer at the output chooses between associate arithmetic output between Ei
and a logic output in Hi. The data in the multiplexer are selected through inputs S3 and
S2 and the other two data inputs to the multiplexer obtain the inputs Ai – 1 for
the shr operation and Ai + 1 for the shl operation.
Note: The output carry Ci + 1 of a specified arithmetic stage must be attached to the
input carry Ci of the next stage in the sequence.
The circuit whose one stage is given in the below diagram provides 8 arithmetic
operations, 4 logic operations, and 2 shift operations, and Each operation is selected by
the 5 variables S3, S2, S1, S0, and Cin.
The below table shows the 14 operations perform by the Arithmetic Logic Unit:
1. The first 8 are arithmetic operations which are selected by S3 S2 = 00
2. The next 4 are logic operations which are selected by S3 S2 = 01
3. The last two are shift operations which are selected by S3 S2 = 10 & 11

Function table of ALSU