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TD 04 VHDL Fpga en

The document provides VHDL descriptions for various digital logic circuits including half adders, full adders, multiplexers, demultiplexers, comparators, encoders, priority encoders, and decoders. For each circuit, it gives the truth table, logic equations, schematic diagram, and VHDL code to implement the logic functions and simulate the circuit behavior.

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bendjeddou ammar
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© © All Rights Reserved
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70 views

TD 04 VHDL Fpga en

The document provides VHDL descriptions for various digital logic circuits including half adders, full adders, multiplexers, demultiplexers, comparators, encoders, priority encoders, and decoders. For each circuit, it gives the truth table, logic equations, schematic diagram, and VHDL code to implement the logic functions and simulate the circuit behavior.

Uploaded by

bendjeddou ammar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 9

M1 instrumentation University of Skikda 12/03/2023

Tutorial session: Advanced digital electronics: VHDL – FPGA


4th series: VHDL (concurrent instructions)
Give the VHDL description of the following electronic circuits:

1) Half-adder. 5) Comparator for 8-bit numbers.


2) Full-adder. 6) 4:2 encoder.
3) 4-to-1 multiplexer. 7) 4:2 priority encoder.
4) 1-to-4 demultiplexer. 8) 2:4 decoder with enable input.

Sol1) Half-adder

Truth table:

A B C (carry) S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Logic function of each output:

S = A ∙ 𝐵̅ + 𝐴̅ ∙ B = A xor B = A ⊕ B
C = A∙B
Logic circuit:

VHDL description:

Dr. A. Ganouche page 1 of 9


Sol2) Full-adder

Truth table:

Cin B A Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Logic function of each output:

S = A⋅B̅ ⋅ ̅̅̅̅̅
𝐶𝑖𝑛 + A ̅ ⋅ B ⋅ ̅̅̅̅
Cin + A̅⋅B ̅ ⋅ Cin + A ⋅ B ⋅ Cin = A ⊕ B ⊕ Cin
̅̅̅̅ + A ⋅ B
Cout = A ⋅ B ⋅ Cin ̅ ⋅ Cin + A
̅ ⋅ B ⋅ Cin + A ⋅ B ⋅ Cin = A ⋅ B + A ⋅ Cin + B ⋅ Cin

Logic circuit:

VHDL description:

Ripple-Carry Adder:

Dr. A. Ganouche page 2 of 9


Example:

Sol3) 4-to-1 multiplexer

Schematic:

Truth table:

S1 S0 Output
0 0 A
0 1 B
1 0 C
1 1 D
Logic function:

𝑜𝑢𝑡𝑝𝑢𝑡 = ̅̅̅
𝑆1 ∙ ̅̅̅
𝑆0 ∙ 𝐴 + ̅̅̅
𝑆1 ∙ 𝑆0 ∙ 𝐵 + 𝑆1 ∙ ̅̅̅
𝑆0 ∙ 𝐶 + 𝑆1 ∙ 𝑆0 ∙ 𝐷
VHDL description 01:

Dr. A. Ganouche page 3 of 9


VHDL description 02:

Sol4) 1-to-4 demultiplexer

Schematic:

Truth table:

S1 S0 A B C D
0 0 i 0 0 0
0 1 0 i 0 0
1 0 0 0 i 0
1 1 0 0 0 i
Logic function:
̅̅̅ ∙ 𝑆0
𝐴 = 𝑆1 ̅̅̅ ∙ 𝑖
̅̅̅
𝐵 = 𝑆1 ∙ 𝑆0 ∙ 𝑖
̅̅̅ ∙ 𝑖
𝐶 = 𝑆1 ∙ 𝑆0
𝐷 = 𝑆1 ∙ 𝑆0 ∙ 𝑖

Dr. A. Ganouche page 4 of 9


VHDL description:

Sol5) Comparator for 8-bit numbers

Truth table:

inputs outputs
A, B S (superior) E (equal) I (inferior)
A>B 1 0 0
A=B 0 1 0
A<B 0 0 1
VHDL description:

Dr. A. Ganouche page 5 of 9


Sol6) 4:2 encoder

Truth table:

D3 D2 D1 D0 Y1 Y0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
other cases x x
The symbol x means the value of the output is 'don't care' otherwise.

Logic function of each output (simplified by Karnaugh map):

Y0 = D1 + D3

Y1 = D2 + D3

Schematic:

VHDL description (conditional assignment):

Dr. A. Ganouche page 6 of 9


VHDL description (selective assignment):

Sol7) 4:2 priority encoder

Truth table:

E3 E2 E1 E0 S1 S0
1 x x x 1 1
0 1 x x 1 0
0 0 1 x 0 1
0 0 0 1 0 0
Other cases x x
VHDL description (conditional assignment):

Dr. A. Ganouche page 7 of 9


VHDL description (selective assignment):

Sol8) 2:4 decoder with an active-high enable input

Schematic:

Truth table:

D1 D0 EN Y3 Y2 Y1 Y0
x x 0 0 0 0 0
0 0 1 0 0 0 1
0 1 1 0 0 1 0
1 0 1 0 1 0 0
1 1 1 1 0 0 0
Logic function of each output:

𝑌0 = ̅̅̅̅
𝐷1 ∙ ̅̅̅̅
𝐷0 ∙ 𝐸𝑁
̅̅̅̅ ∙ 𝐷0 ∙ 𝐸𝑁
𝑌1 = 𝐷1
𝑌2 = 𝐷1 ∙ ̅̅̅̅
𝐷0 ∙ 𝐸𝑁
𝑌3 = 𝐷1 ∙ 𝐷0 ∙ 𝐸𝑁

Dr. A. Ganouche page 8 of 9


VHDL description:

Timing diagram (ModelSim):

Dr. A. Ganouche page 9 of 9

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