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This document contains the VHDL code for a finite state machine (FSM) with 4 states: idle_st, x1_st, x2_st, and dv_st. The FSM responds to primary inputs s1_i, s2_i, and dne_i to transition between states and set outputs en_o, cl_o, and dv_o accordingly. Some details of the circuit need to be modified to achieve the required performance.

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katuwalnawaraj76
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25 views

Untitled Document

This document contains the VHDL code for a finite state machine (FSM) with 4 states: idle_st, x1_st, x2_st, and dv_st. The FSM responds to primary inputs s1_i, s2_i, and dne_i to transition between states and set outputs en_o, cl_o, and dv_o accordingly. Some details of the circuit need to be modified to achieve the required performance.

Uploaded by

katuwalnawaraj76
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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filename: fsm0.

vhd, last modified: 2024-0115


-- --------------------------------------------------------------------
-- some GHDL-cmds: ghdl -s xxx.vhd : Syntax check
-- ghdl -a xxx.vhd : Assembles file xxx.vhd
-- ghdl -e xyz : Elaborates xyz, no packages
-- prepare waveform: ghdl -r xxx_TB1 --wave=xxx_TB1_wave.ghw
-- --------------------------------------------------------------------
-- ATTENTION ====> some details must be changed to get the required
-- performance of the circuit.
-- --------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- --------------------------------------------------------------------
ENTITY fsm0 IS
PORT (rb_i,cp_i: IN STD_LOGIC; -- Primary Input, reset, active low
s1_i : IN STD_LOGIC; -- Primary Inputs, s1, Start
s2_i : IN STD_LOGIC; -- Primary Inputs, s2, Stop
dne_i : IN STD_LOGIC; -- from Serial Output, all done
en_o : OUT STD_LOGIC; -- enable counter
cl_o : OUT STD_LOGIC; -- clear counter
dv_o : OUT STD_LOGIC); -- to uat, data valid
END fsm0;
-- --------------------------------------------------------------------
-- --------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.top_pack.ALL;
-- --------------------------------------------------------------------
-- --------------------------------------------------------------------
ARCHITECTURE ar1 OF fsm0 IS
-- -- +------------+
TYPE state_name IS (idle_st,x1_st,x2_st,dv_st); -- ! !
SIGNAL now_st : state_name; -- !rb_i !
SIGNAL nxt_st : state_name; -- !cp_i !
-- ----------------------------------------------------- ! !
BEGIN -- !s1_i en_o!
-- ----------------------------------------------------- !s2_i cl_o!
clkd: PROCESS (rb_i,cp_i) -- !dne_i dv_o!
BEGIN -- ! !
IF (rb_i='0') THEN now_st <= idle_st; -- +------------+
ELSIF (cp_i'EVENT AND cp_i='1') THEN now_st <= nxt_st;
END IF;
END PROCESS clkd;
-- --------------------------------------------------------------------
st_trans: PROCESS (now_st,s1_i,s2_i,dne_i)
BEGIN
nxt_st <= idle_st;
CASE now_st IS

WHEN idle_st => IF (s1_i ='1') THEN nxt_st <= x1_st; --


s1=01..,start
ELSE nxt_st <= idle_st; -- s1=00..,wait
END IF;

WHEN x1_st => IF (s2_i ='1') THEN nxt_st <= dv_st; --


s2=01..,stop
ELSE nxt_st <= x1_st; --
s2=00..,wait
END IF;
WHEN dv_st => nxt_st <= x2_st; -- trigger
uat

WHEN x2_st => IF (dne_i='1') THEN nxt_st <= idle_st; -- all done?
ELSE nxt_st <= x2_st; -- no, more
to go
END IF;
END CASE;
END PROCESS st_trans;
-- --------------------------------------------------------------------
ausgabe : PROCESS (now_st)
BEGIN
CASE now_st IS
WHEN idle_st => cl_o <= '1'; en_o <= '0'; dv_o <= '0';
WHEN x1_st => cl_o <= '0'; en_o <= '1'; dv_o <= '0';
WHEN dv_st => cl_o <= '0'; en_o <= '0'; dv_o <= '1';
WHEN x2_st => cl_o <= '0'; en_o <= '0'; dv_o <= '0';
END CASE;
END PROCESS ausgabe;
-- --------------------------------------------------------------------
END ar1;

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