KARNATAK LAW SOCIETY’S

GOGTE INSTITUTE OF TECHNOLOGY

UDYAMBAG, BELAGAVI-590008
(An Autonomous Institution under Visvesvaraya Technological University, Belagavi)
(APPROVED BY AICTE, NEW DELHI)
Department of Electronic and Communication

PROJECT REPORT
On

LINEAR FEEDBACK SHIFT REGISTER

Submitted by
Smriti Dandagi – 2GI21EC142

Under the guidance of

Prof. Suresh Kuri
2022 – 2023

GUIDE SIGNATURE
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Institute Vision

KLS Gogte Institute of Technology shall stand out as an institution of excellence in

technical education and in training individuals for outstanding caliber, character
coupled with creativity and entrepreneurial skills.

Mission

To train the students to become quality engineers with high standards of

professionalism and ethics who have positive attitude, a perfect blend of
techno-managerial skills and problem-solving ability with an analytical and
innovative mindset.

Department Vision:

The Electronic and Communication Engineering Department shall impart quality

technical education and entrepreneurship skills to develop creative individuals to
face changing global scenario.

Mission:

To augment the national talent pool, with electronics and communication engineers
having all-encompassing technical knowledge, principled practices and
nationalistic practices.
KARNATAK LAW SOCIETY’S

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GOGTE INSTITUTE OF TECHNOLOGY

UDYAMBAG, BELAGAVI-590008
(An Autonomous Institution under Visvesvaraya Technological University, Belagavi)
(APPROVED BY AICTE, NEW DELHI)

Department of Electronics and Communication

Certificate of Completion
This is to certify that Smriti Dandagi with USN. 2GI21EC142 has successfully completed the
course on Digital Systems as a student of KLS GIT in the field of Electronics and
Communication. Students has displayed a strong aptitude for the subject and has demonstrated
excellent understanding and knowledge of the key concepts and principles related to digital
systems.

Their active participation in class discussions, group projects and assignments have shown their
dedication and commitment to the subject. It is my pleasure to recognize students achievements
in this subject and to award this certificate of completion..
The report has been approved as it satisfies the academic requirements in respect of subject
prescribed for the said Degree.

Signature of the Guide Signature of the HOD Signature of the Principal

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ABSTRACT

The basic idea of this project is to implement a low transition Linear Feedback Shift Register that
creates test patterns with more better correlation between the abutting bits. The improved
correlation between the abutting bits of test patterns decreases the changing activity in the
circuit. The decreased changing activity results in low power dissolution. Back then, the biggest
concerns of the VLSI designer were area, execution, expense and consistency; power
consideration was just of only least value. Lately, however, this has started to change and,
increasingly, power is being provided approximate value to area and speed considerations. Many
elements have put up with this trend. Hence the main driving factor has been the significant
success and extension of the class of personal computing devices (audio- and video-based
multimedia products and portable desktops) and wireless communications systems (personal
digital assistants and personal communicators) which demand high-speed computation and
complex functionality with low power consumption.

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INDEX

SI No. Chapters Page

No.
1 Introduction 06
2 Literature survey 07
3 Objective and problem statement 09
4 Methodology 10
5 Design and implementation 12
6 Result and analysis 13
7 Outcomes 14
8 Conclusion and scope of the work 15

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1. INTRODUCTION:
In computing, a linear-feedback shift register (LFSR) is a shift register whose input bit is
a linear function of its previous state.

The most commonly used linear function of single bits is exclusive-or (XOR). Thus, an LFSR is
most often a shift register whose input bit is driven by the XOR of some bits of the overall shift
register value.

The initial value of the LFSR is called the seed, and because the operation of the register is
deterministic, the stream of values produced by the register is completely determined by its
current (or previous) state. Likewise, because the register has a finite number of possible states, it
must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback
function can produce a sequence of bits that appears random and has a very long cycle.

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2. LITERATURE SURVEY:
LFSR stands for Linear Feedback Shift Register and it is a design that is useful inside of FPGAs.
LFSRs are simple to synthesize, meaning that they take relatively few resources and can be run
at very high clock rates inside of an FPGA. There are many applications that benefit from using
an LFSR including:

 Counters

 Test Pattern Generators

 Data Scrambling

 Cryptography

Uses in cryptography
LFSRs have long been used as pseudo-random number generators for use in stream ciphers, due
to the ease of construction from simple electromechanical or electronic circuits, long periods,
and very uniformly distributed output streams. However, an LFSR is a linear system, leading to
fairly easy cryptanalysis. For example, given a stretch of known plaintext and corresponding
ciphertext, an attacker can intercept and recover a stretch of LFSR output stream used in the
system described, and from that stretch of the output stream can construct an LFSR of minimal
size that simulates the intended receiver by using the Berlekamp-Massey algorithm. This LFSR
can then be fed the intercepted stretch of output stream to recover the remaining plaintext.

Three general methods are employed to reduce this problem in LFSR-based stream ciphers:

 Non-linear combination of several bits from the LFSR state;

 Non-linear combination of the output bits of two or more LFSRs (see also: shrinking
generator); or using Evolutionary algorithm to introduce non-linearity.[13]
 Irregular clocking of the LFSR, as in the alternating step generator.

Important LFSR-based stream ciphers include A5/1 and A5/2, used in GSM cell phones, E0,
used in Bluetooth, and the shrinking generator. The A5/2 cipher has been broken and both A5/1
and E0 have serious weaknesses.[14][15]

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The linear feedback shift register has a strong relationship to linear congruential generators.[16]

LFSRs are used in circuit testing for test-pattern generation (for exhaustive testing, pseudo-
random testing or pseudo-exhaustive testing) and for signature analysis.

Test-pattern generation

Complete LFSR are commonly used as pattern generators for exhaustive testing, since they cover
all possible inputs for an n-input circuit. Maximal-length LFSRs and weighted LFSRs are widely
used as pseudo-random test-pattern generators for pseudo-random test applications.

To prevent short repeating sequences (e.g., runs of 0s or 1s) from forming spectral lines that may
complicate symbol tracking at the receiver or interfere with other transmissions, the data bit
sequence is combined with the output of a linear-feedback register before modulation and
transmission. This scrambling is removed at the receiver after demodulation. When the LFSR
runs at the same bit rate as the transmitted symbol stream, this technique is referred to
as scrambling. When the LFSR runs considerably faster than the symbol stream, the LFSR-
generated bit sequence is called chipping code. The chipping code is combined with the data
using exclusive or before transmitting using binary phase-shift keying or a similar modulation
method. The resulting signal has a higher bandwidth than the data, and therefore this is a method
of spread-spectrum communication. When used only for the spread-spectrum property, this
technique is called direct-sequence spread spectrum; when used to distinguish several signals
transmitted in the same channel at the same time and frequency, it is called code-division
multiple access.

Neither scheme should be confused with encryption or encipherment; scrambling and spreading
with LFSRs do not protect the information from eavesdropping. They are instead used to
produce equivalent streams that possess convenient engineering properties to allow robust and
efficient modulation and demodulation.

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3. OBECTIVE AND PROBLEM STATEMENT:

LFSRs can be implemented in hardware, and this makes them useful in applications that
require very fast generation of a pseudo-random sequence, such as direct-sequence spread
spectrum radio. LFSRs have also been used for generating an approximation of white noise in
various programmable sound generators.

To prevent short repeating sequences (e.g., runs of 0s or 1s) from forming spectral lines
that may complicate symbol tracking at the receiver or interfere with other transmissions, the
data bit sequence is combined with the output of a linear-feedback register before modulation
and transmission. This scrambling is removed at the receiver after demodulation. When the
LFSR runs at the same bit rate as the transmitted symbol stream, this technique is referred to
as scrambling. When the LFSR runs considerably faster than the symbol stream, the LFSR-
generated bit sequence is called chipping code. The chipping code is combined with the data
using exclusive or before transmitting using binary phase-shift keying or a similar modulation
method. The resulting signal has a higher bandwidth than the data, and therefore this is a method
of spread-spectrum communication. When used only for the spread-spectrum property, this
technique is called direct-sequence spread spectrum; when used to distinguish several signals
transmitted in the same channel at the same time and frequency, it is called code-division
multiple access.

Neither scheme should be confused with encryption or encipherment; scrambling and spreading
with LFSRs do not protect the information from eavesdropping. They are instead used to
produce equivalent streams that possess convenient engineering properties to allow robust and
efficient modulation and demodulation.

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4. METHODOLOGY:

The linear feedback shift register is implemented as a series of Flip-Flops inside of an FPGA that
are wired together as a shift register. Several taps off of the shift register chain are used as inputs
to either an XOR or XNOR gate. The output of this gate is then used as feedback to the
beginning of the shift register chain, hence the Feedback in LFSR.

5-Bit LFSR using XNOR gates

FIGURE 4.1

When an LFSR is running, the pattern that is being generated by the individual Flip-Flops is
pseudo-random, meaning that it’s close to random. It’s not completely random because from any
state of the LFSR pattern, you can predict the next state. There are a few properties of shift
registers that are important to note:

 LFSR patterns are pseudo-random.

 Output patterns are deterministic. You can figure out the next state by knowing the
position of the XOR gates as well as the current pattern.

 A pattern of all 0’s cannot appear when the taps use XOR gates. Since 0 XORed with 0
will always produce 0, the LFSR will stop running.

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 A pattern of all 1’s cannot appear when the taps use XNOR gates. Since 1 XNORed with
1 will always produce 1, the LFSR will stop running.

 The maximum possible number of iterations of any LFSR = 2Bits-1

TIMING DIAGRAM:

The figure below shows the timing diagram of the Linear Feedback Shift Register when the test
bench is applied to the source code.

FIGURE 4.2

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5. DESIGN & IMPLEMENTATION:

(One to Many & Many to One)

Consider the case of an 8-bit LFSR, for which the minimum number of taps that will generate a
maximal-length sequence is four. In the real world, XOR gates only have two inputs, so a four-
input XOR function has to be created using three XOR gates arranged as two levels of logic.
Even in those cases where an LFSR does support a minimum of two taps, you may actually wish
to use a greater number of taps such as eight (which would result in three levels of XOR logic).

The problem is that increasing the levels of logic in the combinational feedback path can
negatively impact the maximum clocking frequency of the function. One solution is to transpose
the many-to-one implementations discussed above into their one-to-many counterparts.

The traditional many-to-one implementation for the eight-bit LFSR has taps at [7,3,2,1]. To
convert this into its one-to-many counterpart, the most-significant tap (which is always the most
significant bit) is fed back directly into the least significant bit, and is also individually XORed
with the other original taps (bits [3,2,1] in this example). Note that although both styles result in
maximal-length LFSRs, the actual sequences of values will differ between them. But the main
point is that using the one-to-many style means that there is never more than one level of
combinational logic in the feedback path, irrespective of the number of taps being employed.

6. RESULT & ANALYSIS:

The Linear Feedback Shift Register is coded using the hardware description
language, Verilog. Spartan 6 trainer kit is shown.

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Longer LFSRs will take longer to run through all iterations. The longest possible number of
iterations for an LFSR of N-bits is 2 N-1. If you think about it, all possible patterns of something
that is N-bits long is 2N. Therefore there is only one pattern that cannot be expressed using an
LFSR. That pattern is all 0’s when using XOR gates, or all 1’s when using XNOR gates as your
feedback gate.

The VHDL and Verilog code creates any N-Bit wide LFSR that you desire. It uses polynomials
(which is the math behind the LFSR) to create the maximum possible LFSR length for each bit
width. Therefore, for 3 bits, it takes 23-1=7 clocks to run through all possible combinations, for 4
bits: 24-1=15, for 5 bits: 25-1=31, etc. I based this on an XNOR implementation to allow the
FPGA to start up in an all-zero state on the LFSR.

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7. OUTCOME:

FIGURE 7.1

Spartan-6 trainer kit

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This shows the FPGA implementation of LFSR. Using Xilinx ISE tool, this code is dumped into
Spartan-6 FPGA trainer kit.

8. Conclusion & Scope of work:

Here by this point we already know that since the Linear Feedback Shift Register is used
in many applications such as counters, data scrambling etc. W can clearly see here that the
through LFSR, we have implemented a counter on the fpga board.

The repeating sequence of states of an LFSR allows it to be used as a clock divider or as a

counter when a non-binary sequence is acceptable, as is often the case where computer index or
framing locations need to be machine-readable.[12] LFSR counters have simpler feedback logic
than natural binary counters or Gray-code counters, and therefore can operate at higher clock
rates. However, it is necessary to ensure that the LFSR never enters an all-zeros state, for
example by presetting it at start-up to any other state in the sequence. The table of primitive
polynomials shows how LFSRs can be arranged in Fibonacci or Galois form to give maximal
periods. One can obtain any other period by adding to an LFSR that has a longer period some
logic that shortens the sequence by skipping some states.

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References:
[1] K.M.L Sai Indrani and P. Ramesh, “A Study on the Performance of an AWGN Channel in a
Communication System,” International Journal of Electronics & Communication Technology,
Vol. 4, Issue 2, pp. 89–90, June 2013.
[2] ” How ITU’s Broadband Standards Improve Access to the Internet,” [online] available at
http://www.itu.int/osg/spu/ip/chapter_seven.html [accessed, June, 2017]
[3] N. Vlajic, “Digital Transmission of Digital Data: Line and Block Coding, Digital
Transmission Modes,” course material, 2010.
[4] N. Jiping, Z. Yongchuan, H. Zhihua， and Y. Zuqiao, “A Digital Image Scrambling Method
Based on AES and Error-correcting Code,” International Conference on Computer Science and
Software Engineering., pp. 677–680, 2008.
[5] Rohith S., K. N. H. Bhat, and A. N. Sharma, “Image Encryption and Decryption using
Chaotic Key Sequence Generated by Sequence of Logistic Map and Sequence of States of Linear
Feedback Shift Register,” International Conference on Advance in Electronics, Computers and
Communications, 2014.

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Appendix:
Code:

`timescal
e 1ns /
1ps

// Generate 1Hz output from 100MHz input

// For LFSR demonstration purposes

module oneHz_gen(
input clk_100MHz,
input reset,
output clk_1Hz
);

reg [25:0] r_count = 0;

reg r_1Hz = 0;

always @(posedge clk_100MHz or posedge reset)

if(reset)
r_count <= 26'b0;
else
if(r_count == 49_999_999) begin
r_count <= 26'b0;
r_1Hz <= ~r_1Hz;
end

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else
r_count <= r_count + 1;

assign clk_1Hz = r_1Hz;

endmodule

Testbench:
module
lfsr4(
input clk,
input reset,
output reg [3:0] lfsr = 4'b0
);

always @(posedge clk or posedge

reset)
if(reset)
lfsr <= 4'b0;
else begin
lfsr[3:1] <= lfsr[2:0];
lfsr[0] <= lfsr[3] ~^
lfsr[0];
end

Endmodule

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