Advanced VLSI Design Memory CMPE 640

Memory
Can be categorized into:
• Read Write Memory (RWM)
• Random Access Memory (RAM): static SRAM (faster) verses dynamic
DRAM (smaller) structures possible. Access time independent of
physical location of data.
• Non-RAM: Serial Access Memory (FIFO, LIFO, Shift register) and Con-
tent Access Memory (CAM). Non-uniform access time.
• Non-volatile Read Write Memory (NVRWM): write time much larger than
read time.
• EPROM, E2PROM, FLASH
• Read Only Memory (ROM)

A second classification for RAMs and ROMs:

• Static-load: no clock required.
• Synchronous: require a clock edge to enable memory operation.
• Asynchronous: recognize address changes and output new data. More
difficult to build.

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Advanced VLSI Design Memory CMPE 640

Memory Architecture
In order to build an N-word memory where each word is M bits wide (typi-
cally 1, 4 or 8 bits), a straightforward approach is to stack memory:

A word is selected by setting exactly

S0
Word 0 one of the select bits, Sx, high.
S1
Word 1
S2 Storage cell
Word 2
N words

This approach works well for small

memories but has problems for large
SN-2 memories.
Word N-2
SN-1 For example, to build a 1Mword
Word N-1 (where word = 8 bits) memory, requires
1M select lines, provided by some
off-chip device.
Input-Output
(M bits)

This approach is not practical.

What can we do?

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Advanced VLSI Design Memory CMPE 640

Memory Architecture
Add a decoder to solve the package problem:
S0
Binary encoded address
Word 0
S1
A0 Word 1
S2 Storage cell
A1 Word 2

Decoder
A2
This reduces the
AK-1 number of external
SN-2 address pins from
Word N-2 1M to 20.
SN-1
Word N-1
K = log2N

one-hot Input-Output
(M bits)
This does not address the memory aspect ratio problem:
The memory is 128,000 time higher than wide (220/23) !
Besides the bizarre shape factor, the design is extremely slow since the ver-
tical wires are VERY long (delay is at least linear to length).

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Advanced VLSI Design Memory CMPE 640

Memory Architecture
The vertical and horizontal dimensions are usually very similar, for an aspect
ratio of unity.
Multiple words are stored in each row and selected simultaneously:
Row address = S0 Bit line
AK to AL-1 S1 Storage cell
AK S2
Row Decoder
AK+1
AK+2 Word line

AL-1
SN-2
SN-1

Column address =
A0 to AK-1 A0
Column decoder Sense amps
AK-1 and drivers
not shown
A column decoder is added to
select the desired word from a row. Input-Output
(M bits)

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Advanced VLSI Design Memory CMPE 640

Memory Architecture
This strategy works well for memories up to 64 Kbits to 256 Kbits.
Larger memories start to suffer excess delay along bit and word lines.
A third dimension is added to the address space to solve this problem:
Block 0 Block i Block P-1

Row
Address

Column
Address
Block
Block selector
Address

Global Data bus 4 Mbit: P = 32 blocks with

Global 128Kbits/block.
Address: [Row][Block][Col] amplifier/driver 128Kbit block: 1024 rows
I/O and 128 columns.

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Advanced VLSI Design Memory CMPE 640

Memory: Architecture
An example:
2m+k bits
Ak
Row decoder
Ak+1
Row decoder
2n-k
Row decoder bits
An-1
Row decoder
A0
Column decoder column mux, sense amp, write buffers
Ak-1
[An-1..Ak][Ak-1..A0]

For example: Let N = 1,048,576 and M = 8 bits for a 1 million byte memory.
n = log2N = 20, k = 8 and m = log2M = 3.
Then there are 2n-k rows = 212 = 4096 and 2k+m columns/23 bits per word = 28
= 256 words.

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Advanced VLSI Design Memory CMPE 640

ROM
ROM cells are permanently fixed: Several possibilities:
BL BL BL
WL WL WL
1

psuedo n-MOS
BL NOR gate.
WL WL
WL BL
0
Resistance of
n/p should be
at least 4.
Diode supplies current BJT supplies current p-MOS used to hold
to raise BL (bitline) for to raise BL for each BL high. n-MOS
all cells on the row. cell on the row. Requires provides pull-down
VDD to be routed. path.

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Advanced VLSI Design Memory CMPE 640

Non-volatile Read-Write Memories

Virtually identical in structure to ROMs.
Selective enabling/disabling of transistors is accomplished through modifi-
cations to threshold voltage. This is accomplished through a floating gate.
20V
Source Drain
Gate
-5V after
Floating Gate tox
programming
this device off - - - - - - - -
tox 20V
n+ - n+
Substrate
Applying a high voltage (15 to 20 V) between source and gate-drain create
high electric field and causes avalanche injection to occur.
Hot electrons traverse first oxide and get trapped on floating gate, leaving it
negatively charged.
This increases the threshold voltage to ~7V. Applying 5V to the gate does not
permit the device to turn on.

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Advanced VLSI Design Memory CMPE 640

Non-volatile Read-Write Memories

The method of erasing is the main differentiating factor between the various
classes of reprogrammable nonvolatile memories.

• EPROM:
UV light renders oxide slightly conductive.
Erase is slow (seconds to several minutes).
Programming is slow (5-10 microsecs per word).
Limited number of programming cycles - about 1000.
Very dense - single transistor functions as both the programming and
access device.

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Advanced VLSI Design Memory CMPE 640

Non-volatile Read-Write Memories

• EEPROM or E2PROM:
Very thin oxide allows electrons to flow to and from the gate via Fowler-
Nordheim tunneling with VGD applied.
Erasure is achieved by reversing the voltage applied during writing.
Source Drain
Gate
tox 10V
Floating Gate
- - - - - - - -
tox

n+ thin tunneling ox n+
Substrate
BL
WL Threshold control becomes a problem:
Removing too much charge results in a
VDD depletion device that cannot be turned off.
Remedy: Add an access transistor.

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Advanced VLSI Design Memory CMPE 640

Non-volatile Read-Write Memories

• Flash EEPROM:
Combines density adv. of EPROM with versatility of EEPROM.
Uses avalanche hot-electron-injection approach to program.
Erasure performed using Fowler-Nordheim tunneling.
Monitoring control hardware checks the value of the threshold during
erasure - making sure the unprogrammed transistor remains an
enhancement device.
Source 12V Drain
Gate

12V tox 12V

Floating Gate
erasure - - - - - - - -
thin tunneling ox

n+ - - programming n+
Substrate
Programming performed by applying 12V to gate and drain.
Erasure performed with gate grounded and source at 12V.

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Advanced VLSI Design Memory CMPE 640

Read-Write Memories (RAM)

SRAM:

VDD

word line

bit bit

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Advanced VLSI Design Memory CMPE 640

Read-Write Memories (RAM)

Generic RAM circuit:

Bit Line clocks

Conditioning
bit bit

RAM cell
row decoder
n-1;k
word line

column decoder
k-1;0 Sense Amp
Column Mux
Write Buffers
Address
read-data write-data

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Advanced VLSI Design Memory CMPE 640

Read-Write Memories (RAM)

SRAM: Read Operation
Precharging bit and bit_bar to 5V before enabling the word line
improves performance.
To optimize speed,
use n-channels as
precharge devices.

bit precharge bit

precharge

VDD bit, bit

word

word
data

data

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Advanced VLSI Design Memory CMPE 640

Read-Write Memories (RAM)

SRAM: Write Operation:

N5 N6
0 write-data

write

cell
N3 cell Pbit N4 word
1->0 0->1
word
bit, bit
bit bit

write N1 cell, cell

N2

write-data Zero stored in cell originally.

1 Nd, N1, and N3 have to pull Pbit below
Nd the inverter threshold.

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Advanced VLSI Design Memory CMPE 640

Read-Write Memories (RAM)

Register files:

Single-write-port, double-read-port
Overpowers 2/2
weak feedback
4/1
inverter
2/3 4/1
4/1
4/1 Adv: No
matter
4/1 what the
2/1
load, cell
cannot be
decode
addr<3:0> 8/1 Biased toward flipped.
VSS to help write.

write-data read-data0 read-data1

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Advanced VLSI Design Memory CMPE 640

Read-Write Memories (RAM)

DRAM:
Refresh: Compensate for charge loss by periodically rewriting the cell
contents.
Read followed by a write operation.
Typical refresh cycles occur every 1 to 4 milliseconds.
4 transistor DRAM created by simply eliminating the p tree in an SRAM cell.

word line

bit bit

Logic 1 values are, of course, a threshold below VDD.

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Advanced VLSI Design Memory CMPE 640

Read-Write Memories (RAM)

3T DRAM:

write
X
Note that this read
cell is inverting
X
write
read bit1
bit1 bit2
bit2 is either clamped to VDD or VDD-VT
is precharged to either VDD or VDD-VT. bit2
V
No device ratioing necessary here !
Most common method of refresh is to read bit2, place its inverse on bit1 and
assert write.
Precharge method of ’setting’ bit2 is preferred (no steady-state current).
Memory structure of choice in ASICs because of its relative simplicity in both
design and operation.

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Advanced VLSI Design Memory CMPE 640

Read-Write Memories (RAM)

1T DRAM
write read
bit
word-line
VDD-VT
X X
Cx Cbit
VDD
V bit
Vpre = VDD/2
word-line
sensing

Cx
V = Vbit - Vpre = (Vx - Vpre)
(Cx + Cbit)
During read operation, charge redistribution occurs between node X and
node bit.
Cx is typically 1 or 2 orders of magnitude smaller than Cbit so the delta-V
value is typically 250 mV.

Most pervasive DRAM cell in commercial memory design.

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Advanced VLSI Design Memory CMPE 640

Read-Write Memories (RAM)

1T DRAM observations:
• Amplification of delta-V (through a sense amplifier) is necessary in order
for the cell to be functional.
Other cell designs used sense amps only to speed up the read operation.
• The read-out operation is destructive ! Output of sense amp is imposed
onto the bit line with word-line high during read-out.
Sense amp activated V(1)

Vpre

V(0)
Word-line activated
• 1T transistor requires an explicit capacitor (3T used gate capacitance).
Capacitance must be large (~30fF) but area small - key challenge in design.
• Bootstrapping word-line to a value larger than VDD circumvents VT loss on
storage capacitor.

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Advanced VLSI Design Memory CMPE 640

Read-Write Memories (RAM)

Content Access Memory (CAM):
Determines if a match exists between a data word with a stored word.
Used in Translation-look-aside buffers.
bit bit
VDD
Match is 0 if ANY SRAM cell
has bit/cell or bit/cell
equal to 1.

word line
SRAM
with extra Each bit of the word
n-channels cell cell
is tied to the match line.
to implement
XOR function. match
Dynamic or Pseudo n-MOS
implementations possible.

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