UNIT -3 [Processor Internal Organization

Registers
Input

Arithmetic and
Memory
Logic Unit

Output
Control

I/O Processor / CPU

• Input: accepts coded information from human operators.
• Memory: stores the received information for later use.
• Processor: executes the instructions of a program stored in the memory.
• Output: reacts to the outside world.
• Control: coordinates all these actions.
1
Main Components of a Processor

Register file: a
memory unit for the Control circuitry:
Control
processor’s general- Register Interpret or decode the
purpose registers circuitry fetched instruction
file
(GPRs)

IR: Hold the instruction

until its execution is
IR completed
(special purpose register)
Arithmetic and Logic Instruction
Unit (ALU): Perform address
ALU PC: Keep track of the
an arithmetic or logic generator address of the next
operation
instruction to be fetched
PC and executed
(special purpose register)

Processor–memory interface

Processor-memory interface: Allow the

communication between processor and memory
Processor Internal: Internal Bus
Internal processor
bus Control
signals
• Internal Processor Bus: PC
…
– ALU, control circuitry, and Address
Instruction
decoder
lines
all the registers are MAR &
External control logic
interconnected via a memory
single common bus. bus
MDR
Data IR
The bus is internal to the lines
processor (i.e., only visible to Y R0
the processor). Constant 4 R1

Select MUX R2
R3
Add
ALU A B

…
Sub
ALU
…

lines Rn-1
Carry
XOR in

Z TEMP
Processor Internal: External Bus (1/2)
• External Memory Bus: Internal processor
bus Control
– Processor-memory signals
…
PC
interface: External Instruction
Address
memory bus are lines
decoder
&
MAR
controlled through External output input control logic
memory
MAR and MDR. bus
MDR
Data IR
– MAR: Specify the lines

requested memory Constant 4

Y R0
R1
address
Select MUX R2
• Input: Address is
R3
specified by processor via Add
ALU A B

…
Sub
internal processor bus. control ALU
…

• Output: Address is send lines Carry Rn-1

XOR in
to the memory via
external memory bus. Z TEMP
Processor Internal: External Bus (2/2)
• External Memory Bus: Internal processor
bus Control
– MDR: Keep the content signals
…
PC
of the requested Instruction
Address
memory address lines
decoder
&
MAR
• There are two inputs and External control logic
memory two two
two outputs for MDR. bus outputs inputs
MDR
• Inputs: Data may be Data IR
lines
placed into MDR either
Y R0
– From the internal Constant 4 R1
processor bus or
Select MUX R2
– From the external
memory bus. R3
Add
ALU A B

…
Sub
• Outputs: Data stored in control ALU
…

MDR may be loaded lines Carry Rn-1

XOR in
from either bus.
Z TEMP
Processor Internal: Register (1/2)
• General-Purpose Internal processor
bus Control
Registers: signals
…
PC
– R0 through Rn-1 Address
Instruction
decoder
• n varies from one lines
MAR &
processor to another. External control logic
memory
bus
MDR
• Special Registers: Data
lines
IR

– Program Counter Y R0
Constant 4
• Keep track of the address R1
of the next instruction to Select MUX R2
be fetched and executed. R3
Add
ALU A B
– Instruction Register

…
Sub
control ALU
…

lines Rn-1
• Hold the instruction until XOR
Carry
in
the current execution is
Z TEMP
completed.
Processor Internal: Register (2/2)
• Special Registers: Internal processor
bus Control
Y, Z, & TEMP signals
…
PC
– Transparent to the Address
Instruction
decoder
programmer. lines
MAR &
External control logic
– Used by the processor memory
bus
for temporary storage Data
MDR
IR
during execution of lines

some instructions. Y R0
Constant 4 R1
– Never used for storing R2
Select MUX
data generated by one R3
Add
instruction for later use ALU A B

…
Sub
control
by another instruction. ALU
…

lines Carry Rn-1

XOR in
– We will discuss their
Z TEMP
Processor Internal Organization
• Arithmetic and Logic Internal processor
bus Control
Unit (ALU): signals
…
PC
– Perform arithmetic or Address
Instruction
decoder
logic operation lines
MAR &
External control logic
Z = A operator B memory
bus
• Two inputs A and B Data
MDR
IR
• One output to register Z lines
Y R0

• Multiplexer (MUX): Constant 4 R1

Select MUX R2
– The input A of ALU: R3
Select (ctrl line) either ALU
Add
A B

…
Sub
• The output of register Y orcontrol ALU
…

lines Carry Rn-1

• A constant value 4 (for XOR in

incrementing PC). Z TEMP

Processor Internal: Control Circuitry
• Instruction decoder: Internal processor
bus Control
– Interpret the fetched signals
…
PC
instruction stored in the Instruction
Address
IR register. lines
decoder
&
MAR
External control logic
• Control logic: memory
bus
MDR
Data
– Issue control signals to lines
IR

control the all the units Y R0

inside the processor. Constant 4 R1

• E.g., ALU control lines, Select MUX R2

select-signal for MUX, Add

R3
carry-in for ALU, etc. ALU A B

…
Sub
control ALU
…

– Interact with the lines

XOR
Carry Rn-1
in
external memory bus.
Z TEMP
Outline
• Processor Internal Structure
• Instruction Execution
– Fetch Phase
– Execute Phase

• Execution of A Complete Instruction

• Multiple-Bus Organization
Instruction Execution (1/3)
1) Fetch Phase Internal processor
bus Control
– IR  [[PC]] signals
…
PC
• Fetch the contents of the Instruction
Address
memory location pointed lines
decoder
&
to by PC, and load into IR External MAR
control logic
memory
– PC  [PC]+4 bus
MDR
• Increment the contents of Data IR
lines
PC by 4.
Y R0
– Why 4? Instruction is 32 Constant 4 R1
bits (4B) and memory is
byte addressable. Select MUX R2
R3
2) Execute Phase ALU
Add
A B

…
Sub
control ALU
– Decode instruction in IR
…

lines Rn-1
Carry
XOR in
– Perform the operation(s)
Z TEMP
Instruction Execution (2/3)
1) Fetch Phase Internal processor
bus Control
– IR  [[PC]] signals
…
PC
• Fetch the contents of the Instruction
Address
memory location pointed lines
decoder
&
to by PC, and load into IR External MAR
control logic
memory
– PC  [PC]+4 bus
MDR
• Increment the contents of Data IR
lines
PC by 4.
Y R0
– Why 4? Instruction is 32 Constant 4 R1
bits (4B) and memory is
byte addressable. Select MUX R2
R3
2) Execute Phase ALU
Add
A B

…
Sub
control ALU
– Decode instruction in IR
…

lines Rn-1
Carry
XOR in
– Perform the operation(s)
Z TEMP
Instruction Execution (3/3)
1) Fetch Phase Internal processor
bus Control
– IR  [[PC]] signals
…
PC
• Fetch the contents of the Instruction
Address
memory location pointed lines
decoder
&
to by PC, and load into IR External MAR
control logic
memory
– PC  [PC]+4 bus
MDR
• Increment the contents of Data IR
lines
PC by 4.
Y R0
– Why 4? Instruction is 32 Constant 4 R1
bits (4B) and memory is
byte addressable. Select MUX R2
R3
2) Execute Phase ALU
Add
A B

…
Sub
control ALU
– Decode instruction in IR
…

lines Rn-1
Carry
XOR in
– Perform the operation(s)
Z TEMP
Instruction Execution: Execute Phase
• An instruction can be executed by performing one
or more of the following operation(s):
1) Transfer data from a register to another
register or to the ALU
1) Perform arithmetic (or logic) operations
and store the result into the special register Z
2) Load content of a memory location to a register
3) Store content of a register to a memory location
1) Register Transfer
• Input and output of Internal processor
bus Control
register Ri are controlled signals
…
PC
by switches ( ): Address
Instruction
decoder
– Ri-in: Allow data to be lines
MAR &
External control logic
transferred into Ri memory
bus
MDR
Data IR
Ri-in lines
Y R0
Ri Constant 4 R1

Select MUX R2
Ri-out R3
Add
ALU A B

…
Sub
– Ri-out: Allow data to be control ALU
…

lines Rn-1
Carry
transferred out from Ri XOR in

Z TEMP
1) Register Transfer (Cont’d)
Internal processor
bus Control
signals
• Ex: R3  R1 PC
…
Instruction
Address
decoder
lines &
MAR
External control logic
memory
Sequence of Steps: bus
Data
MDR
IR
lines
Y R0
R1-out, R3-in Constant 4 R1

Select MUX R2
R3
Add
ALU A B

…
Sub
control ALU
…

lines Rn-1
Carry
XOR in

Z TEMP
2) Arithmetic or Logic Operation
• ALU: A circuit without Internal processor
bus Control
storage to manipulate data. signals
…
PC
– Two inputs: from A & B Address
Instruction
decoder
• A: #4 or register Y lines
MAR &
External control logic
• B: Any other register memory
– ALU: Perform operation bus
Data
MDR
IR
– One output: to register Z lines
Y R0
• Ex: R3  R1 + R2 Constant 4 R1

Sequence of Steps: Select MUX R2

R3
Add
 R1-out, Y-in ALU A B

…
Sub
control ALU
…

Rn-1
 Select-Y, R2-out, lines
XOR
Carry
in

Add, Z-in Z TEMP

Z-out,
 Lec09:
CSCI2510 R3-in Unit
Basic Processing
2) Arithmetic or Logic Operation (Cont’d)
• Ex: R3  R1 + R2

 R1-out, Y-in  Select-Y  Z-out, R3-in

R2-out, Add,
Z-in
Question:
CSCI2510 Why
Lec09: Basic to first
Processing Unit transfer R1 to the special register Y?24
3) Fetching a Word from Memory

• Data transferring takes place through MAR and MDR.

– MAR: Memory Address Register
– MDR: Memory Data Register
k-bit
Processor address bus Memory
(byte-addressable)
MAR Up to 2k addressable
memory locations
n-bit
data bus (unit: word)
MDR Word length = n bits

Control lines
( R /W, MFC, etc.)
*MFC (Memory Function Completed): Indicating the
requested operation has been completed.
3) Fetching a Word from Memory (Cont’d)

• MAR: Memory Address

Register MAR-in
– Uni-directional bus (). MAR
– Connect to the external
address lines directly.
External
memory bus
(address lines)

• MDR: Memory Data MDR-outE MDR-out

Register
– Bi-directional bus (). MDR
– MDR connections to both
internal and external MDR-inE MDR-in
buses are all controlled External Internal
by switches ( ). memory bus
(data lines)
processor bus
3) Fetching a Word from Memory (Cont’d)
•Ex: Mov R2, (R1) Internal processor
bus Control
PC signals
…
R/W
Sequence of Steps: MFC
(Control lines) Instruction
decoder
External &
MAR
1. R1-out, memory
bus
Addr
lines
control logic

MAR-in, MDR
Data IR
Read (start to load a lines

word from memory) Y R0

Constant 4 R1
2. MDR-inE, Select MUX R2

WaitMFC (wait until the Add

A B
R3
ALU

…
Sub
loading is completed) control ALU
…

lines Rn-1
Carry

3. MDR-out, XOR in

Z TEMP
R2-in
3) Fetching a Word from Memory (Cont’d)

• Timing Sequence: Step 1 2 3

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
1. R1-out (not shown), Clock

MAR-in, MAR in

Read (start to read

a word from memory) Address Address bits appear on Address Bus (MAR content)

=== assume memory Read

read takes 3 cycles === Memory

2. MDR-inE, Read
(MR)

WaitMFC (wait MDR inE

until the loading is Data Data bits

completed)
MFC

3. MDR-out,
R2-in (not shown) MDR out
4) Storing Word to Memory
• This operation is similar Internal processor
bus Control
to the previous one. PC signals
…
• Ex: Mov (R1), R2 R/W
MFC
(Control lines) Instruction
decoder
External
Sequence of Steps: memory Addr
MAR &
control logic
bus lines
 R1-out, MDR
Data
MAR-in lines
IR

Y R0

 R2-out, MDR-in, Constant 4 R1

Write (start to store a Select MUX R2

R3
word into memory) ALU
Add
A B

…
Sub
control ALU
…

Rn-1
 MDR-outE, lines
XOR
Carry
in

WaitMFC (wait until the Z TEMP

storing is completed)
Revisit: Fetch Phase
• Fetch Phase: The first phase of Internal processor
bus Control
machine instruction execution signals
…
PC
– IR  [[PC]] Address
Instruction
decoder
• Fetch the instruction lines
MAR &
from the memory External control logic
memory
location pointed to by PC, bus
MDR
and load it into IR Data IR
lines
– PC  [PC]+4 Y R0
• Increment the contents Constant 4 R1
of PC by 4 Select MUX R2

• What is the sequences Add

A B
R3
ALU

…
Sub
of steps for the fetch control ALU
…

lines Rn-1
Carry
phase with the highest XOR in

parallelism? Z TEMP
Fetch Phase (Step - 1)
•Ex: Fetch Phase Internal processor
bus Control
Sequence of Steps: PC signals
…
R/W
 PC-out, MAR-in, Read MFC
(Control lines) Instruction
decoder
External
Select-4, Add, Zin memory Addr
MAR &
control logic
bus lines
Fetch the instruction MDR
IR
– Increment PC in parallel
Y R0
 MDR-inE, WaitMFC Constant 4 R1

Z-out, PC-in, Y-in Select MUX R2

R3
– Y-in is for branch ALU
Add
A B

…
Sub
(discuss later). control ALU
…

lines Rn-1
Carry
XOR in

 MDR-out, IR-in Z TEMP

Fetch Phase (Step - 2)
•Ex: Fetch Phase Internal processor
bus Control
Sequence of Steps: PC signals
…
R/W
 PC-out, MAR-in, Read MFC
(Control lines) Instruction
decoder
External
Select-4, B-in, memory Addr
MAR &
control logic
bus
Z-in, Add lines
MDR
– Fetch the instruction IR

– Increment PC in parallel. Y R0
Constant 4 R1
 MDR-inE, WaitMFC Select MUX R2
Z-out, PC-in, Y-in Add
R3
ALU A B
– Y-in is for branch

…
Sub
control ALU
…

Rn-1
(discuss later). lines
XOR
Carry
in

 MDR-out, IR-in Z TEMP

Fetch Phase (Step - 3)
•Ex: Fetch Phase Internal processor
bus Control
Sequence of Steps: PC signals
…
R/W
 PC-out, MAR-in, Read MFC
(Control lines) Instruction
decoder
External
Select-4, B-in, memory Addr
MAR &
control logic
bus
Z-in, Add lines
MDR
– Fetch the instruction IR

– Increment PC in parallel. Y R0
Constant 4 R1
 MDR-inE, WaitMFC Select MUX R2
Z-out, PC-in, Y-in Add
R3
ALU A B
– Y-in is for branch

…
Sub
control ALU
…

Rn-1
(discuss later). lines
XOR
Carry
in

 MDR-out, IR-in Z TEMP

Observations and Insights
• The internal processor bus and the external memory
bus can be operated independently (concurrently).
– Since the separation provided by MAR and MDR.

• Independent operations imply the possibility of

performing some steps in parallel.
– E.g., memory access and PC increment, instruction
decoding and reading source register

• During memory access, processor waits for MFC.

– There is NOTHING TO DO BUT WAIT for few cycles.

CSCI2510 Lec09: Basic Processing Unit 41

Outline
• Processor Internal Structure
• Instruction Execution
– Fetch Phase
– Execute Phase

• Execution of A Complete Instruction

• Multiple-Bus Organization
Example 1) ADD R1, (R3)
• Execution of a Complete Instruction:
Sequence of Steps:
1) Fetch the instruction Fetch:
1. PC-out, MAR-in, Read
2) Decode the instruction
Select-4, B-in, Z-in, Add
3) Load the operand [R3]
2. MDR-inE, WaitMFC Z-out,
from memory
PC-in, Y-in
4) Perform the addition
5) Store the result to R1 3. MDR-out, IR-in
Decode:
Execution:
4. R3-out, MAR-in, Read
5. R1-out, Y-in, MDR-inE, WaitMFC
6. MDR-out, SelectY, Add, Z-in,
7. Z-out, R1-in, End
Example 1) ADD R1, (R3) (2/3)
Sequence of Steps: Internal processor
bus Control
1. PC-out, MAR-in, Read PC signals
…
Select-4, B-in, Z-in, Add R/W
(Control lines) Instruction
MFC decoder
2. MDR-inE, WaitMFC External
MAR &
memory Addr control logic
Z-out, PC-in, Y-in bus lines
3. MDR-out, IR-in MDR
IR
4. R3-out, MAR-in, Read
Y R0
5. R1-out, Y-in, MDR-inE, Constant 4 R1
WaitMFC Select MUX R2

6. MDR-out, SelectY, Add, Add

R3
ALU A B
Z-in, B-in

…
Sub
control ALU
…

lines Rn-1
7. Z-out, R1-in XOR
Carry
in

Z TEMP
Example 1) ADD R1, (R3) (3/3)
• Detailed Explanation for Sequence of Steps:
 PC loaded into MAR, read request to memory,
MUX selects 4, added to PC (B-in) in ALU, store sum in Z
 Z moved to PC (and Y) while waiting for memory
 Word fetched from memory and loaded into IR
 Instruction Decoding: Figure out what the instruction
should do and set control circuitry for steps 4 – 7
 R3 transferred to MAR, read request to memory
 Content of R1 moved to Y while waiting for memory
 Read operation completed, the loaded word is already in
MDR and copied to B-in of ALU, SelectY as second input
of ALU, add performed
 Result is transferred to R1