Synchronous Counters,

ripple counter & other

counters
Lecture 2

Dronacharya Group of Institutions

Introduction: Counters
 Counters are circuits that cycle through a specified
number of states.
 Two types of counters:
 synchronous (parallel) counters
 asynchronous (ripple) counters

 Ripple counters allow some flip-flop outputs to be

used as a source of clock for other flip-flops.
 Synchronous counters apply the same clock to all
flip-flops.
Synchronous (Parallel) Counters
 Synchronous (parallel) counters: the flip-flops are
clocked at the same time by a common clock pulse.
 We can design these counters using the sequential
logic design process (covered in Lecture #12).
 Example: 2-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J,K inputs).
Present Next Flip-flop
state state inputs
00 01 A1 A0 A1+ A0+ TA1 TA0
0 0 0 1 0 1
11 10 0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1
Synchronous (Parallel) Counters
 Example: 2-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J,K inputs).
Present Next Flip-flop
state state inputs
A1 A0 A1+ A0+ TA1 TA0 TA1 = A0
0 0 0 1 0 1
0 1 1 0 1 1 TA0 = 1
1 0 1 1 0 1
1 1 0 0 1 1

A0 J A1
J Q Q
C C
Q' K Q'
K

CLK
Synchronous (Parallel) Counters
 Example: 3-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J, K inputs).
Present Next Flip-flop
state state inputs
A 2 A1 A0 A2+ A1+ A0+ TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
A1 A1 A1

1 1 1 1 1 1 1
A2 1 A2 1 1 A2 1 1 1 1

A0 A0 A0
TA2 = A1.A0 TA1 = A0 TA0 = 1
Synchronous (Parallel) Counters
 Example: 3-bit synchronous binary counter (cont’d).
TA2 = A1.A0 TA1 = A0 TA0 = 1

A2 A1 A0

Q Q Q
J K J K J K
CP
1
Synchronous (Parallel) Counters
 Note that in a binary counter, the nth bit (shown
underlined) is always complemented whenever
011…11  100…00
or 111…11  000…00
 Hence, Xn is complemented whenever
Xn-1Xn-2 ... X1X0 = 11…11.
 As a result, if T flip-flops are used, then
TXn = Xn-1 . Xn-2 . ... . X1 . X0
Synchronous (Parallel) Counters
 Example: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1

1 A1.A0 A2.A1.A0

A0 J A1 J A2 J A3
J Q Q Q Q
C C C C
Q' K Q' K Q' K Q'
K

CLK
Synchronous (Parallel) Counters
 Example: Synchronous decade/BCD counter.
Clock pulse Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 0 0 0 1 T0 = 1
2 0 0 1 0
3 0 0 1 1 T1 = Q3'.Q0
4 0 1 0 0
5 0 1 0 1 T2 = Q1.Q0
6 0 1 1 0
7 0 1 1 1 T3 = Q2.Q1.Q0 + Q3.Q0
8 1 0 0 0
9 1 0 0 1
10 (recycle) 0 0 0 0
Synchronous (Parallel) Counters
 Example: Synchronous decade/BCD counter
(cont’d).
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0

Q0

1 T T Q1 T Q2 T Q3
Q Q Q Q
C C C C
Q' Q' Q' Q'

CLK
Up/Down Synchronous Counters
 Up/down synchronous counter: a bidirectional
counter that is capable of counting either up or
down.
 An input (control) line Up/Down (or simply Up)
specifies the direction of counting.
 Up/Down = 1  Count upward
 Up/Down = 0  Count downward
Up/Down Synchronous Counters
 Example: A 3-bit up/down synchronous binary
counter.
Clock pulse Up Q2 Q1 Q0 Down
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

TQ0 = 1 Up counter Down counter

TQ1 = (Q0.Up) + (Q0'.Up' ) TQ0 = 1 TQ0 = 1
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' ) TQ1 = Q0 TQ1 = Q0’
TQ2 = Q0.Q1 TQ2 = Q0’.Q1’
Up/Down Synchronous Counters
 Example: A 3-bit up/down synchronous binary
counter (cont’d).
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )

Q0 Q1

1 T T T Q2
Q Q Q
Up C C C
Q' Q' Q'

CLK
Designing Synchronous Counters
 Covered in Lecture #12. 000
100 001
 Example: A 3-bit Gray code
101 011
counter (using JK flip-flops).
111 010
110
Present Next Flip-flop
state state inputs
Q2 Q1 Q0 Q2+ Q1+ Q0+ JQ2 KQ2 JQ1 KQ1 JQ0 KQ0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 1 0 X 1 X X 0
0 1 0 1 1 0 1 X X 0 0 X
0 1 1 0 1 0 0 X X 0 X 1
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 1 0 0 X 0 0 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 1 X 0 X 1 X 0
Designing Synchronous Counters
 3-bit Gray code counter: flip-flop inputs.

Q1Q0 Q1Q0 Q1Q0

Q2 Q2 00 01 11 10 Q2 00 01 11 10
00 01 11 10
0 0 1 X X 0 1 X X
1
1 X X X X 1 X X 1 X X 1

JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = Q2.Q1 + Q2'.Q1'

= (Q2  Q1)'
Q1Q0 Q1Q0 Q1Q0
Q2 00 01 11 10 Q2 00 01 11 10 Q2 00 01 11 10
0 X X X X 0 X X 0 X 1 X
1 1 1 X X 1 1 X 1 X
KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2.Q1' + Q2'.Q1
= Q2  Q1
Designing Synchronous Counters
 3-bit Gray code counter: logic diagram.
JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = (Q2  Q1)'
KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2  Q1

Q0 Q1 Q2
J Q J Q J Q
C C C
Q1 Q2
K Q' K Q' ' K Q' '
Q0
'
CLK
Decoding A Counter
 Decoding a counter involves determining which state
in the sequence the counter is in.
 Differentiate between active-HIGH and active-LOW
decoding.
 Active-HIGH decoding: output HIGH if the counter is
in the state concerned.
 Active-LOW decoding: output LOW if the counter is
in the state concerned.
Decoding A Counter
 Example: MOD-8 ripple counter (active-HIGH
decoding).
0 1 2 3 4 5 6 7 8 9 10
Clock
A' HIGH only on
B' count of ABC = 000
C'
A' HIGH only on
B' count of ABC = 001
C
A' HIGH only on
B count of ABC = 010
C'
.
.
.
A HIGH only on
B count of ABC = 111
C
Decoding A Counter
 Example: To detect that a MOD-8 counter is in state
0 (000) or state 1 (001).
A'
B' 0 1 2 3 4 5 6 7 8 9 10
C' Clock
A'
B'
C A' HIGH only on
B' count of ABC = 000
or ABC = 001

 Example: To detect that a MOD-8 counter is in the

odd states (states 1, 3, 5 or 7), simply use C.
0 1 2 3 4 5 6 7 8 9 10
Clock
HIGH only on count
C of odd states
Ring Counters
 One flip-flop (stage) for each state in the sequence.
 The output of the last stage is connected to the D
input of the first stage.
 An n-bit ring counter cycles through n states.
 No decoding gates are required, as there is an output
that corresponds to every state the counter is in.
Ring Counters
 Example: A 6-bit (MOD-6) ring counter.
PRE
Q0 Q1 Q2 Q3 Q4 Q5
D Q D Q D Q D Q D Q D Q

CLR
CLK

Clock Q0 Q1 Q2 Q3 Q4 Q5 100000
0 1 0 0 0 0 0
000001 010000
1 0 1 0 0 0 0
2 0 0 1 0 0 0
3 0 0 0 1 0 0 000010 001000
4 0 0 0 0 1 0
5 0 0 0 0 0 1 000100
Johnson Counters
 The complement of the output of the last stage is
connected back to the D input of the first stage.
 Also called the twisted-ring counter.
 Require fewer flip-flops than ring counters but more
flip-flops than binary counters.
 An n-bit Johnson counter cycles through 2n states.
 Require more decoding circuitry than ring counter
but less than binary counters.
Johnson Counters
 Example: A 4-bit (MOD-8) Johnson counter.
Q0 Q1 Q2
D Q D Q D Q D Q
Q'
Q3'
CLR
CLK

Clock Q0 Q1 Q2 Q3 0000
0 0 0 0 0
0001 1000
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0 0011 1100
4 1 1 1 1
5 0 1 1 1 0111 1110
6 0 0 1 1
7 0 0 0 1 1111
Johnson Counters
 Decoding logic for a 4-bit Johnson counter.
Clock A B C D Decoding A'
0 0 0 0 0 A'.D' State 0
D'
1 1 0 0 0 A.B'
2 1 1 0 0 B.C' A
3 1 1 1 0 C.D' State 1
B'
4 1 1 1 1 A.D
5 0 1 1 1 A'.B B
State 2
6 0 0 1 1 B'.C C'
7 0 0 0 1 C'.D
C
State 3
D'
B' A
State 6 State 4
C D
C' A'
State 7 State 5
D B