Digital Design - Computer

Architecture
디지털 설계 - 컴퓨터구조
Combinational Circuits
Lecture 2

Brian J. d’Auriol

Lecture Notes developed by Brian J. d’Auriol, permission to use material granted for non-profit, academic use, provided credit is explicitly given; all other use must request prior permission from the author.
Acknowledgements
• Lecture Notes developed by Brian J. d’Auriol, permission to use
material granted for non-profit, academic use, provided credit is
explicitly given; all other use must request prior permission from the
author.

• Presentation contains additional copyrighted images used herein for

purposes of academic teaching; all such copyrighted material retains
the original copyright terms.

Slide 2
Processor Operation Requirements
Computer Processor //Author: Brian J. d'Auriol
operations components //Date: Sept. 9, 2011
#include <stdio.h>
#define F "%-13.13s %4.4s %4d\n"
Int a=3, b=5 int main(void){
unsigned short int a = 3; // bit pattern: 011
bit-wise AND a & b 1 unsigned short int b = 5; // bit pattern: 101
bit-wise OR a | b 7 printf("Integer operations\n");
addition a + b 8 ALU printf("a=%d, b=%d\n",a,b);
printf(F, "bit-wise AND", "a&b", a&b);
subtraction a - b -2 printf(F, "bit-wise OR", "a|b", a|b);
comparison a < b 1 printf(F, "addition", "a+b", a+b);
printf(F, "subtraction", "a-b", a-b);
equality a == b 0 ALU post-operation printf(F, "comparison", "a<b", a<b);
right shift b >> 1 2 Shift unit, shift register
printf(F, "equality",
printf(F, "right shift",
"a==b", a==b);
"b>>1", b>>1);
Multiplication a * b 15 printf(F, "multiplication", "a*b", a*b);
multiplier printf(F, "division", "a/b", a/b);
division a / b 0 }

What are the processor components that are

used to perform these operations?

Slide 3
Simplified Computer Basic Component
Organization
basic circuit ALU multipler
adder
mux

Shift register FPU Central

Processing
register Unit
(CU)

decoder register file

sequential circuit controller

Slide 4
 4 x 1Multiplexer
A
What is the truth table for this circuit?
B
Data Result
path
S T RESULT
C
0 0
D 0 1
Control path: control 1 0
signals control devices
and selects data path 1 1
S
T
Control
path
Slide 5
 4 x 1 Multiplexer
A
What is the truth table for this circuit?
B
Data Result
path
S T RESULT
C
0 0
D 0 1
Control path: control 1 0
signals control devices
and selects data path 1 1
0 S
0 T

Control
path
Slide 6
 4 x 1 Multiplexer
A
What is the truth table for this circuit?
B
Data Result
path
S T RESULT
C
0 0 A
D 0 1
Control path: control 1 0
signals control devices
and selects data path 1 1
0 S
0 T

Control
path
Slide 7
 4 x 1 Multiplexer
A
What is the truth table for this circuit?
B
Data Result
path
S T RESULT
C
0 0 A
D 0 1
Control path: control 1 0
signals control devices
and selects data path 1 1
S
T
Control
path
Slide 8
 4 x 1 Multiplexer
A
S T What is the truth table for this circuit?
B
Data Result
path S T S T RESULT
C
ST
0 0 A
D 0 1 B
ST
Control path: control 1 0 C
signals control devices
and selects data path 1 1 D
S
T Result = S’T’A + S’TB + ST’C + STD

Control
path
Slide 9
 4 x 1 Multiplexer
A
S T
B
S T S T RESULT
C
ST
0 0 A
always @ (x) begin
case (x[5:4]) D 0 1 B
2'b00 : y <= x[3:3];
ST
2'b01 : y <= x[2:2];
2'b10 : y <= x[1:1];
1 0 C
2'b11 : y <= x[0:0];
endcase
1 1 D
end
S
T

Slide 10
 Crossbar Mux Switching
Crossbar switch: all inputs can be
connected to all outputs, one-to-one,
but once a connection is made, that
input and output cannot be again
connected. Used in processor and
data communication switches.

2 2 2 2
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

Slide 11
 Crossbar Mux Switching
Crossbar switch: all inputs can be
connected to all outputs, one-to-one,
but once a connection is made, that
input and output cannot be again
connected. Used in processor and
data communication switches.

2 2 2 2
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

Slide 12
 Encoded
Decoder
(e.g. minterm form)
x1 x0

A
X1 X0 A B C D
B 0 0 1 0 0 0
0 1 0 1 0 0
C
1 0 0 0 1 0

D 1 1 0 0 0 1

Slide 13
1 0
Decoder
x1 x0

A
X1 X0 A B C D
B 0 0 1 0 0 0
0 1 0 1 0 0
C
1 0 0 0 1 0

D 1 1 0 0 0 1

Slide 14
Decoder Circuit Example 1
(canonical circuit implementation)
0 a
A 1 b
B 2 c
3 d
2-4 decoder

y1 (AB) = Σ(0,2) y0 (AB) =Σ(1,3)

Input Decoder outputs Function

variables outputs
A B a b c d y1 y0
0 0 1 0 0 0 1 0

0 1 0 1 0 0 0 1
1 0 0 0 1 0 1 0

1 1 0 0 0 1 0 1 Slide 15
Decoder Circuit Example 1
(canonical circuit implementation)
0 a
A 1 b
B 2 c
3 d
2-4 decoder

y1 (ab) = Σ(0,2) y0 (a,b) =Σ(1,3)

Input Decoder outputs Function

variables outputs
A B a b c d y1 y0
0 0 1 0 0 0 1 0

0 1 0 1 0 0 0 1
1 0 0 0 1 0 1 0

1 1 0 0 0 1 0 1 Slide 16
Decoder

Symbol often means a ‘buffer’, often used for electrical purposes.

Slide 17
Decoder

Slide 18
Simple 4-2 Encoder
A
x A B C D x y
B
0 0 0 1 0 0
C y 0 0 1 0 0 1
Pre-condition: A + B + C + D = 1 0 1 0 0 1 0
(addition) 1 0 0 0 1 1

Slide 19
 Full adder
co1 coo CarryIn (Ci0)=0

a2 a1 a0 a0
+ 1-bit adder Plus Sum0 (s0)
b2 b1 b0 b0

s2 s1 s0 CarryOut (Co0)

CarryIn (Ci0)
1 1
a1
1-bit adder Plus Sum1 (s1)
0 1 1 3 b1
+
0 0 1 +1 CarryOut (Ci0)
1 0 0 4
Slide 20
 Full adder
Inputs Outputs
1-bit adder a b Ci Co Sum Comments
CarryIn (Ci0)
0 0 0
a0 0 0 1
Plus Sum0 (s0)
b0 0 1 0
0 1 1
CarryOut (Co0)
1 0 0
1 0 1
1 1 0
1 1 1
Slide 21
 Full adder
Inputs Outputs
1-bit adder a b Ci Co Sum Comments
CarryIn (Ci0)
0 0 0 0 0 0+0+0=0
a0 0 0 1
Plus Sum0 (s0)
b0 0 1 0
0 1 1
CarryOut (Co0)
1 0 0
1 0 1
1 1 0
1 1 1
Slide 22
 Full adder
Inputs Outputs
1-bit adder a b Ci Co Sum Comments
CarryIn (Ci0)
0 0 0 0 0 0+0+0=0
a0 0 0 1 0 1 0+0+1=1
Plus Sum0 (s0)
b0 0 1 0 0 1 0+1+0=1
0 1 1
CarryOut (Co0)
1 0 0 0 1 1+0+0=1
1 0 1
1 1 0
1 1 1
Slide 23
 Full adder
Inputs Outputs
1-bit adder a b Ci Co Sum Comments
CarryIn (Ci0)
0 0 0 0 0 0+0+0=0
a0 0 0 1 0 1 0+0+1=1
Plus Sum0 (s0)
b0 0 1 0 0 1 0+1+0=1
0 1 1 1 0 0+1+1=2
CarryOut (Co0)
1 0 0 0 1 1+0+0=1
1 0 1 1 0 1+0+1=2
1 1 0 1 0 1+1+0=2
1 1 1
Slide 24
 Full adder
Inputs Outputs
1-bit adder a b Ci Co Sum Comments
CarryIn (Ci0)
0 0 0 0 0 0+0+0=0
a0 0 0 1 0 1 0+0+1=1
Plus Sum0 (s0)
b0 0 1 0 0 1 0+1+0=1
0 1 1 1 0 0+1+1=2
CarryOut (Co0)
1 0 0 0 1 1+0+0=1
1 0 1 1 0 1+0+1=2
1 1 0 1 0 1+1+0=2
1 1 1 1 1 1+1+1=3
Slide 25
 Full adder
Inputs Outputs
1-bit adder a b Ci Co Sum Comments
CarryIn (Ci0)
0 0 0 0 0 0+0+0=0
a0 0 0 1 0 1 0+0+1=1
Plus Sum0 (s0)
b0 0 1 0 0 1 0+1+0=1
0 1 1 1 0 0+1+1=2
CarryOut (Co0)
1 0 0 0 1 1+0+0=1
1 0 1 1 0 1+0+1=2
1 1 0 1 0 1+1+0=2
1 1 1 1 1 1+1+1=3
Slide 26
 Full adder
Inputs Outputs
1-bit adder a b Ci Co Sum Comments
CarryIn (Ci0)
0 0 0 0 0 0+0+0=0
a0 0 0 1 0 1 0+0+1=1
Plus Sum0 (s0)
b0 0 1 0 0 1 0+1+0=1
0 1 1 1 0 0+1+1=2
CarryOut (Co0)
1 0 0 0 1 1+0+0=1
Co=∑(3,5,6,7) 1 0 1 1 0 1+0+1=2
Co = a’ b Ci + a b’ Ci + 1 1 0 1 0 1+1+0=2
a b Ci’ + a b Ci 1 1 1 1 1 1+1+1=3
Slide 27
 Full adder
Inputs Outputs
1-bit adder a b Ci Co Sum Comments
CarryIn (Ci0)
0 0 0 0 0 0+0+0=0
a0 0 0 1 0 1 0+0+1=1
Plus Sum0 (s0)
b0 0 1 0 0 1 0+1+0=1
0 1 1 1 0 0+1+1=2
CarryOut (Co0)
1 0 0 0 1 1+0+0=1
1 0 1 1 0 1+0+1=2
1 1 0 1 0 1+1+0=2
1 1 1 1 1 1+1+1=3
Slide 28
 Full adder
Inputs Outputs
1-bit adder a b Ci Co Sum Comments
CarryIn (Ci0)
0 0 0 0 0 0+0+0=0
a0 0 0 1 0 1 0+0+1=1
Plus Sum0 (s0)
b0 0 1 0 0 1 0+1+0=1
0 1 1 1 0 0+1+1=2
CarryOut (Co0)
1 0 0 0 1 1+0+0=1
s =∑(1,2,4,7) 1 0 1 1 0 1+0+1=2
s = a’ b’ Ci + a’ b Ci' + 1 1 0 1 0 1+1+0=2
a b’ Ci’ + a b Ci 1 1 1 1 1 1+1+1=3
Slide 29
 Full adder implementation
SoP (Canonical)
a
circuit version
b
c
3

5
Co=∑(3,5,6,7) Co

6
Co = a’ b Ci + a b’ Ci +
a b Ci’ + a b Ci 7

2
s =∑(1,2,4,7) S

4
s = a’ b’ Ci + a’ b Ci' +
a b’ Ci’ + a b Ci 7
Slide 30
 Full adder implementation
(decoder version)

0
Co=∑(3,5,6,7) 1 S
a
2
Co = a’ b Ci + a b’ Ci +

3-8 decoder
3
a b Ci’ + a b Ci b
4
c 5 Co

s =∑(1,2,4,7) 7

s = a’ b’ Ci + a’ b Ci' +
a b’ Ci’ + a b Ci
Slide 31
 Full adder implementation
(standard circuit)
Co = a’ b Ci + a b’ Ci + a b Ci’ + a b Ci
Ci(a’b + a b’)+ a b (Ci’ + Ci)
1-bit adder Ci(a + b)+ a b
CarryIn (Ci0) s = a’ b’ Ci + a’ b Ci' + a b’ Ci’ + a b Ci
a0
Sum0 (s0)
Ci(a’b’ + a b) + Ci' (a’b + a b’)
Plus
b0
Ci(a + b)’+ Ci' (a + b)
CarryOut (Co0)
Ci + a + b
ai
bi Si+1

Cii
Coi
Slide 32
 Full adder implementation (standard
circuit, reduced gate type)
Co = a’ b Ci + a b’ Ci + a b Ci’ + a b Ci
Ci(a’b + a b’)+ a b (Ci’ + Ci)
1-bit adder Ci(a + b)+ a b
x1 x2 F x1 x2 F
CarryIn (Ci0)
0 0 0 0 0 0
0 1 1 0 1 1
a0 1 0 1 1 0 1 This input can not
Plus Sum0 (s0) 1 1 1 1 1 0 exist, thus XOR can
b0 replace OR.
OR XOR
CarryOut (Co0)
1 ai
1 bi Si+1

Cii 0
0
Coi
1 Slide 33
 Full adder implementation (standard
circuit, reduced gate type)
Co = a’ b Ci + a b’ Ci + a b Ci’ + a b Ci
Ci(a’b + a b’)+ a b (Ci’ + Ci)
1-bit adder (Ci(a + b)) + a b
x1 x2 F x1 x2 F
CarryIn (Ci0)
0 0 0 0 0 0
0 1 1 0 1 1
a0 1 0 1 1 0 1 This input can not
Plus Sum0 (s0) 1 1 1 1 1 0 exist, thus XOR can
b0 replace OR.
OR XOR
CarryOut (Co0)
1 ai
1 bi Si+1

Cii 0
0
Coi
1 Slide 34
 Ripple carry adder using full adder
a0
b0 S0
a0
Plus s0 Cio
b0 Co0

a1
Plus s1
b1 a1
b1 S1
a2
Plus s1
b2 Ci1
Co1

Ci2
Slide 35
 Ripple carry adder using full adder
a0 2 XOR gate delay
a0 b0 S0
Plus s0
b0
Cio
Co0
a1
Plus s1
b1 1 AND + 2 XOR gate delay

a2
a1 1 AND + 3 XOR gate delay
b1 S1
Plus s1 32-bit: XOR + (n-1)(AND+XOR|OR) + XOR
b2 = 64 gates total (for sign bit)

Ci1
Propagation delay = Co1
O(n), that is, linear
with word size 2 AND + 3 XOR gate delay

This is a very slow

32-bit: XOR + (n)(AND+XOR|OR) = 65 gates total (for carry out bit)
circuit. Ci2
Slide 36
 Carry-lookahead adder
Ripple carry:
C1 = b0C0 + a0C0 + a0b0
C2 = b1C1 + a1C1 + a1b1
Ci+1 = bi Ci + ai Ci + ai bi
C3 = b2C2 + a2C2 + a2b2
C4 = b3C3 + a3C3 + a3b3 Ci+1 = Ci(bi + ai ) + ai bi
Ci+1 = Ci( pi ) + gi generates
a 1 to the
propagates a
carry
1 to the carry
Partial Full Adder (PFA or B Cell) Note: generate and propagate functions
have 1 gate delay constant time
ai
bi Si+1
Cii pi+1
gi+1
Slide 37
 Carry-lookahead adder
Ci+1 = Cipi+ gi
i=0 C1 = C0p0+ g0

Ci+1 = (Ci-1pi-1+ gi-1)pi+ gi

= Ci-1pi-1pi+ gi-1pi+ gi
i=1 C2 = C0p0p1+ g0p1+ g1

Ci+1 = ((Ci-2pi-2+ gi-2)pi-1+ gi-1)pi+ gi

= Ci-2pi-2pi-1pi+ gi-2pi-1pi+ gi-1pi+ gi
i=2 C3= C0p0p1p2+ g0p1p2+ g1p2+ g2
Slide 38
 Carry-lookahead adder
C0
Ci+1 = Cipi+ gi a0 s0
PFA g0
i=0 C1 = C0p0+ g0 b0 C1
p0
C1
a1 s1
Ci+1 = (Ci-1pi-1+ gi-1)pi+ gi PFA g1 C2
b p1
= Ci-1pi-1pi+ gi-1pi+ gi 1
C2
i=1 C2 = C0p0p1+ g0p1+ g1 a2 s2 Carry
PFA g2 Lookahead C3
b2 p2 logic

Ci+1 = ((Ci-2pi-2+ gi-2)pi-1+ gi-1)pi+ gi

= Ci-2pi-2pi-1pi+ gi-2pi-1pi+ gi-1pi+ gi
i=2 C3= C0p0p1p2+ g0p1p2+ g1p2+ g2
Slide 39
 Carry-lookahead adder
final design

Note the OR between p and g, so the XOR implementation for

p = a + b when a=1 and b=1 will result in a zero: but since
g = a b, g will be one for these inputs, and the OR
note: xi=ai, yi=bi between p and g ensures that the final output is
correct.

Slide 40
 Arithmetic Logic Unit (ALU)
ALU primary function: to enable basic arithmetic operations (in C: &, |, +, -, <, >)

Operation

a
0
a AND b
Result
a OR b
1
b
2 x 1 Mux

Integer operations
2 function ALU that implements bitwise a=3, b=5
AND and bitwise OR. bit-wise AND a & b 1
bit-wise OR a|b 7

Slide 41
 Arithmetic Logic Unit (ALU)

ALU operation
ALU operation
selector
to be performed
Operation

a
0
Result a b
1 a+b
b

2 x 1 Mux

CarryIn

a
Plus sum
b

CarryOut
Just another operation
to be performed
Slide 42
 Arithmetic Logic Unit (ALU)

ALU operation
ALU operation
selector
to be performed
Operation
2
a
0
Result a b
1 a+b
b
adder

CarryIn

a
2
Plus sum
b

CarryOut
Just another operation
to be performed Note: the ALU developed here uses the ripple-carry adder design.
Slide 43
Arithmetic Logic Unit (ALU)

Operation O peration
CarryIn
a
0
Result a
0
1
b

1
Result
CarryIn

a
2 2
Plus sum b
b

CarryOut CarryO ut

1-bit three function ALU

Slide 44
 Arithmetic Logic Unit (ALU)
• Subtraction: use two's complement approach, i.e.,
negate b and add.

Binvert Operation
CarryIn

a
0

1
Result

b 0 2

CarryOut
Slide 45
 Arithmetic Logic Unit (ALU)
• Subtraction: use two's complement approch, i.e.,
negate b and add.

Binvert Operation
CarryIn

a
0

negate 1
Result
(flip)
b
b 0 2

CarryOut
Slide 46
 Arithmetic Logic Unit (ALU)
Binvert Operation
CarryIn

a
0

1
Result

b 0 2
1

CarryOut

1-bit four function ALU

Binvert Operation Description
0 00 and
0 01 or
0 10 addition
1 10 subtraction

Slide 47
 Arithmetic Logic Unit (ALU)
Binvert Operation O pe ration
B in v ert
CarryIn
The 1-bit ALU Least
Significant
a
0 circuit is (because carry-in
replicated not connected)
1 a0
Result (copied) for b0 ALU0 result0
each bit in
b 0 2 the computer
1
word, with
the ripple- a1
result1
b1 ALU1
CarryOut carry adder’s
carry-out
1-bit four function ALU connected to
the next’s a2
Binvert Operation Description carry-in. b2 ALU2 result2

0 00 and
0 01 or
a3 ALU3 result3
0 10 addition b3
Most
1 10 subtraction significant

Most significant 31 Bit order 0 Least significant

Slide 48
 Arithmetic Logic Unit (ALU)
Comparison: a < b Recall: binary numbers are stored in two’s
complement (2’s complement) format:
Consider the slt (set less than) therefore, most significant bit reprsents the
sign of the binary number.
MIPS instruction
Note: assume no
• Compare two (integer) inputs overflow occurs

• If (a < b) • a-b
• Result = 1 – If sign bit = 1
• Result = 0000 0001 (8-bit word)
• a<b
• Else
• Result = 0 – Else (sign bit = 0)
• Result = 0000 0000 (8-bit word) • a not < b

Note: Result0 is set 0 or 1 depending on Note: Result0 is set to the

condition, all other result bits are set to zero. sign bit after subtraction
Slide 49
 Arithmetic Logic Unit (ALU)

O pe ration
B in v ert
A in v ert
Comparison: a < b
CarryIn
Consider the slt (set less than)
MIPS instruction
a0
b0 ALU0 result0
B in v ert O pe ration less0
C a rry In

a
0 a1
b1 ALU1 result1
0
1
R e su lt

b 0
a2
2 result2
b2 ALU2
New input less
1 0
New output: Set
less
3

Set a3
ALU3 result3
Ca rry O ut b3
Note: Result0 is set to the sign bit after subtraction 0
set
all other result bits are set to zero
Slide 50
B in v ert
Arithmetic Logic Unit (ALU)
A in v ert O pe ration

O pe ration
B in v ert
A in v ert
CarryIn 3

a 0 CarryIn
0
1

1 a0
b0 ALU0 result0
less0

b 0 + 2 Result
a1
1 b1 ALU1 result1
Less 3 0

4
a2
5 b2 ALU2 result2
0
other
functions

a3
b3 ALU3 result3
0
Multifunction ALU set

Set Slide 51
CarryOut
B in v ert
Arithmetic Logic Unit (ALU)
A in v ert O pe ration
All of the available functions
CarryIn 3
Ainvt Binvt Op a b Ci L Set Co R
a 0
0 0 000 x x a and b
0
1
0 0 001 x x a or b

1 0 0 010 0 x a+b

0 0 010 1 x a+b+1

x x 011 x x x L

b 0 + 2 0 x 100 x x x a
1 x 0 101 x x x b
Less 3 0 1 000 x x a and b'
0 1 001 x x a or b'
4 0 1 010 1 x a-b
5 x 1 101 x x x b'
1 0 000 x x a' and b
other
functions 1 0 001 x x a' or b
1 0 010 1 x b-a
1 X 100 x x x a'

Multifunction ALU 1 1 000 x x a' and b'

1 1 001 x x a' or b'
Set Slide 52
CarryOut
B in v ert
Arithmetic Logic Unit (ALU)
A in v ert O pe ration
All of the available functions
CarryIn 3
Ainvt Binvt Op a b Ci L Set Co R
a 0
0 0 000 x x a and b
0
1
0 0 001 x x a or b

1 0 0 010 0 x a+b

0 0 010 1 x a+b+1

x x 011 x x x L

b 0 + 2 0 x 100 x x x a
1 x 0 101 x x x b
Less 3 0 1 000 x x a and b'
0 1 001 x x a or b'
4 0 1 010 1 x a-b
5 x 1 101 x x x b'
1 0 000 x x a' and b
other
functions 1 0 001 x x a' or b
1 0 010 1 x b-a
1 X 100 x x x a'

Multifunction ALU 1 1 000 x x a' and b'

1 1 001 x x a' or b'
Set Slide 53
CarryOut
B in v ert
Arithmetic Logic Unit (ALU)
A in v ert O pe ration
All of the available functions
CarryIn 3
Ainvt Binvt Op a b Ci L Set Co R
a 0
0 0 000 x x a and b
0
1
0 0 001 x x a or b

1 0 0 010 0 x a+b

0 0 010 1 x a+b+1

x x 011 x x x L

b 0 + 2 0 x 100 x x x a
1 x 0 101 x x x b
Less 3 0 1 000 x x a and b'
0 1 001 x x a or b'
4 0 1 010 1 x a-b
5 x 1 101 x x x b'
1 0 000 x x a' and b
other
functions 1 0 001 x x a' or b
1 0 010 1 x b-a
1 X 100 x x x a'

Multifunction ALU 1 1 000 x x a' and b'

1 1 001 x x a' or b'
Set Slide 54
CarryOut
 Arithmetic Logic Unit (ALU)

O pe ration
SLT operation timing

B in v ert
A in v ert
Time Ainvt Binvt Op a b Ci L Set Co R
CarryIn T0 0 1 010 1 x a-b
T1 x x 011 x x x L

a0 T0 0 1 011 1 SLT
b0 ALU0 result0
less0
Note 1) Don’t care values can be combined
with other control signal values
a1
b1 ALU1 result1
0 Note 2) Op code only applies to the
multiplexer which selects the output. In this
case, the operation 010 (a-b) is not the
a2
b2 ALU2 result2 output, therefore, this operation code can be
0 ignored.

a3 Combinational circuit means that after some

b3 ALU3 result3
0
period of time, the circuit stabilizes to the
set correct output. Therefore, the SLT requires
more time than a-b operation to stabilize. Slide 55
 Arithmetic Logic Unit (ALU)

O pe ration
Post ALU operations

B in v ert
A in v ert
CarryIn

a0 Zero
b0 ALU0 result0
less0 (if result = 0, Zero = 1, otherwise, Zero = 0)

a1
b1 ALU1 result1
0

a2
b2 ALU2 result2
0

a3
b3 ALU3 result3
0
set

Slide 56