Course Plan

A. Course Handout (Version 1.0) | Last updated on 4th Dec, 2023

Institute/School Name Chitkara University Institute of Engineering & Technology

Department Name Department of Computer Science and Engineering
Programme Name Bachelor of Engineering (B.E), Computer Science & Engineering
Course Name Computer Organisation and Session 2023-2024
Architecture
Course Code 22CS016 Semester/Batch 4th/CSE 2022
L-T-P (Per Week) 3-0-0 Course Credit 03
Course Coordinator Dr. Kamal Saluja

1. Objective of the Course

This course is a study of the evolution of computer architecture and the factors influencing the design of
hardware and software elements of computer systems. It begins with the basic organization, design, and
programming of a simple digital computer. The main objectives of the course are:
• To introduce internal communication of computers.
• To comprehend the implementation of the machine instructions for the operation of the
computer system.
• To interpret the concept of microprogrammed control, parallel processing, and pipelining.
• To illustrate the memory organization and data transfer techniques.

Articulate the knowledge of digital electronics, computer organization and architecture to propose
CLO01
innovative solutions.

CLO02 Comprehend the architecture and functionality of the central processing unit.

CLO03 Conceptualize the microprogrammed control, parallel processing and pipelining.

Evaluate different computer architectures, memory hierarchies, and I/O techniques, and make
CLO04
informed decisions about their suitability for different applications.

Analyze the performance of computer systems in terms of processing speed, memory usage, and I/O
CLO05
operations, and identify potential bottlenecks and areas for improvement.

2. Course Learning Outcomes

After completion of the course, the student should be able to:

Course Outcome POs CL* KC** Sessions

Articulate the knowledge of digital PO1, PO2, PO3, PO4 K2 Factual 11

electronics, computer organization
CLO01
and architecture to propose
innovative solutions.
CLO02 Comprehend the architecture and PO1,PO2,PO3,PO4, K4 Conceptual 13
functionality of the central PO11,PO12 Procedural
processing unit.
CLO03 Conceptualize the PO1,PO2,PO3,PO4,PO12 K3 Conceptual 17
microprogrammed control, Procedural
parallel processing and pipelining.

Computer Organisation and Architecture /22CS016 Page 1 of 7

 Course Plan

CLO04 Evaluate different computer PO1,PO2,PO3,PO4,PO5, K3 Conceptual 11

architectures, memory hierarchies, PO10,, PO11, PO12 Procedural
and I/O techniques, and make
informed decisions about their
suitability for different
applications.
CLO05 Analyze the performance of PO1,PO2,PO3,PO4,PO05, K3 Conceptual 8
computer systems in terms of PO9, PO12 Metacognitive
processing speed, memory usage,
and I/O operations, and identify
potential bottlenecks and areas
for improvement.
Total Contact Hours 60
Revised Bloom’s Taxonomy Terminology
*
Cognitive Level =CL
**
Knowledge Categories = KC

CLO-PO Mapping grid |Program outcomes (POs) are available as a part of the Academic Program Guide
Course PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
Learning
Outcomes

CLO1 H H H H
CLO2 H H H H L M

CLO3 H M L M H

CLO4 H M M M L M M

CLO5 H H H M L L M
H=High, M=Medium, L=Low

3. ERISE Grid Mapping

Feature Enablement Level(1-5, 5 being highest)

Entrepreneurship 2

Research 5

Innovation 2

Skills 2

Employability 4

4. Recommended Books:

Text Books:
B01: Computer System Architecture, M. Morris Mano, Pearson Education, Third Edition, 2008
B02: Computer Organization and Architecture: Designing for Performance, William Stallings, Pearson
Education, Seventh Edition, 2008

Computer Organisation and Architecture /22CS016 Page 2 of 7

 Course Plan

Reference Books:
B03: Computer Architecture and Organization, John P Hayes, Tata Mc-Graw Hill, 3rd Edition, 1998
B04: Computer Organization and Design: The Hardware/Software Interface, Patterson, D. A., and Hennessy,
J.L., Elsevier, 3rd Edition, 2005.
B05: Essentials of Computer Organization and Architecture, Linda Null, Jones & Bartlett Learning, 6th Edition,
2023

E-Resources:
https://ndl.iitkgp.ac.in/

5. Other readings & relevant websites:

S.No. Link of Journals, Magazines, websites and Research Papers

1. http://nptel.ac.in/courses/106104073/
2. http://nptel.ac.in/courses/106106092/
3. http://nptel.ac.in/courses/106103068/
4. https://ocw.mit.edu/courses/6-823-computer-system-architecture-fall-
2005/pages/lecture-notes/
5. http://www.cs.iit.edu/~virgil/cs470/Book/

6. Recommended Tools and Platforms

• NPTEL
• SWAYAM

7. Course Plan:

Lecture
Topic(s) Books
Number
1-2 Introduction to Computer Organization & Architecture, Overview of Digital B01-Chpater-1
System
3-5 Introduction to Flip-Flops and its types B01-Chpater-1
6-7 Shift Registers: SIPO, SISO, PISO and PIPO B01-Chpater-2
8-10 Introduction and Design of Synchronous (mod-n) and Asynchronous (Ripple) B01-Chpater-2
counters.
11-14 Basic Computer Organization: Instruction Codes, Computer Registers, B05-Chpater-4
Computer Instructions.
15-16 Timing and Control, Instruction Cycle B02-Chpater-12
17-18 Memory Reference Instructions, Input-Output and Interrupts B01-Chpater-5

19-21 Central Processing Unit: Introduction, General Register Organization B01-Chpater-8

22-24 Stack Organization and Instruction Format, Notations B01-Chpater-8

25-28 Addressing Modes, Data Transfer and Manipulation B01-Chpater-8

29-32 Program Control: Status bits, Conditional Branch Instructions, Program B01-Chpater-8
Interrupts & Types
33-34 RISC and CISC Characteristics. B02-Chpater-13
35-39 Pipelining and parallel processing: Basics of pipelining, pipeline hazards, B04-Chpater-4
techniques for handling hazards, parallel processing architectures

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 Course Plan

40-42 Input-Output Organization: I/O Interface B01-Chpater-11

43-45 Asynchronous Data Transfer B01-Chpater-11

46-48 Modes of Transfer B01-Chpater-11
49-53 Direct Memory Access (DMA), DMA Transfer, Input-Output Processor (IOP), B02-Chpater-7
CPU-IOP Communication.
54-58 Memory Organization: B03-Chpater-6
Memory Hierarchy, Main Memory, Auxiliary Memory, Associative Memory
59-60 Cache Memory and Virtual Memory B01-Chpater-12

8. Delivery/Instructional Resources

Web Audio-Video
Lecture
Topic(s) References
Number
1-2 Introduction to Computer https://nitsri.ac.in/Departmen https://www.youtube.com/w
Organization & Architecture, t/Electronics%20&%20Commu atch?v=q6oiRtKTpX4
Overview of Digital System nication%20Engineering/Chapt
er1-Introduction.pdf https://www.youtube.com/w
atch?v=jm0PGDSSBkI
https://www.cuemath.com/nu
mbers/number-systems/ https://www.youtube.com/w
atch?v=i-tnQMDdbfc

3-5 Introduction to Flip-Flops and https://www.tutorialspoint.co https://www.youtube.com/w

its types m/what-are-computer- atch?v=Aft2vPt9tkc
registers-in-computer- https://www.youtube.com/w
architecture atch?v=Vt3lFnBwgpo
https://www.youtube.com/w
atch?v=Iecj9xmIfXM
6-7 Shift Registers: SIPO, SISO, https://www.youtube.com/w
PISO and PIPO https://www.tutorialspoint.co atch?v=Aft2vPt9tkc
m/what-are-computer- https://www.youtube.com/w
registers-in-computer- atch?v=Vt3lFnBwgpo
architecture https://www.youtube.com/w
atch?v=Iecj9xmIfXM
8-10 Introduction and Design of https://www.javatpoint.com/i https://www.youtube.com/w
Synchronous (mod-n) and nstruction-cycle atch?v=Bsh_WYIlLXs
Asynchronous (Ripple)
counters.
11-14 Basic Computer https://home.adelphi.edu/~sie https://www.youtube.com/w
Organization: Instruction gfried/cs371/371l10.pdf atch?v=0XybwAbup-
Codes, Computer Registers, w&list=PL59E5B57A04EAE09
Computer Instructions. C&index=33

https://www.youtube.com/w
atch?v=LTVCbvlZbKU
15-16 Timing and Control, https://nptel.ac.in/courses/10 https://www.youtube.com/w
Instruction Cycle 6/103/106103068/ atch?v=iGHzG5xR_nA
17-18 Memory Reference https://nptel.ac.in/courses/10 https://www.youtube.com/w
Instructions, Input-Output 6/103/106103068/ atch?v=X6GbaLQUuz8
and Interrupts

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 Course Plan

19-21 Central Processing Unit: https://uomustansiriyah.edu.i https://www.youtube.com/w

Introduction, General q/media/lectures/5/5_2020_0 atch?v=vjqnWn5PdD0
Register Organization 5_23!12_34_32_AM.pdf
22-24 Stack Organization and http://nptel.ac.in/courses/106 https://www.youtube.com/w
Instruction Format, 104073/ atch?v=u-sp4gBAJKI
Notations
25-28 Addressing Modes, Data http://nptel.ac.in/courses/106 https://www.youtube.com/w
Transfer and Manipulation 104073/ atch?v=p9wxyIx-j-c
29-32 Program Control: Status bits, http://nptel.ac.in/courses/106 https://www.youtube.com/w
Conditional Branch 106092/ atch?v=oTmpeck2M6M
Instructions, Program
Interrupts & Types
33-34 RISC and CISC https://cs.colby.edu/courses/F https://www.youtube.com/w
Characteristics. 20/cs232/notes/9.ISA(II).pdf atch?v=pt-OOSSGezc
35-39 Pipelining and parallel https://ocw.mit.edu/courses/6 http://www.infocobuild.com/e
processing: Basics of -823-computer-system- ducation/audio-video-
pipelining, pipeline hazards, architecture-fall- courses/electronics/DigitalCo
techniques for handling 2005/resources/l05_singlecycl mputerOrganization-IIT-
hazards, parallel processing e/ Kharagpur/lecture-07.html
architectures
https://ocw.mit.edu/courses/6
-823-computer-system-
architecture-fall-
2005/resources/l06_pipeline/
40-42 Input-Output Organization: https://nptel.ac.in/courses/10 https://www.youtube.com/wa
I/O Interface 6/103/106103068/ tch?v=Y17TLZCSe4M
43-45 Asynchronous Data Transfer https://cvbl.iiita.ac.in/sks/coa- https://www.youtube.com/wa
files/lectures/Lec_11_IO[1].pd tch?v=-gRryttI3Ig
f
46-48 Modes of Transfer https://witscad.com/course/c https://www.youtube.com/w
omputer- atch?v=-gRryttI3Ig
architecture/chapter/io-data-
transfer
49-53 Direct Memory Access https://witscad.com/course/c https://www.youtube.com/w
(DMA), DMA Transfer, Input- omputer- atch?v=3RfqkVyvnnc
Output Processor (IOP), CPU- architecture/chapter/dma-
IOP Communication. controller-and-io-processor
54-58 Memory Organization: https://ocw.mit.edu/courses/6 http://www.infocobuild.com/
Memory Hierarchy, Main -823-computer-system- education/audio-video-
Memory, Auxiliary Memory, architecture-fall- courses/electronics/DigitalCo
Associative Memory 2005/resources/l07_caches/ mputerOrganization-IIT-
Kharagpur/lecture-17.html
59-60 Cache Memory and Virtual https://ocw.mit.edu/courses/6 http://www.infocobuild.com/
Memory -823-computer-system- education/audio-video-
architecture-fall- courses/electronics/DigitalCo
2005/resources/l09_add_trans mputerOrganization-IIT-
/ Kharagpur/lecture-19.html

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 Course Plan

9. Action plan for different types of learners

Slow Learners Average Learners Fast Learners

• Remedial Classes on • Provide focused • Incorporate real-life problem-
Saturdays instruction on areas solving scenarios to engage fast
• Offer supplementary where average learners in critical thinking.
materials or activities to learners may need • Encourage the pursuit of
reinforce concepts additional support. independent research projects or
outside regular class • Encourage special assignments aligned with
hours. collaborative learning personal interests.
• Foster a collaborative through group projects • Provide opportunities for them to
learning environment and activities. mentor or assist peers who may
where students can learn need additional support.
from their peers.

10. Evaluation Scheme & Components:

Evaluation No. of Weightage of Mode of

Type of Component
Component Assessments Component Assessment
Subjective Test/Sessional
Component 2 03* 40% Offline
Tests (STs)
Component 3 End Term Examinations 01 60% Offline
Total 100%
*
All the STs are mandatory. Makeup Examination will compensate for either ST1 or ST-2 (Only for genuine
cases, based on Dean’s approval).

11. Details of Evaluation Components:

Evaluation Description Syllabus Timeline of Examination Weightage

Component Covered (%) (%)
ST 01 30% Week 6
Component 2 ST 02 31% - 57% Week 10 40%
ST 03 58% - 97% Week 17
At the end of the
Component 3 End Term Examination* 100% 60%
semester
Total 100%
*As per Academic Guidelines minimum 85% attendance is required to become eligible for appearing in the End Semester
Examination.

11. Syllabus of the Course:

No. of Weightage
S. No. Topic (s)
Lectures %
Introduction to Computer Organization & Architecture, Overview of
2
Digital System.
Introduction to Flip-Flops and its types 3
1 30%
Shift Registers: SIPO, SISO, PISO and PIPO 2
Introduction and Design of Synchronous (mod-n) and Asynchronous
3
(Ripple) counters.

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 Course Plan

Basic Computer Organization: Instruction Codes, Computer Registers,

Computer Instructions, Timing and Control, Memory Reference 8
Instructions, Input-Output and Interrupts.
ST-1 (Syllabus = (Lecture number 1-18)
Central Processing Unit: Introduction, General Register Organization.
6
Stack Organization and Instruction Format, Notations.
2 Addressing Modes, Data Transfer and Manipulation. 4 27%
Program Control: Status bits, Conditional Branch Instructions, Program
6
Interrupts & Types, RISC/CISC Characteristics.
ST-2 (Syllabus = (Lecture number 19-34)
Pipelining and parallel processing: Basics of pipelining, pipeline
hazards, techniques for handling hazards, parallel processing 5
architectures.
Input-Output Organization: I/O Interface, Asynchronous Data Transfer,
3 Modes of Transfer, Direct Memory Access (DMA), DMA Transfer, DMA 14 40%
Controller Input-Output Processor (IOP), CPU-IOP Communication.
Memory Organization:
Memory Hierarchy, Main Memory, Auxiliary Memory, Associative 5
Memory
ST-3 (Syllabus = (Lecture number 35-58)

12 Cache Memory and Virtual Memory 2 3%

End Term (Covering 100% syllabus)

This Document is approved by:

Designation Name Signature

Course Coordinator Dr. Kamal Saluja
Head-Academic Delivery Dr. Ravi Kumar Sachdeva
Dean Dr. Raj Gaurang Tiwari
Dean Academics Dr. Monit Kapoor

Date (DD/MM/YYYY) Dec 04, 2023

Computer Organisation and Architecture /22CS016 Page 7 of 7