Lecture #11

Finite-state Machines
Introduction

 Digital circuits composed of combinational and

sequential logic sections are generally described
as finite state machines.
 A machine is synchronous when the state
transitions are controlled or synchronized by a
clock signal.
 A machine whose operation is not dependent on a
clock signal is said to be asynchronous.
 The present state (PS) of a state machine is
determined by the variables stored in the flip-flops
of the sequential section.
 The next state (NS) of the state machine is defined
by the circuit of the combinational logic section.
Introduction

 A machine always has a finite number

of states. For N variables, the machine
must have between 2 and 2N states.
 A machine is defined by specifying the
number of inputs and outputs, the
initial state, the PS and the NS.
Introduction

 Among finite state machines, we can

differentiate between the Moore model
and the Mealy model.

 It must be noted that there are also

hybrid machines with some outputs
being of Moore type and others of
Mealy type.
Moore
 Moore state machine: the state
machine output depends entirely on
the PS;
 Mealy
 Mealy state machine: the state machine
output depends on the inputs and PS.
 State diagram
 Usualy there are two tools for describing sequential
systems.
 A state table shows, for each input combination and
each state, what the output is and what the next state
is, that is, what is to be stored in memory after the
next clock.
 A state diagram (or state graph) is a graphical
representation of the behavior of the system, showing
for each input combination and each state what the
output is and what the next state is, that is, what is to
be stored in memory after the next clock.
 A state diagram presents the information from the
state/output table in a graphical form.
 A state diagram is constructed according to certain
rules
Sum rule
 Sum rule: the Boolean sum of all
conditions under which a transition
from a given state occurs must be
equal to 1:
Mutual--exclusion
Mutual
 Mutual-exclusion requirement: each
condition under which a transition from
a given state occurs cannot be
associated with more than one
transition path:
 As a result, the Boolean product of both
state transition conditions, Fl · Fk (l, k =
0, 1, 2, · · · , n – 1) and (l != k), is equal
to 0.
 However, these relationships need not
be verified for applications where certain
conditions will never happen or are not
allowed (don’t-care conditions).
Moore
 Each state is represented by a circle.
 Also included in the circle is the output for that state.
 Each line coming out of a circle represents a possible
transition.
 The label on the line indicates the input that causes
that transition.
 There must be one path from each state for each
possible input combination.
Mealy
 The output is associated with the transition, rather
than the state.
 Each path has a double label: the input causing
the transition, followed by a slash and the output
that occurs when the system is in that state and
that is the input.
 Thus, from state A, the path to state B is labeled
1/0, meaning that that path is followed when x = 1,
and the output produced is 0.
 Design of synchronous finite
state machines
 The procedure for designing synchronous finite
state machines may include the following steps:
1) derive the state diagram;
2) draw up the state table;
3) assign bit combinations to the variables in order
to represent the different states (encoding the
different states) and draw up the corresponding
state table;
4) choose the flip-flop type;
5) derive the input equations based on Karnaugh
maps;
6) represent the resulting logic circuit.
 Example - Binary sequence
detector
 A logic circuit that can recognize the binary
sequence 101 is to be designed.
 The output, Y, will be set to 1 immediately after the
last bit of this sequence is applied at the input, X, of
the circuit.
 The initial step consists in representing the state
diagram describing the state changes and the
output in response to each of the input bits.
 This diagram is then converted into a state table
that, in conjunction with the excitation table of a
given flip-flop, helps to fill in the Karnaugh maps
used for the determination of the logic equations of
the NSs and output.
Example - Binary sequence
detector (101)
Mealy model
Mealy model
 It is possible to represent four states
with two flip-flops.
 There is, therefore, a state that is
unused by the 101 sequence detector
based on the Mealy model.
 In general, when there are unused
states their effect on the state
machine operation must be analyzed.
 Example –
Binary sequence detector (101)
Moore model
 For implementation of the detector based
on the Moore model, we proceed as
previously described, but by associating
possible outputs with the states rather than
with the transitions between states.
Example - Binary sequence
detector
Moore model
Moore model
 Comparison of the Mealy and
Moore Machines
 In general, a finite state machine based on the Mealy model
uses fewer states than one based on the Moore model.
 This is because the dependence of the output to the inputs is
exploited to reduce the number of states required in order to
satisfy the specifications of a given application.
 A state machine based on the Mealy model is faster than one
based on the Moore model.
 The output of the Moore model is generally obtained one
clock period later.
 The output of a state machine based on the Mealy model can
be affected by transient disturbances superposed on the input
signal.
 This is not the case for state machines based on the Moore
model, which are, therefore, preferable for applications that
require level triggering or control.

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