17-1 (8015) IEEE Asian Solid-State Circuits Conference

November 5 - 7 , 2018/Tainan, Taiwan

A 1.6-GHz 3.3-mW 1.5-MHz Wide Bandwidth AS

Fractional-N PLL with a Single Path FIR Phase Noise
Filtering
Jingcheng Tao and Chun-Huat Heng
National University o f Singapore, Kent Ridge, Singapore
Email: [email protected]

Abstract—This paper describes a novel AE quantization noise

filtering method for wideband AH fractional-N PLL. A single
path finite impulse response (FIR) filtering technique is realized
through two-step phase interpolation. A prototype 1.6GHz Ah
fractional-N PLL with 1.5MHz wide loop bandwidth is
implemented in 130nm CMOS process. Measurement results
show that the proposed technique effectively reduces the high
frequency quantization noise by 12dB and achieves an in-band
phase noise of -lOldBc/Hz at 400kHz and 2.14ps integrated jitter,
while consuming only 3.3mW power and an area of 0.24mm2.
Keywords—wideband; fractional-N PLL; FIR; single path;
phase noise filtering

I. I n t r o d u c t io n
AE fractional-N PLLs have played a key role in modem
wireless and wireline applications, offering very fine frequency
resolution without being limited by the reference frequency.
Ah fractional-N PLL can also enable direct digital phase
modulation, which is critical for polar transmitter. However,
wide loop filter bandwidth is needed to meet the bandwidth
requirement o f the modulated data. For PLLs with smaller loop
bandwidth, the issue is overcome by either applying pre­
emphasis on the transmitted data, or employing 2-points
modulation to achieve all-pass characteristic [1]. Both (a)
techniques require sophisticated calibration to characterize the
PLL loop filter and VCO characteristics. Wider loop filter
bandwidth also allows faster frequency hopping. Nevertheless,
the AE fractional-N PLL loop bandwidth is usually limited by
the shaped AE quantization noise at high frequencies.
Various techniques have been reported to suppress the high
frequency shaped phase noise for fractional-N PLL to achieve
wider PLL loop bandwidth. One approach is to adopt a digital-
to-analog converter (DAC) to compensate for the accumulated
phase errors generated by the AE modulator [2]. However,
complicated calibration is often needed to mitigate the analog
mismatches and non-linearity. This incurs larger power and
area penalty. Hybrid FIR filtering technique has been proposed
to filter out the high frequency shaped phase noise due to the
(b)
AE modulator [3] [4]. However, it requires multiples parallel
Fig. 1: Block diagram o f the proposed AE fractional-N PLL(a)
circuit paths, with each path containing their own charge pump Mode lwith FIR filtering (b) Mode 2 without filtering
(CP), phase frequency detector (PFD) and divider. In [5], a
high frequency phase blender and an interpolator are utilized to high over sampling ratio (OSR) is achieved by using cascaded
reduce the number o f dividers and PFDs, but multiple high PLLs to obtain high reference frequency o f 800MHz.
frequency circuit paths are still required. These duplicated However, the circuit suffers from limited frequency resolution
circuit paths incur significant area and power penalty. In [6], and higher modulator power consumption.

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17-1 (8015) IEEE Asian Solid-State Circuits Conference
November 5 - 7 , 2018/Tainan, Taiwan

In this paper, we propose a novel FIR phase noise filtering

technique with only a single circuit path, which leads to
significant circuit area and power saving. The proposed
technique is demonstrated with a 1.6 GHz AL fractional-N
PLL.

II. S ingle P ath FIR F iltering Arch itecture

The single path FIR noise filtering technique is illustrated
in Fig. 1(a). The phase rotation mechanism o f the proposed
fractional-N PLL is controlled by two sets o f control words, i.e.
4-bit M[3:0] and 3-bit K[2:0]. M[3:2] controls the multi-phase
divider output while M[1:0] determines the 1st phase
interpolator (PIi). K[2:0] will adjust the 2nd phase interpolator
(PI2) output. A divide-by-2 stage generates four equally spaced
phases denoted as /, Q, IB, QB at half the VCO frequency.
Then the four phases are fed into a multi-phase divider to
Fig. 2: Phase rotation diagram
generate P0, P90, P1S0, P270, P360 with an evenly spaced phase
of half VCO cycle. QB is then fed to a dual modulus divider
that is controlled by the carry bit o f the digital phase
accumulator.
The PLL has two working modes: mode 1 (with single path
FIR filtering, Fig. 1(a)) and mode 2 (without FIR filtering, Fig.
1(b)). In mode 2, a 2nd order AS modulator is used to generate
fractional frequency control output (D0) with a high-pass noise
profile. D0 is then directly sent to the digital phase
accumulator. The M[3:2] and carry bit from the accumulator
are then used to control multi-phase divider and the dual
modulus divider. Through M[3:2], the MUX will select the
two neighbouring phases (d^, d>2) from Po~ p3 eo to feed into
XOR PD. In mode 2, the single-path FIR filtering is disabled
by keeping M[1:0]=00 and K[2:0]=000. This essentially
results in a phase-rotator (PR) based fractional-N PLL with a
phase resolution o f 1/2 VCO cycle.
In mode 1, the modulator output (D0) will first go through a
digital FIR filter to suppress the high frequency shaped phase
noise. This effectively generates an average o f Npm delayed
AL modulator outputs (NiV^-order FIR, in this design,
N fir= 8 ). A s a result, the high frequency shaped noise is
suppressed by the low pass FIR filter but the digital filtered
output will have larger bit-width. The digitally filtered output is
then passed to the digital phase accumulator. The accumulator
will in turn generate carry bit, M[3:0] and K[2:0]. M[3:2] and
the carry bit function similarly as in mode 2. To provide finer
phase control that corresponds to the larger digital output bit-
width, a two-stage phase interpolator PL controlled by M[1:0]
is inserted to further interpolate the MUX outputs into 4 finer
phases with a phase resolution o f 1/8 VCO cycle. Hence, Fig. 3: (a) Mode 2 : w/o noise filtering
M[3:0] now controls a total o f 16 phase rotation steps. (b) Mode 1: w/ single path FIR noise filtering
Although more phase interpolations can be incorporated into
PL, the inherent non-linearity o f voltage-to-phase conversion multiple delayed circuit paths at the CP. In the proposed single
limits the number o f interpolated phases in PL- path FIR approach, higher resolution analog phase control is
achieved by embedding PI2 inside the XOR phase
It should be pointed out that the 3-bit K[2:0] from
detector/interpolator (the XOR PD/PI). The PI2 operation is
accumulator is used to represent the fractional phase rotation in
described as follows: First, the two interpolated finer adjacent
addition to the integer part M[3:0]. To correctly represent this
phases (0lf 02) from PL described earlier are fed into the XOR
finer digital fractional phase rotation, we need to create their
PD/PI. The phase detector part consists of two XOR gates
corresponding higher resolution analog phase representation to
(XOR_PDl and XOR_PD2) that compare (0 i, 02) with the
avoid the truncation error that will otherwise worsen the
reference signal. Finer phase interpolation is achieved by
overall phase noise. In the hybrid FIR approach, this is
weighting the output currents (a and 1-a) of the two phase
achieved in analog domain by summing the phase errors from

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17-1 (8015) IEEE Asian Solid-State Circuits Conference
November 5 - 7 , 2018/Tainan, Taiwan

detectors based on K[2:0] and then summing them to generate

the desired CP output current. Much better linearity and
resolution can be achieved in PI2 because the phase
interpolation is performed in current domain. The total CP
current ( N ^ ) is set by the desired PLL loop bandwidth. With
this approach, fractional phase resolution can be achieved
without extra power consumption. Fig. 2 illustrates the phase
rotation details o f the proposed technique. As an example,
assume the initial phase is 0°, and the FIR output is 2.375:
M=0010, K=011. M rotates the phase to the red region; K will
then further interpolate the phase within this region as shown in
the zoom-out sub-figure. Fig. 3(a) and (b) compares the phase
noise performance in mode 1 and mode 2 when the loop
bandwidth is 1.5 MHz. As shown, the AS quantization noise Fig. 4: Multi-phase divider
(blue line) is significantly suppressed in mode 1.

m. C ir c u it d e s ig n

A. Multi-phase Divider
The multi-phase divider is shown in Fig. 4. The divide-by-2
quadrature phase generator employs two D-latches in a master-
slave configuration [8]. The frill swing output o f this structure
allows easier interfacing with the subsequent frequency
divider. The dual-modulus divider output is delayed by a
retiming circuit. The amount o f delay in the retiming circuit is
tuned automatically by detecting output phase sequence to
make sure that the sequence o f P0- P36Q is always correct.
B. Pipelined Phase Interpolator (PI¡)
Pi! is an inverter-based two-stage pipelined phase
interpolator as shown in Fig. 5(a). The stack inverters are used
to minimize the overshooting effect. Small inverter buffers
between each stage slow down the rise/fall time to achieve
better interpolation at the output. All these help to improve the
PI linearity as depicted in Fig. 5(b).
C. XORPI/PD
The schematic o f the XOR PD/PI is shown in Fig. 6 [7].
The charge pump function is embedded within this block. Four
XOR PDs are used here to steer the current into or away from
the actual charge pump path. XOR PD 1 and X O R P D 2 are
employed to detect the phase difference between the reference
signal and the divider feedback signal. Two additional phase
detectors, XOR-PD 3 and XOR-PD 4, are used to steer the tail
current when XOR-PD 1 and XOR-PD 2 are both turned off. A
unity gain buffer is added to maintain the same voltage for both effectively filters out the out-of-band AS quantization noise.
the replica node and output node. The phase interpolation is The in-band phase noise is about -101 dBc/Hz at 400 kHz and
done by scaling the output currents o f the two phase detectors the measured integrated RMS jitter from 40 kHz to 40 MHz is
by varying the 3-bit tail current DAC. 2.14 ps. The reference spur as shown in Fig. 8(a) is -57.6 dBc.
IV. M ea su rem en t R esults The total power consumption is only 2.7 mA under 1.2 V DC
supply and Fig. 8(b) shows the system power breakdown.
This PLL is fabricated in 130-nm CMOS process as shown
in Fig. 7. Its active die area is only 0.24 mm2. The designed Our work is benchmarked with recent works on AS
loop bandwidth is 1.5 MHz. The 50 MHz reference signal quantization noise cancellation in Table I. Thanks to the
using external crystal is generated on chip. The measured proposed single path FIR filtering technique, our work
phase noise o f free-running VCO is -103 dBc/Hz at 200 KHz demonstrates the lowest power (3.3 mW) and smallest circuit
offset and 120 dBc/Hz at 1 MHz offset. Fig. 6 shows the area (0.24 mm2) compared to other AS quantization noise
measured phase noise performance. When the single path FIR suppression techniques, while achieving excellent and
filtering is enabled, the phase noise due to AS modulator comparable phase noise filtering performance.
quantization error is reduced by 12 dB. Compared to phase
noise o f integer-N mode, it is clear that the proposed technique

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17-1 (8015) IEEE Asian Solid-State Circuits Conference
November 5 - 7 , 2018/Tainan, Taiwan

TABLE I
P erformance Comparison with previous reported fractional-N PLLs
T his w o rk [2]T M T T ’2016 [3 ]JS S C ’2009 [4]JS S C ’2009 [5|JS S C '2 0 1 3 |6 ]J S S C ’2012

O u tp u t frequency 1.6 G H z 1.8 G H z 1 GHz 2 GHz 1 GHz 2.4 G H z

BW 1.5 M H z 1 M Hz 1 M Hz 200 kH z 3.2 kH z 2 M Hz

In - b a n d p h ase noise -101 dB c/H z -101 dB c/H z -85 dB c/H z -92 dB c/H z -106 dB c/H z -102 dB c/H z
(400 kH z) (100 kH z) (10 kH z) (200 kH z) (100 kH z) (100 kH z)
O u t-o f-b a n d p h ase -124 dB c/H z -129 dB c/H z N.A. -128 dB c/H z -107 dB c/H z 130 dB c/H z
noise (6 M H z) (3 M H z) (3.5 M H z) (6 M H z) (10 M H z)

Noise cancelling Single P a th F IR DAC KIR F IR F IR em b e d d ed H ig h -O S R

m eth o d
F ra c tio n a l s p u r level -57 dB c -68 dB c N.A. -63 dB c -66 dBc -54.7 dB c

C o re pow er 3.3 m W 8.3 m W 6.1 m W 17.2 m W 16.8 m W 9.6 m W

C o re area 0.24 n u n 2 0.33 n u n 2 0.5 m m 2 1.5 m m 2 0 .3 1 m m 2 0.46 m m 2

T echnology 130 nm 130 nm 180 nm 180 nm 130 nm 130 nm

V C O type LC LC R ing LC R in g LC

V. C o n c l u s io n
In this paper, we demonstrate an architecture that can
suppress the shaped AS phase noise at higher frequencies by 12
dB. It has the smallest area o f 0.24 mm2 and power o f 3.3 mW
compared to other high frequency shaped phase noise
suppression techniques. This is made feasible by avoiding
multiple feedback analog circuit paths or high frequency phase
blender. The proposed 1.6-GHz PLL exhibits 1.5-MHz loop
bandwidth, and achieves -101 dBc/Hz in-band phase noise and
2.14 ps RMS jitter. This allows direct data modulation without
Fig. 7: PL L die photo the need of pre-emphasis or sophisticated calibration.

A cknow ledgm ent

This work is funded by MOE Tier 2 grant MOE2016-T2-1-
123.

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