M.S.

Ramaiah Institute of Technology

(Autonomous Institute, Affiliated to VTU)
Department of ARTIFICIAL INTELLIGENCE AND MACHINE LEARNING

Course Name: Computer Organization and

Architecture
Course Code: AI553
Unit -1

◻ Basic Structure of Computers: Basic Operational

Concepts, Bus Structures, Performance – Processor
Clock, Basic Performance Equation, Clock Rate,
Performance Measurement.
◻ Machine Instructions and Programs: numbers,
arithmetic operations and characters, Memory
Location and Addresses, Memory Operations
Introduction
 What is Computer

◻ All computers have in

common: hardware and software.
ô Hardware is any part of your computer
that has a physical structure, such as the
keyboard or mouse.
ô Software is any set of instructions that tells
the hardware what to do and how to do it.
Examples of software include web
browsers, games, and word processors.
What are the different types of
computers?
Analogy
◻ A chef prepares a certain recipe, then serves it to the
customers.
◻ Chef knows how to prepare the food item whereas customer
cares only about quality and taste of the food.
◻ “customer” as computer organization
◻ “chef” can referred to as computer architecture
Analogy
 Computer organization

◻ Computer Organization- The way hardware components are

connected to form a computer system
◻ In other words, it is mainly about the programmer’s or user point
of view.
◻ Organization - physical design of a computer
1.How many registers?
2. What is a register?
3. How many registers does a typical CPU have?
 Computer Architecture

◻ Structure and behaviour of the various functional units of the

computer and their interactions
◻ Basically, throws light on the designer’s point of view.
Computer Architecture

◻ In a system, there are a set of instructions, it is enough for

programmer or user to know what are a set of instructions
present in case of computer organization

◻ System designer worries about how a set of instructions are

implemented, algorithm of implementation is the emphasis
in the case of architectural studies.
Generations of Computer
Functional Units

◻ A Computer consist of 5 main parts

Functional Units

A computer program is a collection of instructions

that can be executed by a computer to perform a
specific task.
Functional Units

Central Processing Unit (CPU) consists of the following

features
CPU is considered as the brain of the computer.
CPU performs all types of data processing operations.
It stores data, intermediate results, and instructions (program).
It controls the operation of all parts of the computer.
3 components inside CPU
■ Registers
■ Control unit
■ ALU(Arithmetic Logic Unit)
Functional Units

ALU (Arithmetic Logic Unit)

This unit consists of two subsections namely,
Arithmetic section
LogicSection
◻ Arithmetic section
The function of arithmetic section is to perform arithmetic
operations like addition, subtraction, multiplication, and division.
◻ Logic Section
The function of the logic section is to perform logic operations
such as comparing, selecting, matching, and merging of data.
Functional Units

Control unit
Functions of this unit are
It is responsible for controlling the transfer of data and
instructions among other units of a computer.
It manages and coordinates all the units of the computer.
It obtains the instructions from the memory, interprets them,
and directs the operation of the computer.
It communicates with Input/output devices for transfer of
data or results from storage.
It does not process or store data.
 BASIC OPERATIONAL CONCEPTS
Connection between the processor and Memory

17
BASIC OPERATIONAL CONCEPTS
◻ The contents of PC(i.e. address) are transferred to the MAR & control-unit
issues Read signal to memory. • After certain amount of elapsed time, the first
instruction is read out of memory and placed into MDR
◻ . Next, the contents of MDR are transferred to IR. At this point, the instruction
can be decoded & executed
◻ . To fetch an operand, it's address is placed into MAR & control-unit issues Read
signal. As a result, the operand is transferred from memory into MDR, and then
it is transferred from MDR to ALU.
◻ Likewise required number of operands is fetched into processor.
◻ Finally, ALU performs the desired operation. • If the result of this operation is
to be stored in the memory, then the result is sent to the MDR.
◻ The address of the location where the result is to be stored is sent to the MAR
and a Write cycle is initiated.
◻ At some point during execution, contents of PC are incremented to point to
next instruction in the program. [The instruction is a combination of opcode and
operand].
1. **Program Counter (PC):**
- Contains the memory address of the instruction to be executed.

BASIC OPERATIONAL CONCEPTS

- Updated during execution to point to the next instruction.
- Releases its contents to the internal bus, sending it to the Memory Address Register (MAR).

2. **Memory Address Register (MAR):**

- Holds the address of the location to or from which data will be transferred.
- The connection to main memory is one-way or unidirectional.

3. **Memory Data Register (MDR):**

- Contains the data to be written to or read from the addressed location.
◻ The contents of PC(i.e. address) are transferred to the MAR & control-unit issues
- During the fetch operation, MDR contains the instruction to be executed or data needed during execution.
- In a write operation, MDR holds the data to be written into the main memory.
Read signal to memory. • After certain amount of elapsed time, the first
instruction
4. **Instruction Register (IR):**
- Contains the instruction currently is read
being out of memory and placed into MDR
executed.
- Before executing the instruction, it needs to be decoded.
- When the ◻ . Next,
content of the MDRthe contents
is transferred to theof
IR, MDR areprocess
the decoding transferred
begins. to IR. At this point, the instruction
can be decoded & executed
- After decoding, the execution of the instruction takes place.

The operational steps described in the passage can be related to the fetch-decode-execute cycle, which is a fundamental process in the operation of a
CPU. Here's a◻more .To fetch
detailed an operand,
breakdown it'ssteps:
of the operational address is placed into MAR & control-unit issues Read
1. **Fetch:** signal. As a result, the operand is transferred from memory into MDR, and then
it is transferred
- The Program Counter from address
(PC) contains the memory MDR oftotheALU.next instruction to be executed.
- The contents of the PC are released to the internal bus and sent to the Memory Address Register (MAR).
◻ Likewise required number of operands is fetched into processor.
- The MAR holds the address, and this address is used to fetch the instruction from the main memory.
- The fetched instruction is placed into the Memory Data Register (MDR).

2. **Decode:**◻ Finally, ALU performs the desired operation. • If the result of this operation is
- The content of theto MDR,
be stored
which now inholds
- The IR contains the instruction being executed.
thethe memory, then
fetched instruction, the result
is transferred is sent Register
to the Instruction to the(IR).
MDR.
and the operands The address of the location where the result is to be stored is sent to the MAR
- Before execution, the instruction needs to be decoded. The decoding process interprets the instruction to determine the operation to be performed
◻ involved.

3. **Execute:**
and a Write cycle is initiated.
Atan some
arithmetic point
operation,during execution,
- After decoding, the CPU performs the actual operation specified by the instruction.
◻
- If the instruction is the ALU (Arithmetic contents
Logic Unit) of inPC
may be involved areoutincremented
carrying the computation. to point to
- If the instructionnext
involvesinstruction
data transfer, the indata
themayprogram. [The
be moved between instruction
registers, the memory,isoraother
combination of opcode
components as directed and
by the instruction.

4. **Update:** operand].
- The Program Counter (PC) is updated to point to the next instruction in memory.
- The cycle then repeats, starting with the fetch of the next instruction.

This series of steps, known as the fetch-decode-execute cycle, is repeated continuously as long as the computer is running. It is a fundamental process
that allows the CPU to fetch instructions from memory, execute them, and move on to the next instruction in a sequential manner, forming the basis for
the execution of computer programs.
 Bus Structure
There are many ways to connect different parts
inside a computer together.
A group of lines that serves as a connecting path
for several devices is called a bus.
Address/data/control
BUS STRUCTURE
◻ A bus is a group of lines that serves as a connecting path for several devices.
◻ Bus must have lines for data transfer, address & control purposes. • Because the bus can
be used for only one transfer at a time, only 2 units can actively use the bus at any given
time.
◻ Bus control lines are used to arbitrate multiple requests for use of the bus.
◻ Main advantage of single bus: Low cost and flexibility for attaching peripheral devices.
◻ Systems that contain multiple buses achieve more concurrency in operations by allowing 2
or more transfers to be carried out at the same time.
◻ Advantage: better performance.
◻ Disadvantage: increased cost.
◻ The devices connected to a bus vary widely in their speed of operation.
◻ To synchronize their operational speed, the approach is to include buffer registers with the
devices to hold the information during transfers. Buffer registers prevent a high-speed
processor from being locked to a slow I/O device during a sequence of data transfers.
Bus Structure

Single-bus
 Bus Structure
Speed Issue
Different devices have different transfer/operate speed.
o Keyboard, printers are slow
o Magnetic or optical disk are fast
o Memory and processor are faster
If the speed of bus is bounded by the slowest device
connected to it, the efficiency will be very low.
How to solve this?
A common approach – use buffers.
Performance

The most important measure of a computer is how

quickly it can execute programs.
Three factors affect performance:
⮚ Hardware design - Cache
⮚ Instruction set

⮚ Compiler design
Performance – Hardware design

◻ Processor time to execute a program depends on the hardware involved in

the execution of individual machine instructions.
Performance – Hardware design

The processor and a relatively small cache memory

can be fabricated on a single integrated circuit chip.
A cache is a special storage space for temporary
files that makes a device run faster and more
efficiently.
ô Speed
ô Cost
ô Memory management
Performance – Hardware design

◻ Processor circuits are controlled by a timing signal called clock.

◻ Clock – defines regular time intervals called clock cycles
◻ P – length of once clock cycle
Performance – Hardware design

To execute a machine instruction, processor

divides the action into 4 steps.
Each step take once clock cycle .
Performance – Hardware design

Clock rate(R)/Processor Speed

ô Is a measure of number of clock cycles per second.

◻ CPU clock speed/clock rate, is measured in Hertz — generally

in gigahertz, or GHz.
Performance – Hardware design

Basic Performance Equation

T – processor time required to execute a program that
has been prepared in high-level language
N – number of actual machine language instructions
needed to complete the execution
S – average number of basic steps needed to execute one
machine instruction. Each step completes in one clock
cycle
R – clock rate
31
Performance – Hardware design

Basic Performance Equation

How to improve T?
• Pipelining and Superscalar operation
• Clock rate
Performance – Hardware design

Pipelining
Instructions are not necessarily executed one after
another.

Pipelining – overlapping the execution of successive

instructions.
Performance – Hardware design

Pipelining – overlapping the execution of successive

instructions.

Superscalar – Different instruction can be executed in

parallel
Performance – Hardware design

Clock Rate
Increase clock rate
⮚ Improve the integrated-circuit (IC) technology to make
the circuits faster
⮚ Reduce the amount of processing done in one basic
step (however, this may increase the number of basic
steps needed)
Performance – Instruction set

Processor can have simple instruction and complex

instruction
Simple instruction requires a small number of steps to
execute.
Complex instruction involve a large number of steps

The design of Instruction set of a Processor can be

Reduced Instruction Set Computer(RISC)
Complex Instruction Set Computer(CISC)
Performance – Instruction set

If a processor has only Simple instructions – Program will

have large number of instructions
ô N – large value
ô S – small value

If a processor has only Complex instructions – Program

will have lesser number of instructions
ô N – small value
ô S – large value
Performance – Instruction set
Performance – Compiler

A compiler translates a high-level language program into

a sequence of machine instructions.
Performance – Compiler

A compiler may not be designed for a specific processor;

however, a high-quality compiler is usually designed for a
specific processor.
Goal – reduce N×S
To reduce N, we need a suitable machine instruction set
and a compiler that makes good use of it.
Performance – Measurement

◻ T is difficult to compute

◻ So, we can measure computer performance using benchmark

programs.
◻ System Performance Evaluation Corporation (SPEC) selects
and publishes representative application programs for
different application domains, together with test results for
many commercially available computers.
Performance Summary

METRICS
Processor clock
Basic performance equation
Pipelining & super scalar operation
Clock rate
Instruction set CISC & RISC
Compiler
Performance measurement
 Number, Arithmetic Operations, and
Characters
Let us learn
◻ Binary number representation
◻ Arithmetic operation on these number
◻ Character representation
 Number, Arithmetic Operations, and
Characters
◻ Computers are built using logic circuits that operate on
information represented by two values 0 and 1.
◻ The bit of information stands for binary digit
◻ Represent number  string of bits called binary
number
◻ Represent Text character  string of bits called
character code
 Number, Arithmetic Operations, and
Characters
◻ Integer number are represented in two forms
Signed integer
Unsigned integer
◻ Unsigned integer number represent positive numbers.
◻ Computer does not have provision to represent
negative sign, so various techniques are used
 Number, Arithmetic Operations, and
Characters
◻ Computers are built using logic circuits that operate on
information represented by two values 0 and 1.
◻ The bit of information stands for binary digit
◻ Represent number  string of bits called binary
number
◻ Represent Text character  string of bits called
character code
Number, Arithmetic Operations, and
Characters
Number representation
◻ Various techniques to represent signed integer number
are
o Sign and magnitude
o One’s complement
o Two’s complement
 Number, Arithmetic Operations, and
Characters
◻ Integer number are represented in two forms
o Signed integer
o Unsigned integer
◻ Unsigned integer number represent positive numbers.
◻ Computer does not have provision to represent
negative sign, so various techniques are used
Number, Arithmetic Operations, and
Characters
Number, Arithmetic Operations, and
Characters
◻ Assumptions:
4-bit machine word
16 different values can be represented
Roughly half are positive, half are negative
Number, Arithmetic Operations, and
Characters
 Sign-and-magnitude
system
 Plus(+) sign to represent positive number and Minus(-) sign to represent
negative number
 Positive number and Negative number are represented with binary digits.
The leftmost bit(sign bit) in the number represent sign of the number.
The remaining bits represent magnitude of number
 Signed magnitude format for 4-bit signed number

MSB = 0, then number is +ve

b3 b2 b1 b0
MSB LSB MSB = 1, then number is -ve

Sign Magnitude
 Sign-and-magnitude
system
b3 b2 b1 b0

+0 0 0 0 0
-0 1 0 0 0
 Sign-and-magnitude
system
b3 b2 b1 b0

+1 0 0 0 1
-1 1 0 0 1
 Sign-and-magnitude
system
b3 b2 b1 b0
5
2

+5 0 1 0 1 2 2 1

-5 1 1 0 1 1
0
 Sign-and-magnitude
system
2 6
b3 b2 b1 b0
2 3 0

+6 0 1 1 0 1
1

-6 1 1 1 0
 Sign-and-magnitude
system
7
b3 b2 b1 b0 2

2 3 1
+7 0 1 1 1
1 1
-7 1 1 1 1
 Sign-and-magnitude
system
 For addition and subtraction, it is necessary to consider signs of both the number and their relative
magnitude in order to carry out the required arithmetic operation
 There are two representation of zero(0)
 +0  0000
 -0  1000
 Due to this, it is difficult to test for zero operation frequently
performed by computer
 1's complement system

 The 1’s complement of a

binary number is the
number that results when
we change all 1’s to zeros
and the zeros to 1’s.
 1's complement system

b3 b2 b1 b0

+0 0 0 0 0
-0 1 1 1 1
 1's complement system

b3 b2 b1 b0

+1 0 0 0 1
-1 1 1 1 0
 1's complement system

b3 b2 b1 b0

+5 0 1 0 1
-5 1 0 1 0

5
2

2 2 1

0
1
 2's complement system

 The 2’s complement is the

binary number that results
when we add 1 to the 1’s
complement.

2’s complement = 1’complement +1

2's complement system

C 1
+2 0 0 1 0
1’s 1 1 0 1
1
-2 1 1 1 0
 5
2
2's complement system
2 2 1

0
1
C
+5 0 1 0 1
1’s 1 0 1 0
1
-5 1 0 1 1
 7
2
2's complement system
2 3 1

1 1
C
+7 0 1 1 1
1’s 1 0 0 0
1
-7 1 0 0 1
2's complement system

C 1 1 1 1
+0 0 0 0 0
1’s 1 1 1 1
1
-0 0 0 0 0
 2's complement system

Advantages
 Here One representation for +0 and -

0
 Here -8 is representable

 Most efficient way to carry out

addition and subtraction operations
 Most often used in computers
 ADDITION OF POSITIVE NUMBERS

 Consider adding two 1-bit numbers.

 The sum of 1 & 1 requires the 2-bit vector 10 to represent the
value 2.
 We say that sum is 0 and the carry-out is 1.
Carry 1
out
1

sum 0
Number, Arithmetic Operations, and
Characters
◻ Various techniques
o Sign and magnitude
o One’s complement
o Two’s complement
◻ They differ in the way we
represent negative numbers
To understand 2’s complement arithmetic

 Consider addition
modulo N(mod N)
 A Graphical device of addition
mod N of positive integers is a
circle with N values ( 0 to N-
1)along its perimeter
 Use this device to compute
(a+b) mod N
To understand 2’s complement arithmetic
 Consider the case N=16
(a + b) mod N
15
(7 +4) mod 16
14
= 11
13 3
Locate 7 on the circle and then
12 4 move 4 units in the clockwise
direction to arrive at the
11 5
answer 11
10 6

9 7
8
To understand 2’s complement arithmetic
 Consider the case N=16
(a + b) mod N
15
(9 +14) mod 16
14
23 mod 16
13
=7
3

12 4 Locate 9 on the circle and then

move 14 units in the clockwise
11 5
direction to arrive at the
10 6 answer 7
9 7
8
ADDITION & SUBTRACTION OF SIGNED NUMBERS

Two rules for addition and subtraction of n-bit signed numbers using the 2's
complement representation system
Rule 1:
To Add two numbers, add their n-bits and ignore the carry-out signal from the
MSB position.
Result will be algebraically correct, if it lies in the range -2n-1 to +2n-1-1.

Rule 2:
To Subtract two numbers X and Y (that is to perform X-Y), take the 2's
complement of Y and then add it to X as in rule 1.

Result will be algebraically correct, if it lies in the range -2n-1 to +2n-1-1.

ADDITION OF SIGNED NUMBERS

Rule 1:
To Add two numbers, add their n-bits and ignore the carry-out
signal from the MSB position.
Result will be algebraically correct, if it lies in the range -2n-1 to
+2n-1-1.

n = 4 bits  - 24-1 to + 24-1 - 1

- 23 to + 23 - 1
-8 to +7
Addition rule
2's complement system

C 1
+2 0 0 1 0
+3 0 0 1 1
+5 0 1 0 1
Addition rule
2's complement system

C
+4 0 1 0 0
-6 1 0 1 0
-2 1 1 1 0
Addition rule
2's complement system

C 1 1 1
-5 1 0 1 1
-2 1 1 1 0
s -7 1 0 0 1
SUBTRACTION OF SIGNED NUMBERS

Rule 2:
To Subtract two numbers X and Y (that is to perform
X-Y), take the 2's complement of Y and then add it to X
as in rule 1.
Result will be algebraically correct, if it lies in the range
-2n-1 to +2n-1-1.

n = 4 bits  - 24-1 to + 24-1 - 1

- 23 to + 23 - 1
-8 to +7
Subtraction rule
2's complement system
1 1 1 1
X -3 1 1 0 1
Y -7 0 1 1 1 C
X-Y +4 0 1 0 0 Y -7 1 0 0 1
1’ 0 1 1 0
s
1
0 1 1 1
Subtraction rule
2's complement system
1 1
X +6 0 1 1 0
Y +3 1 1 0 1 C
X-Y +3 0 0 1 1 Y +3 0 0 1 1
1’ 1 1 0 0
s
1
1 1 0 1
Subtraction rule
2's complement system
1 1 1 1
X -7 1 0 0 1

Y +1 1 1 1 1 C
X-Y -8 1 0 0 0 Y +1 0 0 0 1
1’ 1 1 1 0
s
1
1 1 1 1
Subtraction rule
2's complement system
1
X +2 0 0 1 0
Y -3 0 0 1 1 C
X-Y +5 0 1 0 1 Y 1 1 0 1
1’ 0 0 1 0
s
1
0 0 1 1
OVERFLOW IN INTEGER ARITHMETIC

 Example of addition and subtraction in 4-bit

example, answers fall in the range of -8 and
+7.
 When answers do not fall within this range,

we say that overflow has occurred

OVERFLOW IN INTEGER ARITHMETIC

◻ When result of an arithmetic operation is outside the

representable range, an arithmetic overflow is said to
occur.
◻ Examine the signs of the two summands X and Y and sign
of the result. When both operands X and Y have the same
sign, an overflow occurs when the sign of S is not the same
as sign of X and Y.
OVERFLOW IN INTEGER ARITHMETIC

◻ The rules for detecting overflow in a two's complement

sum are simple:
1. If the sum of two positive numbers yields a

negative result, the sum has overflowed.

2. If the sum of two negative numbers yields a

positive result, the sum has overflowed.

3. Otherwise, the sum has not overflowed.
OVERFLOW IN INTEGER ARITHMETIC

◻ Perform following operation on the 4-bit signed numbers using 2’s

complement representation system. Also indicate whether overflow
has occurred. (+7) + (+4)
C 0 1
X +7 0 1 1 1
Y +4 0 1 0 0
S -5 1 0 1 1 Overflow has occurred
OVERFLOW IN INTEGER ARITHMETIC

◻ Perform following operation on the 4-bit signed numbers using 2’s

complement representation system. Also indicate whether
overflow has occurred. (-5) + (-6)
C 1 1
X -5 1 0 1 1
Y -6 1 0 1 0
S +5 0 1 0 1 Overflow has occurred
OVERFLOW IN INTEGER ARITHMETIC

◻ Perform following operation on the 4-bit signed numbers using 2’s

complement representation system. Also indicate whether overflow
has occurred. (+7) + (-4)
C 1 1
X +7 0 1 1 1
Y -4 1 1 0 0
S +3 0 0 1 1
No Overflow
CHARACTERS
◻ Character can be letters of the alphabet , decimal digits,
punctuation marks and so on.
◻ Are represented by codes(ASCII -7bits and EBDIC – 8bits )

ASCII American standard

committee on Information
Interchange

EBDIC Extended Binary coded

Decimal Interchange code
Memory Location and Addresses

What is Memory
It is a storage unit, a place to hold data and instruction.
Memory Location and Addresses

Memory Organisation
Memory consist of
many millions of
storage cells.
Each cell can store 1-bit
information having
value (0 or 1)
Memory organized as
group of n-bits
Memory Location and Addresses

Group of n-bits is
referred as word
n is called word length
The word length of 8 bit
is known as byte
Word length can range
from 16 to 64bits,
simple called word.
Memory Location and Addresses

Memory Location
Memory is divided into
multiple small parts, of
fixed size and capable of
holding information.

Memory Address
ô Each memory location is
uniquely identified by a
BINARY ADDRESS(HEXA
VALUE).
Memory Location and Addresses

Memory Address
If 2k addresses constitute the address space of computer,
then memory can have up to 2k addressable locations.

Example
k= 10 , 210 = 1,024(1K kilo) locations
k= 20 , 220 = 1,048,576(1M mega) locations
k= 24 , 224 = 16,777,216(16M mega) locations
k= 30 , 230 = 1G (giga) locations
k= 32 , 232 = 4G (giga) locations
k= 40 , 240 = 1T(tera) locations
Memory Location and Addresses

If the word length is 32

bits, single word can
store 32 bits or 4 ASCII
characters as shown in
the Figure .
Memory Location and Addresses

It is impractical for bit address locations

But prefer byte address location – byte addressable
memory

Byte Addressable memory

Each Memory address refers to a single byte of
storage. To store data of large size, multiple
consecutive locations are used
Memory Location and Addresses

Two ways Byte address can be assigned across words

ô Big-Endian Assignments
ô Little-Endian Assignments
Memory Location and Addresses

Big Endian
The MSB of the data is
placed at the byte with
the lowest address.
Little Endian
The LSB of the data is
placed at the byte with
the lowest address.
Memory Operations

Load (or Read or Fetch)

⮚ Copy the content. The memory content doesn’t change.
⮚ Address – Load
⮚ Registers can be used
Store (or Write)
⮚ Overwrite the content in memory
⮚ Address and Data – Store
⮚ Registers can be used
 UNIT-2
102

◻ Instructions and Instruction Sequencing: register

transfer notation, assembly language notation,
basic instruction types, branching, condition
codes, generating memory address, Addressing
Modes: variables and constants, indirection and
pointers, indexing and arrays, relative addressing,
Basic Input and Output Operations
Instruction and Instruction sequencing

Computer performs 4 types of operations:

Data transfer between memory and processor

Arithmetic and logic operations on data
Program sequencing and control
I/O transfers
Data Transfer
Transfer data from one location to another location
Memory locations
Processor registers
Registers in I/O system
Location is given symbolic name
Name for memory address location A,LOC,VAR,PLACE
Name for Processor register names R1,R2,R3…..
Name for I/O register names DATAIN,DATAOUT
Data Transfer
Register Transfer Notation
Assembly Language Notation
Data Transfer

R3  [R1] + [R2]
This type of notation is called RTN (Register Transfer
Notation) Processor
R1 =10
R2 = 20
R3 = 30
Data Transfer
Contents of location are denoted by placing square
brackets around the name of the location
R1  [LOC]
Processor Memory Memory
R1 =10 address location
LOC 10
 Data Transfer

Assembly Language Notation

Move LOC, R1 Processor Memory Memory

R1 =10 address location
LOC 10
 Data Transfer

Assembly Language Notation

Add R1,R2,R3
Processor
R1 =10
R2 = 20
R3 = 30
Instruction and Instruction sequencing

Basic instruction types

Three address instruction format
Two address instruction format
One address instruction format
Zero address instruction format
Basic Instruction Types
Opcode Operand(s) or Address(es)

To represent machine instruction and program, we

use assembly language format.
General 3 address instruction format
Operation Source1, Source 2, Destination

Operands
Source 1, Source 2 are source operands
Destination are called destination operands
Basic Instruction Types
Example C= A+B
Add the value of variable A and B and store in C
During compilation three variables A,B,C are
assigned to distinct locations in memory
Action Memory Memory location
address
C  [A]+[B] A 10
B 20
C 30
Basic Instruction Types
Three address instruction format
Add A, B ,C

This instruction contain memory address of three

operands
Operands A and B – Source operand
Operand C – Destination operand
 Basic Instruction Types
Three address instruction format
Add A, B ,C

◻ Operands A , B,C are memory address - k bits

◻ 3 * 1000 = 3kbits for addressing purpose
◻ Operation Add – n bits
◻ Modern Processor is 32bit address space, then 3 address instruction format is
too large to fit in one word
◻ So multiple word is required for single instruction
 Basic Instruction Types
Two address instruction format
Operation Source, Destination
Add A, B Memory Memory location
address
B  [A]+[B] A 10

But here we are replacing the B 20 30

Content of original location B

Basic Instruction Types
Two address instruction format

Operation Source, Destination

Move B, C Memory Memory location

address
Add A, C A 10
B 20
C 30
Basic Instruction Types
One address instruction format

Operation Operand

Operand Specified in instruction can be source or

destination, depending on the instruction
Basic Instruction Types
One address instruction format

Operation Operand

When second operand is required, processor register

like Accumulator can be used

Add A
 Basic Instruction Types
One address instruction format

Add A
◻ Add the content of memory location to the content of Accumulator
and store the result in accumulator
Memory Memory
Processor address location
Acc= 20 A 10
20+10 = 30
Basic Instruction Types
One address instruction format

Operation Operand

Operand Specified in instruction can be source or

destination, depending on the instruction
Source Operand
Load A
Store A
Destination Operand
 Basic Instruction Types

Add A Load A
Store A
Load A - copies the contents of memory location
A into accumulator

Memory address Memory location

Processor
A 10
Acc= 10
 Basic Instruction Types

Add A Load A
Store A
Store A - copies the contents of accumulator into
memory location A

Memory address Memory location

Processor
A 20
Acc= 20
 Basic Instruction Types
Load A
Add A,B,C
Add B
C  [A]+[B] Store C

Memory address Memory location

Processor
A 5
Acc= 5
B 10
= 5+10
= 15 C 15
Basic Instruction Types
Processor has several general purpose register
Many instruction involve operands that are in the
register
Processor computations are performed directly on
data held in processor register Processor
R1 =10
R2 =20
Add Ri, Rj or R3 =30
Add Ri, Rj , Rk
Basic Instruction Types
Transfer data between different location
Move Source Destination

Places a copy of the content of source to destination

Processor

Move R1 , R2 R1 =10
R2 =10
Basic Instruction Types

Move A , R1

Load A , R1
Processor Memory Memory
Both are same R1 =10
address location
A 10
Basic Instruction Types

Move LOC , R1

Processor Memory Memory

address location
R1 =10
LOC 10
Basic Instruction Types

Move R1, A

Store R1, A
Processor Memory Memory
Both are same R1 =10
address location
A 10
Basic Instruction Types
Zero address instruction format
It is also possible to use instruction in which
locations of all the operands are defined implicitly.
Such instruction are found in machines that stores
operands in a structure called pushdown stack
Example: Evaluate (A+B) * (C+D)

ADD A, B, R1 ; R1 ← M[A] + M[B]

ADD C, D, R2 ; R2 ← M[C] + M[D]
MUL R1, R2, X ; M[X] ← R1 * R2
Processor Memor Memory
y location
R1 =30 address
R2=5 A 10
B 20
C 2
D 3
X 35
 Example: Evaluate (A+B) * (C+D)

MOV A,R1 ; R1 ← M[A]

Processor Memor Memory
ADD B,R1 ; R1 ← R1 + M[B] R1 =30 y location
addres
MOV C,R2 ; R2 ← M[C] R2=150 s
ADD D,R2 ; R2 ← R2 + M[D] A 10

MUL R1, R2 ; R2 ← R1 * R2 B 20
C 2
MOV R2, X ; M[X] ← R2
D 3
X 150
Unit -1

◻ Functional units, Bus structures, performance,

◻ Overflow in integer arithmetic: Numbers, Arithmetic operations
and characters
◻ Memory locations and addresses,
◻ Memory operations,
◻ Instructions and instruction sequencing,
◻ Addressing modes,
◻ Subroutines and use of stack frames,
◻ Encoding of machine instructions.
Instruction Execution and Straight-Line Sequencing

Executing a given instruction is a two phase procedure

• Instruction Fetch
• Instruction Execute
Instruction Fetch – instruction is fetched from memory
location whose address is in PC, and placed in IR.
Instruction Execute – instruction placed in IR is examined and
the required operation is done. PC is incremented to point to
next instruction.
Instruction Execution and Straight-Line Sequencing

To begin executing a program, the address of first

instruction will be placed in program counter, then
processor control circuit will use the information in PC
to fetch and execute instruction one at a time, in the
order of increasing addresses. This is called Straight-
Line Sequencing
Instruction Execution and Straight-Line Sequencing

Write a program for C  [A] +[B ]

1. MOV A,R0
2. ADD B,R0
3. MOV R0,C
Assume
• Memory Word length is 32 bits
• Memory is byte addressable
• Three instructions are stored in
successive word locations, starting at
location i.
• Each instruction is 4 bytes long, i+4,
i+8
Instruction Execution and Straight-Line Sequencing
 Instruction Execution and Straight-Line Sequencing

Consider the task to add a list of n numbers

◻ The addresses of memory locations of n

numbers are NUM1,NUM2,NUM3..

◻ After adding the result is placed in SUM

 Instruction Execution and Straight-Line Sequencing

◻ Instead of using long list of Add instructions,

it is possible to place a single Add
instructions in a program loop.
◻ This loop is straight line sequence of
instruction executed as many times as
needed
◻ It starts at location LOOP and ends at the
Branch instruction (Branch >0)
Instruction Execution and Straight-Line Sequencing
Memory Memory location
address
Processor
R1 =3/2/1
R0 =2+3+5 SUM 10
N n=3
NUM1 2
NUM2 3
NUM3 5
Condition Codes

Processor status is described as Condition codes or

Status codes.
Condition codes refers to the information about
most recently executed information.
This is accomplished by recording the required
information in individual bits called condition code
flags( 0 or 1)
 Condition Codes
Condition code flags
N (negative)
Z (zero)
V (overflow)
C (carry)
Unit -1

◻ Functional units, Bus structures, performance

◻ Overflow in integer arithmetic: Numbers, Arithmetic operations
and characters
◻ Memory locations and addresses
◻ Memory operations
◻ Instructions and instruction sequencing
◻ Addressing modes
◻ Subroutines and use of stack frames
◻ Encoding of machine instructions
Generating memory address
How to specify the address of an operand
The instruction set of a computer provides a
method called Addressing modes
Addressing modes : Different ways in which the
location of an operand is specified is called
addressing modes.
Important addressing modes found in modern
processor
Addressing modes
Different Addressing modes are :
1. Register mode
2. Absolute mode
3. Immediate mode
4. Indirect mode
5. Index mode
6. Base with Index mode
7. Base with Index and Offset mode
8. Autoincrement mode
9. Autodecrement mode
Addressing modes
Two Addressing modes to access variables
1. Register mode
2. Absolute mode
Addressing modes
Register mode
Every instruction includes operands; the operands can be a memory location,
a processor register or an I/O device.
The instruction which uses processor registers to represent operands is the
instruction in register addressing mode.

Add R4, R3, Load R3, R2

Addressing modes
Register mode
Effective address is the location of an operand of the
instruction. Operand is the data to be accessed.
EA=R

Add R4, R3, Load R3, R2

Addressing modes
Absolute mode(Direct mode)
The direct addressing mode is also known as Absolute Addressing
mode.
Here, the instruction contains the address of the location in

memory where the value of the operand is stored .

EA = A
Add R2, A
Store R2, B
Addressing modes
Addressing modes to represent constants
3. Immediate mode
Addressing modes
Immediate mode
In immediate addressing mode, the value of the operand
is explicitly mentioned in the instruction.
Here, effective address is not required as the operand is
explicitly defined in instruction.
Addressing modes
Immediate mode
The Add instruction, adds 100 to R2’s content .
The # sign in front of the value indicates the immediate
value to be operated.
If a value does not have # sign in front of it then it is the
address of a memory location.

Add #100, R2
Addressing modes
Immediate mode
Store considers the immediate value 100H as address as
it does not have # sign in front of it.
The Store instruction stores the content of R2 at memory
location 100H.
Store R2,100H
 Addressing modes
Example : A= B+6

Move B , R1
Processor
Add #6 , R1 R1 =5 + 6 =11
Memory Memory
address location
Move R1, A A 11
B 5
Addressing modes
Addressing modes to Indirection and Pointers
4. Indirect mode
 Addressing modes
Indirect mode
A processor register is used to hold the address of a
memory location where the operand is placed.
In higher-level language, it is referred to as pointers.
The indirect mode is denoted by placing the register
inside the parenthesis.
Here the effective address is the content of memory
location present in the register.
EA=(R)
 Addressing modes
Example to execute Add instruction Sum =5+3;
Add (R1) , R0
Processor Memory Memory location
R1 = B address
Add (R1), R0
R0 = 3 + 5

B 5
 Addressing modes
Example to execute Add instruction Sum =5+3;
Add (A) , R0
Processor Memory Memory location
address
Add (A), R0
R0 = 3 + 5 A B

B 5
Addressing modes
Adding a list of numbers . Indirect addressing can be
used used to access successive number in the list.
Addressing modes
Addressing modes to deal with lists and array
5. Index mode
6. Base with Index mode
7. Base with Index and Offset mode
Addressing modes
Index mode
◻ The effective address of the operand is generated by adding
a constant value to the contents of a register
◻ Register  General purpose registers (Index register)
◻ Index mode symbolically as X(Ri)
◻ X denotes constant value contained in instruction, It can be
an explicit number or symbolic name representing a
numerical value
◻ (Ri) denotes name of the register
◻ EA = X + [Ri]
 Addressing modes
2 ways of using Index mode –Offset given as constant
Add 20(R1) , R2

EA = X + [Ri]
X defines the Offset(displacement)
 Addressing modes
2 ways of using Index mode –Offset is in index register
Add 1000(R1) , R2

EA = X + [Ri]
X corresponds to memory
location
Addressing modes
Base with Index Mode
we know that Index mode EA = X + [Ri]
• Sometimes second register can be used to contain
the offset X, we can write index mode as (Ri ,Rj)
o Effective address is the sum of the contents of
register Ri and Rj.
• EA = [Ri ]+ [Rj ]
Addressing modes
Base with Index and offset Mode
we know that Index mode EA = X + [Ri]
o Sometimes index mode uses two registers plus a
constant , we can write index mode as X(Ri ,Rj)
o Effective address is the sum of the contents of
register Ri , Rj and a constant.
o We can write the Index mode as X(Ri ,Rj.)
o EA = X + [Ri ]+ [Rj ]
Addressing modes
Addressing modes use PC instead of General purpose
register
8. Relative mode
 Addressing modes
Relative mode
The effective address is determined by the index
mode using the PC in place of general purpose register
Ri
Common use to specify target address in Branch
instructions.
Addressing modes
Example of Relative mode
Branch>0 LOOP
Addressing modes
Addressing modes for accessing data items in
successive locations in memory
9. Autoincrement mode
10. Autodecrement mode
Addressing modes
Autoincrement mode
The EA of the operand is the contents of register
specified in instruction.
After accessing the operand, the contents of a
register are automatically incremented to point to
the next item in a list.
Written as (Ri)+
MOVE R0, (R2)+
Addressing modes
Autoincrement mode
Addressing modes
Example MOVE R0, (R2)+
Processor Memory address Memory location
R0 = 5
R2 = LOC(1000) LOC(1000) 5
LOC1(1001)
LOC1(1001)
Addressing modes
Autodecrement mode
The contents of a register are automatically
decremented and are then used as EA of operand
Written as -(Ri)
Addressing modes
Autodecrement mode
Addressing modes
Example MOVE -(R0), R1
Processor Memory address Memory location

R0 = LOC(1001) LOC(1000) 35

LOC(1000) LOC1(1001)

R1 = 35
Generic addressing modes
Byte addressable memory 32-bits
Each number occupies4 byte
Order of matrix n in location NUM
R0-used for summing the results and storing result
R1-to hold order of the matrix
R2,R3,R4-index registers for two source array and destination array
Assembly Language
Types of Instructions
Data Transfer Instructions
Name Mnemonic
Data value is not
Load LD modified

Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
 Data Transfer Instructions
Mode Assembly Register Transfer
Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC+ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR+XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1+1
Program-Controlled I/O Example

Read in character input from a keyboard and

produce character output on a display screen.
 Rate of data transfer (keyboard, display, processor)
 Difference in speed between processor and I/O device
creates the need for mechanisms to synchronize the
transfer of data.
 A solution: on output, the processor sends the first
character and then waits for a signal from the display that
the character has been received. It then sends the second
character. Input is sent from the keyboard in a similar way.