Single Stage Amplifiers:

Amplifier is a device which increases the strength of the input signal applied. The
amplification is done to improve the strength of the signal sometimes above the noise
signal. Also in some cases the input signal is weak to drive a load of a subsequent
stage.

Depending upon the amount of amplification to be done, the amplifiers are either
single stage amplifiers or multi stage amplifiers i.e. more than one stage say two stage
or three stage etc.

The Figure 1 shows the general Amplifier Block Diagram where input is taken as x(t) and
output is taken as y(t)
The general Amplifier equation is given by:
y(t) =Ax(t)
Here A is called the gain.

NEED OF BIASING:
In electronics, Biasing is the setting of initial operating conditions (current and voltage) of an
active device in an amplifier. Many electronic devices, such as diodes, transistors and
vacuum tubes, whose function is processing time-varying (AC) signals, also require a steady
(DC) current or voltage at their terminals to operate correctly. This current or voltage is a
bias. The AC signal applied to them is super-positioned on this DC bias current or voltage.
For proper working of a transistor, it is essential to apply external voltages of correct polarity
across its emitter-base and collector-base junctions. This is transistor biasing.
Unlike BJTs, thermal runaway does not occur with FETs. However, the wide differences in
maximum and minimum transfer characteristics make I D levels unpredictable with simple
fixed-gate bias voltage. To obtain reasonable limits on quiescent drain currents ID and drain-
source voltage VDS, source resistor and potential divider bias techniques must be used. With
few exceptions, MOSFET bias circuits are similar to those used for JFETs.
Field Effect Transistor (FET) amplifiers provide an excellent voltage gain and high input
impedance. Because of high input impedance and other characteristics of JFETs they are
preferred over BJTs for certain types of applications. They are also low-power-consumption
configurations with good frequency range and minimal size and weight.
There are 3 basic FET circuit configurations:
i)Common Source
ii)Common Drain
iii) Common Gain
Similar to BJT CE, CC and CB circuits, only difference is in BJT large output collector
current is controlled by small input base current whereas FET controls output current by
means of small input voltage. In both the cases output current is controlled variable. FET
amplifier circuits use voltage-controlled nature of the JFET. In Pinch off region, I D depends
only on VGS.
The Junction Field Effect Transistor (JFET) can be operated mainly in three regions. Those
are the Cut-off, Ohmic and Saturation regions. We must operate the JFET in the Ohmic or
linear regions for amplification. We will use the respective JFET amplifier based on the
requirement.

JFET Amplifier / Common Source JFET Amplifier:

The common source JFET amplifier has one important advantage compared to the common-
emitter BJT amplifier in that the FET has an extremely high input impedance and along with
a low noise output makes them ideal for use in amplifier circuits that require very small input
voltage signals.
Transistor amplifier circuits such as the common emitter amplifier are made using Bipolar
Transistors, but small signal amplifiers can also be made using Field Effect Transistors. The
design of an amplifier circuit based around a junction field effect transistor or “JFET” or even
a metal oxide silicon FET or “MOSFET” is exactly the same principle as that for the bipolar
transistor circuit.
A suitable quiescent point or “Q-point” needs to be found for the correct biasing of the JFET
amplifier circuit with single amplifier configurations of Common-source (CS), Common-
drain (CD) or Source-follower (SF) and the Common-gate (CG) available for most FET
devices. Common Source JFET Amplifier as this is the most widely used JFET amplifier
design.
The JFET gate voltage Vg is biased through the potential divider network set up by
resistors R1 and R2 and is biased to operate within its saturation region which is equivalent to
the active region of the bipolar junction transistor.
Unlike a bipolar transistor circuit, the junction FET takes virtually no input gate current
allowing the gate to be treated as an open circuit. Then no input characteristics curves are
required. Since the N-Channel JFET is a depletion mode device is normally “ON” with a
negative gate to source voltage is required to modulate or control the drain current. This
negative voltage can be provided by biasing from a separate power supply voltage or by a
self-biasing arrangement as long as a steady current flows through the JFET even when there
is no input signal present, and Vg maintains a reverse bias of the gate-source p-n junction.
The biasing is provided from a potential divider network allowing the input signal to produce
a voltage fall at the gate as well as voltage rise at the gate with a sinusoidal signal.
Any suitable pair of resistor values in the correct proportions would produce the correct
biasing voltage so the DC gate biasing voltage Vg is given as:

Note that this equation only determines the ratio of the resistors R1 and R2, but in order to
take advantage of the very high input impedance of the JFET as well as reducing the power
dissipation within the circuit, we need to make these resistor values as high as possible, with
values in the order of 1MΩ to 10MΩ being common.
The input signal, (Vin) of the common source JFET amplifier is applied between the Gate
terminal and the zero volts rail, (0v). With a constant value of gate voltage Vg applied the
JFET operates within its “Ohmic region” acting like a linear resistive device. The drain
circuit contains the load resistor, Rd. The output voltage, Vout is developed across this load
resistance.
The efficiency of the common source JFET amplifier can be improved by the addition of a
resistor, Rs included in the source lead with the same drain current flowing through this
resistor. Resistor, Rs is also used to set the JFET amplifiers “Q-point”.
When the JFET is switched fully “ON” a voltage drop equal to Rs*Id is developed across this
resistor raising the potential of the source terminal above 0v or ground level. This voltage
drop across Rs due to the drain current provides the necessary reverse biasing condition
across the gate resistor, R2 effectively generating negative feedback.
So in order to keep the gate-source junction reverse biased, the source voltage, Vs needs to be
higher than the gate voltage, Vg. This source voltage is therefore given as:

Then the Drain current, Id is also equal to the Source current, Is as “No Current” enters the
Gate terminal and this can be given as:
This potential divider biasing circuit improves the stability of the common source JFET
amplifier circuit when being fed from a single DC supply compared to that of a fixed voltage
biasing circuit. Both resistor, Rs and the source by-pass capacitor, Cs serve basically the same
function as the emitter resistor and capacitor in the common emitter bipolar transistor
amplifier circuit, namely to provide good stability and prevent a reduction in the loss of the
voltage gain. However, the price paid for a stabilized quiescent gate voltage is that more of
the supply voltage is dropped across Rs.
Then the value in farads of the source by-pass capacitor is generally fairly high above 100uF
and will be polarized. This gives the capacitor an impedance value much smaller, less than
10% of the transconductance, gm (the transfer coefficient represents gain) value of the device.
At high frequencies the by-pass capacitor acts essentially as a short-circuit and the source will
be effectively connected directly to ground.
The basic circuit and characteristics of a Common Source JFET Amplifier are very similar
to that of the common emitter amplifier. A DC load line is constructed by joining the two
points relating to the drain current, Id and the supply voltage, Vdd remembering that when Id =
0: ( Vdd = Vds ) and when Vds = 0: ( Id = Vdd/RL ). The load line is therefore the intersection of
the curves at the Q-point as follows.

Common Source JFET Amplifier Characteristics Curves

As with the common emitter bipolar circuit, the DC load line for the common source JFET
amplifier produces a straight line equation whose gradient is given as: -1/(Rd + Rs) and that it
crosses the vertical Id axis at point A equal to Vdd/(Rd + Rs). The other end of the load line
crosses the horizontal axis at point B which is equal to the supply voltage, Vdd.
The actual position of the Q-point on the DC load line is generally positioned at the mid
center point of the load line (for class-A operation) and is determined by the mean value
of Vg which is biased negatively as the JFET is a depletion-mode device. The output of
the Common Source JFET Amplifier is 180o out of phase with the input signal.
One of the main disadvantages of using Depletion-mode JFET is that they need to be
negatively biased. Should this bias fail for any reason the gate-source voltage may rise and
become positive causing an increase in drain current resulting in failure of the drain
voltage, Vd.
Also the high channel resistance, Rds(on) of the junction FET, coupled with high quiescent
steady state drain current makes these devices run hot so additional heatsink is required.
However, most of the problems associated with using JFET’s can be greatly reduced by using
enhancement-mode MOSFET devices instead.
MOSFET’s or Metal Oxide Semiconductor FET’s have much higher input impedance’s and
low channel resistances compared to the equivalent JFET. Also the biasing arrangements for
MOSFETs are different and unless we bias them positively for N-channel devices and
negatively for P-channel devices no drain current will flow, then we have in effect a fail safe
transistor.
Performance Parameters of JFET

1. AC Drain Resistance: The ratio of change in voltage across the drain-source terminal
and the change in drain current is termed as AC drain resistance. But the ratio should be
considered at a point when the gate-source voltage is kept constant. Its value is in range of 10
kΩ to 1 MΩ. It is also referred as dynamic resistance (rd), it should not be confused with the
resistance of channel (RDS), Rds is purely DC while rd is not.

2. DC Drain Resistance: RDS is a symbol used for DC drain resistance. It is the ratio
between the change in drain-source voltage and the change in drain current. The value of DC
drain resistance is static. Thus it is also termed as static or ohmic resistance.
3. Transconductance: It is the ratio between the change in drain current and the change
in gate-source voltage but at constant drain-source voltage. It is represented by gm.

4. Amplification factor: The amplification factor is obtained by determining the ratio

between the change in drain-source voltage with respect to change in gate-source voltage but
keeping the value of drain current constant.

It is represented by µ. The value of amplification factor can be high as 100.

The Significance of the amplification factor is that it helps to determine the control of gate to
source voltage on the value of drain current in comparison to that of the drain to source
voltage.

JFET Amplifier Current and Power Gains

The input current( Ig) of a common source JFET amplifier is very small because of the
extremely high gate impedance, Rg. A common source JFET amplifier therefore has a very
good ratio between its input and output impedances and for any amount of output
current, IOUT the JFET amplifier will have very high current gain Ai.
Because of this common source JFET amplifiers are extremely valuable as impedance
matching circuits are used as voltage amplifiers. Likewise, because: Power = Voltage x
Current, (P = V*I) and output voltages are usually several millivolts or even volts, the power
gain, Ap is also very high.