Lecture 12: Semiconductor memory II

CAM, Periphery, Case study

Hyeon-Min Bae

Department of Electrical Engineering

KAIST, Daejeon, Korea

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Static CAM Memory Cell

Bit Bit Bit Bit

Word Bit Bit
M8 M9
M4 M5
CAM ••• CAM
M6 M7

Word
Word S S
int
CAM ••• CAM M3 M2
Match M1
••• •••
Wired-NOR Match Line

6T SRAM + 3T comparison
Match initialized to VDD,
if Bit == S à intà0 à match: high
If not, int à VDD-VT, match: low
Match is connected in OR fashion, any mismatch à match: low
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Periphery

q Decoders
q Sense Amplifiers
q Input/Output Buffers
q Control / Timing Circuitry

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Row Decoders

Collection of 2M complex logic gates

Organized in regular and dense fashion

(N)AND Decoder

NOR Decoder

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Hierarchical Decoders

Multi-stage implementation improves performance

•••

WL 1

WL 0

A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3

•••
NAND decoder using
2-input pre-decoders
A1 A0 A0 A1 A3 A2 A2 A3

Total 128x16+4x4x4= 2112T. (vs 4096T) 8 input (0~256)

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Dynamic Decoders

Precharge devices VDD

GND GND

WL 3
VDD
WL 3

WL 2
WL 2 VDD

WL 1
WL 1
V DD
WL 0
WL 0

VDD f A0 A0 A1 A1
A0 A0 A1 A1 f

2-input NOR decoder 2-input NAND decoder

• Only one line is high • Active low
• High power • Only one line is high
• Faster • Small area

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4-input pass-transistor based column decoder

BL 0 BL 1 BL 2 BL 3

S0
A0

2-input NOR decoder

S1

S2

A1 S3

Ex) P.6
D

Advantages: speed (but tpd does not add to overall memory access time)
Only one extra transistor in signal path
Disadvantage: Large transistor count à 2! + 𝑘 2! + 2!
Precharge Word line select Bit select

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4-to-1 tree based column decoder

BL 0 BL 1 BL 2 BL 3

A0

A0

A1

A1

D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination of tree and pass transistor approaches
#T=2$ + 2$%& … + 2 = 2(2$ − 1)
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Decoder for circular shift-register

VDD VDD VDD VDD VDD VDD

WL 0 WL 1 WL 2
f f f f f f
• • •
R f f R f f R f f
VDD

For FIFO or video memory.

Only one bit is high at a time and shifts à pointer

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Sense Amplifiers

make D V as small
×D V
t = C
---------------- as possible
p Iav

large small

Idea: Use Sense Amplifer

small
transition s.a.

input output

Amplification (100mV--> full swing), Delay reduction (by increasing the swing),
Power reduction (through small bit line swing), Signal restoration (full swing)
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Differential Sense Amplifier

VDD

M3 M4
y Out

bit M1 M2 bit

SE M5
𝐴' = 𝑔(&(𝑟)*||𝑟)+)
Directly applicable to
SRAMs

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Slew limited case

VDD

𝑑𝑉 𝐼,,
M3 M4 =
y
𝑑𝑡 𝐶)-.

𝐶)-. ∆𝑉)-.
bit M1 M2 bit ∆𝜏 =
𝐼,,

P=𝐼,, 𝑉//
SE M5 ISS
Large Iss for speed up but
trades off exists

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Differential Sensing ― SRAM

1. Precharge & EQ before readà ensure

V DD V DD no difference in bit lines
PC 2. One of the bit line becomes low (not full
swing due to PMOS load à saves
precharge time)
BL BL V DD V DD
EQ
y M3 M4 𝑦2y
𝑥
WL i
x M1 M2 2x x 𝑥
2x

SE M5 SE

SE
SRAM cell i

V DD
Diff.
x Sense 2x Output
Amp y

SE
Output
(a) SRAM sensing scheme

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Latch-Based Sense Amplifier (DRAM)

EQ
BL BL
VDD

SE

SE

Initialized in its meta-stable point with EQ

Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.
Full swing required for refresh and write
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Charge-Redistribution Amplifier

Vref

VL VS
M1

C small
M2 M3 C large

Transient Response

Concept

Initial: VS=VDD, VL=Vref-VTn

M2 turns on à VL drops à VL=VS (due to
charge redistribution)
Large Vs change (like an amplifier)

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Single-to-differential conversion

WL
BL 2x
x
Diff.
1
Cell S.A. 2
V ref

Output

How to make a good Vref?

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1-Transistor DRAM Cell

Write: C S is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.

𝐶, + 𝐶01 𝑉01 = 𝐶, 𝑉023 + 𝐶01 𝑉456 Typically CBL~10CS

𝐶,
𝑉01 − 𝑉456 = (𝑉023 − 𝑉456 )
𝐶, + 𝐶01
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Open bit line architecture with dummy cells

EQ

L L1 L0 VDD R0 R1 L
SE

BLL BLR

… …
CS CS CS CS CS CS
SE

Dummy cell Dummy cell

1. EQ high à precharge bit lines to VDD/2. &Charge

dummy cells to VDD/2.
2. one of the wl in the left toggles, L toggles too create
reference voltage & equal charge injection to bit lines
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Example

Column is precharged to VDD/2 and the internal dummy

cell voltage are also pre charged to VDD/2. Compute
voltage when reading a “1” and reading a ‘0”. Assume
boosted wordlines are used so the full VDD levels can be
store in each cell. Column capacitance is 10Cs.
7!!
+
𝐶8)9-(:+ 𝑉// 𝐶8699 = 𝑉; (𝐶8)9-(: + 𝐶8699 )
𝑉//
2 10𝐶 + 𝑉// 𝐶
𝑉; = = 0.55𝑉//
10𝐶 + 𝐶
7!!
𝐶8)9-(: + 0×𝐶8699 = 𝑉; (𝐶8)9-(: + 𝐶8699 )
+
𝑉//
2 10𝐶
𝑉; = = 0.45𝑉//
10𝐶 + 𝐶
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Open Bit-line Architecture —Cross Coupling

EQ

WL 1 WL 0 WL WL D WL 0 WL 1
C WBL D C WBL
BL BL
C BL Sense C BL
C C C Amplifier C C C

="#$
Bit line swing=∆<1
="#$ >=#$

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Folded-Bitline Architecture

WL 1 WL 1 WL 0 C WL 0 WL D WL D
WBL

BL C BL x y

… C C C Sense
C C C
EQ Amplifier

BL C BL x y
C WBL

Advantage in terms of noise suppresion but increases BL

length and associated capacitance

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Transposed-Bitline Architecture

C cross
BL 9
BL
SA
BL
BL 99
(a) Straightforward bit-line routing

C cross
BL 9
BL
SA
BL
BL 99

(b) Transposed bit-line architecture

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Alpha-particles (or Neutrons)

a -particle
WL VDD
BL
SiO 2
n1 1 2
1 2
2
1 2
1 2
1 2
1

1 Particle ~ 1 Million Carriers

Alpha particle: 2 neutron+2 proton
Sources: Universe (altitude dependent), radioactive material
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Noise Sources in 1T DRam

BL substrate Adjacent BL
CWBL
a -particles

WL

leakage
CS
electrode

Ccross

Soft error: No hardware problem but occurring error events

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Redundancy

Row
Redundant Address
rows
Fuse
:
Bank

Row Decoder
Redundant
columns
Memory
Array

Column Decoder Column

Address

Defective columns and rows are replaced by redundant ones

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Error-Correcting Codes

Example: Hamming Codes (3 parity and 4 bits)

e.g. B3 Wrong
with
1

1 =3

2$ ≥ 𝑚 + 𝑘 + 1 M: # of bits, k: check bits

For the correction of 128bits, at least 8 check bits are required

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Redundancy and Error Correction

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